ci: make emit_verilog bit-exactness a reproducible gate (CI-02) - #1869
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Turns last cycle's one-off proof into an invariant. tools/verify_emit_bitexact.py
regenerates the GF-T cores fresh from their .t27 specs (via t27c, per L2 GENERATION
-- no hand-committed gen/), emits the microsequencer for hidden widths {2,3,4,5},
and cross-checks yout u32 per step in Icarus Verilog over an 80-step training run
(forward+backprop+update). Self-contained and CI-friendly: SKIPs cleanly (exit 0)
when iverilog or t27c is absent so it never breaks Rust-only CI; a real spec->RTL
divergence exits 1.
New workflow emit-bitexact-gate.yml builds t27c, installs iverilog, and runs the
gate on any PR touching the trainer generator or the GF-T core specs (runs on this
PR -- self-validating). A future regression now fails in CI instead of silently
miscomputing on silicon.
Refs #1764
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Turns last cycle's one-off bit-exact proof into an invariant.
tools/verify_emit_bitexact.pyregenerates the GF-T cores fresh from their .t27 specs (via t27c, per L2 GENERATION), emits the microsequencer for hidden widths {2,3,4,5}, and cross-checksyoutu32 per step in Icarus Verilog over an 80-step training run. Self-contained + CI-friendly: SKIPs (exit 0) when iverilog/t27c absent so it never breaks Rust-only CI; a real spec→RTL divergence exits 1.New workflow
emit-bitexact-gate.yml(CI-02) builds t27c, installs iverilog, runs the gate on any PR touching the trainer generator or GF-T core specs — runs on this PR (self-validating). A future regression now fails in CI instead of silently miscomputing on silicon. Refs #1764