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verify: emit_verilog RTL is bit-exact vs the GF-T model + fix latent multi-output bug - #1868

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verify: emit_verilog RTL is bit-exact vs the GF-T model + fix latent multi-output bug#1868
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@gHashTag gHashTag commented Aug 7, 2026

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Closed a gap in the spec->Verilog bit-exact thesis: emit_verilog was only smoke-checked, never simulated against the model. An iverilog harness seeds the model from the RTL's own init lines, streams the same training sequence through both, and compares yout u32 per step — RTL == model BIT-EXACT over 80 training steps for hidden widths {2,3,4,5} (forward+backprop+update all bit-identical).

The cross-check exposed a latent multi-output bug: t1.. was read as uninitialized x in RTL vs 0 in the model (the x0i/x1i/ti port shape only carries 2 inputs + 1 target). Fixed honestly: emit_verilog asserts n_in=2,n_out=1 (hidden width is the free programmable-size axis) and zero-inits the whole register file on reset. Python self-tests still green; added guard + zero-init assertions. Refs #1764

…multi-output bug

Closed a gap in the spec->Verilog bit-exact thesis: emit_verilog was only
smoke-checked, never cross-checked against the model in a simulator. An iverilog
harness now seeds the model from the RTL's own init lines, streams the same
training sequence through both, and compares yout u32 per step -- RTL == model
BIT-EXACT over 80 training steps for hidden widths {2,3,4,5} (forward+backprop
+update all bit-identical).

The cross-check exposed a latent multi-output bug: t1.. was read as uninitialized
x in RTL vs 0 in the model (the x0i/x1i/ti port shape only carries 2 inputs +
1 target). Fixed: emit_verilog asserts n_in=2,n_out=1 (hidden width is the free
programmable-size axis) and zero-inits the whole register file on reset so RTL
matches the model structurally with no x-propagation. Python self-tests still
green; added guard + zero-init assertions.

Refs #1764

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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PR Dashboard

Generated at: 2026-08-07 12:40:30 UTC

Summary

Status Count
Total Open PRs 12
PRs with Failing Checks 0
PRs with All Checks Green 12
READY 5
FAILING 0
PENDING 0

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  • ⚠️ STALE -- sha256(compiler.rs)=4c1aaad5309a != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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gHashTag merged commit 2d372a9 into master Aug 7, 2026
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gHashTag deleted the feat/emit-bitexact-verify branch August 7, 2026 12:41
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