feat: emit_verilog for the GF-T backprop microsequencer (programmable trainer) - #1865
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tools/gft_backprop_microcode.py gains emit_verilog(n_in,n_hid,n_out,modname) -- emits a synthesizable microsequencer module (register file + case(pc) ROM) for any 2-layer net, completing topology -> microcode -> buildable Verilog. Self-test PASS. Measured: the (2,3,1) net (3 hidden, 43 steps) builds to fasm 2.92M -- essentially identical to the (2,2,1) XOR net's 2.93M, Max 20.69 MHz PASS. The datapath is fixed; bigger nets grow only the register file + microcode (= time, not area). Arbitrary 2-layer nets build to ~2.9M bitstreams, deep under the ~17M ceiling => a programmable ternary NN trainer where network size costs time, not FPGA area. Build with synth_xilinx -nocarry. Refs #1764 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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tools/gft_backprop_microcode.py gains emit_verilog(n_in,n_hid,n_out) — emits a synthesizable microsequencer module for any 2-layer net, completing topology -> microcode -> buildable Verilog. Self-test PASS. Measured: the (2,3,1) net builds to fasm 2.92M — essentially identical to the (2,2,1) XOR net's 2.93M (datapath fixed; bigger nets grow only register file + microcode = time, not area). A programmable ternary NN trainer where network size costs time, not FPGA area. Build with -nocarry. docs/NOW.md updated. Refs #1764