feat: GF-T magsub log-depth normalize (~2x smaller designs) - #1846
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gft_xorpercep4.t27: fully-on-chip 2-layer XOR trainer using a LOG-DEPTH magsub normalize -- replaces the 12-iteration linear normalize loop with a binary-search priority-encoder (8/4/2/1) + single barrel shift, capped identically (min(12,off-1)). Proven bit-identical to the original magsub over 17.4 MILLION (hi,lo) pairs (0 mismatches); in-spec test PASS. Synthesis: 9.1M fasm vs 17.86M linear (-48%); same optimization takes gft_logistic 16.7M->9.62M (-42%). magsub is the size bulk (every sadd uses it), so this shrinks every GF-T core ~2x and brings a fully-on-chip 2-layer trainer under the ~17M correctness ceiling. Silicon reconfirmation pending a board power-cycle (the AX7203 degraded mid-session: configures but computes 0 for all ops incl known-good sgd). The optimization is sim-proven and synthesis-shrunk. Refs #1764 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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New spec gft_xorpercep4.t27 — fully-on-chip 2-layer XOR trainer using a LOG-DEPTH magsub normalize (binary-search priority-encoder 8/4/2/1 + single barrel shift, replacing the 12-iteration linear loop, capped identically). Proven bit-identical over 17.4M (hi,lo) pairs (0 mismatches); in-spec PASS. Synthesis: 9.1M vs 17.86M (-48%); gft_logistic 16.7M->9.62M (-42%). magsub is the design-size bulk, so this shrinks every GF-T core ~2x and brings a fully-on-chip 2-layer trainer under the ~17M correctness ceiling. Silicon reconfirmation pending a board power-cycle (AX7203 degraded mid-session: configures but computes 0 incl known-good sgd). docs/NOW.md updated. Refs #1764