feat: GF-T fully-on-chip 2-layer XOR trainer (perceptron output) - #1827
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gft_xorpercep.t27: fully-on-chip 2-layer XOR -- fixed hidden h=relu(Wx+c) computed on the FPGA + trainable perceptron output (pred=z>0, g=pred-y, v_j'=v_j-eta*g*h_j; no hard-sigmoid to stay small); returns (v0'<<32)|v1'. In-spec test PASS; GF-T Python sim converges XOR 4/4. Honest note: as one design (fasm 19.5M) it exceeds the openXC7 correctness ceiling -- silicon responds but never updates. This REFINES the ceiling to ~17-18M (works <=16.7M, fails >=19.5M). Working on-chip XOR path is the split (fixed hidden off-chip + output trained on the 16.7M logistic bitstream). docs/NOW.md updated. Refs #1764 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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New spec gft_xorpercep.t27 — fully-on-chip 2-layer XOR: fixed hidden relu features + trainable perceptron output (no hard-sigmoid). In-spec PASS; GF-T sim converges XOR 4/4. Honest note: as one design (19.5M) it exceeds the openXC7 correctness ceiling (silicon responds but never updates), which REFINES the ceiling to ~17-18M (works <=16.7M, fails >=19.5M). Working on-chip XOR = split (fixed hidden off-chip + output on the 16.7M logistic bitstream, cycle 53). docs/NOW.md updated. Refs #1764