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alpha: sign-extend memory-format displacement #3036

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fe25ea2
alpha: sign-extend memory-format displacement
Samin061 Aug 18, 2026
1539bf3
alpha: add inc patch for memory-format displacement sign extension
Samin061 Aug 26, 2026
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8 changes: 4 additions & 4 deletions arch/Alpha/AlphaGenDisassemblerTables.inc
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@Rot127 Rot127 Aug 26, 2026

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Please add a patch file in for that one in suite/auto-sync/inc_patches/

@Samin061 Samin061 Aug 26, 2026

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Added it as suite/auto-sync/inc_patches/Alpha/01_mem_disp_sign_extend.patch so the sign-extension survives a regen. Checked it applies cleanly with git apply --recount against the freshly generated .inc.

Original file line number Diff line number Diff line change
Expand Up @@ -733,7 +733,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
tmp = fieldname(insn, 21, 5); \
if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
tmp = fieldname(insn, 0, 16); \
MCOperand_CreateImm0(MI, tmp); \
MCOperand_CreateImm0(MI, (int16_t)tmp); \
tmp = fieldname(insn, 16, 5); \
if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
return S; \
Expand Down Expand Up @@ -871,15 +871,15 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
tmp = fieldname(insn, 21, 5); \
if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
tmp = fieldname(insn, 0, 16); \
MCOperand_CreateImm0(MI, tmp); \
MCOperand_CreateImm0(MI, (int16_t)tmp); \
tmp = fieldname(insn, 16, 5); \
if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
return S; \
case 23: \
tmp = fieldname(insn, 21, 5); \
if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
tmp = fieldname(insn, 0, 16); \
MCOperand_CreateImm0(MI, tmp); \
MCOperand_CreateImm0(MI, (int16_t)tmp); \
tmp = fieldname(insn, 16, 5); \
if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
return S; \
Expand All @@ -889,7 +889,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
tmp = fieldname(insn, 21, 5); \
if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
tmp = fieldname(insn, 0, 16); \
MCOperand_CreateImm0(MI, tmp); \
MCOperand_CreateImm0(MI, (int16_t)tmp); \
tmp = fieldname(insn, 16, 5); \
if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
return S; \
Expand Down
40 changes: 40 additions & 0 deletions suite/auto-sync/inc_patches/Alpha/01_mem_disp_sign_extend.patch
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Original file line number Diff line number Diff line change
@@ -0,0 +1,40 @@
diff --git a/arch/Alpha/AlphaGenDisassemblerTables.inc b/arch/Alpha/AlphaGenDisassemblerTables.inc
index a35b974..6441634 100644
--- a/arch/Alpha/AlphaGenDisassemblerTables.inc
+++ b/arch/Alpha/AlphaGenDisassemblerTables.inc
@@ -733,7 +733,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
tmp = fieldname(insn, 21, 5); \
if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
tmp = fieldname(insn, 0, 16); \
- MCOperand_CreateImm0(MI, tmp); \
+ MCOperand_CreateImm0(MI, (int16_t)tmp); \
tmp = fieldname(insn, 16, 5); \
if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
return S; \
@@ -871,7 +871,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
tmp = fieldname(insn, 21, 5); \
if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
tmp = fieldname(insn, 0, 16); \
- MCOperand_CreateImm0(MI, tmp); \
+ MCOperand_CreateImm0(MI, (int16_t)tmp); \
tmp = fieldname(insn, 16, 5); \
if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
return S; \
@@ -879,7 +879,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
tmp = fieldname(insn, 21, 5); \
if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
tmp = fieldname(insn, 0, 16); \
- MCOperand_CreateImm0(MI, tmp); \
+ MCOperand_CreateImm0(MI, (int16_t)tmp); \
tmp = fieldname(insn, 16, 5); \
if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
return S; \
@@ -889,7 +889,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
tmp = fieldname(insn, 21, 5); \
if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
tmp = fieldname(insn, 0, 16); \
- MCOperand_CreateImm0(MI, tmp); \
+ MCOperand_CreateImm0(MI, (int16_t)tmp); \
tmp = fieldname(insn, 16, 5); \
if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \
return S; \
54 changes: 54 additions & 0 deletions tests/MC/Alpha/insn-alpha.s.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -2015,3 +2015,57 @@ test_cases:
insns:
-
asm_text: "rs $1"
-
input:
bytes: [ 0xb0, 0xb0, 0x42, 0x20 ]
arch: "CS_ARCH_ALPHA"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "lda $2,-0x4f50($2)"
-
input:
bytes: [ 0xf0, 0xff, 0x22, 0xa4 ]
arch: "CS_ARCH_ALPHA"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ldq $1,-0x10($2)"
-
input:
bytes: [ 0xf0, 0xff, 0x22, 0xb4 ]
arch: "CS_ARCH_ALPHA"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "stq $1,-0x10($2)"
-
input:
bytes: [ 0xff, 0xff, 0x22, 0x88 ]
arch: "CS_ARCH_ALPHA"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "lds $f1,-1($2)"
-
input:
bytes: [ 0xff, 0xff, 0x22, 0x9c ]
arch: "CS_ARCH_ALPHA"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "stt $f1,-1($2)"
-
input:
bytes: [ 0xf0, 0xff, 0x22, 0xb8 ]
arch: "CS_ARCH_ALPHA"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "stl_c $1,-0x10($2)"
8 changes: 4 additions & 4 deletions tests/details/alpha.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ test_cases:
type: ALPHA_OP_REG
reg: $29
-
asm_text: "lda $30,0xffd0($30)"
asm_text: "lda $30,-0x30($30)"
details:
regs_read: [ $30 ]
regs_write: [ $28, $30 ]
Expand All @@ -51,7 +51,7 @@ test_cases:
reg: $30
-
type: ALPHA_OP_IMM
imm: 0xffd0
imm: -0x30
-
type: ALPHA_OP_REG
reg: $30
Expand Down Expand Up @@ -112,7 +112,7 @@ test_cases:
type: ALPHA_OP_REG
reg: $29
-
asm_text: "lda $30,0xffd0($30)"
asm_text: "lda $30,-0x30($30)"
details:
regs_read: [ $30 ]
regs_write: [ $28, $30 ]
Expand All @@ -123,7 +123,7 @@ test_cases:
reg: $30
-
type: ALPHA_OP_IMM
imm: 0xffd0
imm: -0x30
-
type: ALPHA_OP_REG
reg: $30
Expand Down
8 changes: 4 additions & 4 deletions tests/details/cs_common_details.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -1228,9 +1228,9 @@ test_cases:
details:
regs_impl_write: [ $28 ]
-
asm_text: "lda $30,0xffd0($30)"
asm_text: "lda $30,-0x30($30)"
mnemonic: "lda"
op_str: "$30,0xffd0($30)"
op_str: "$30,-0x30($30)"
details:
regs_impl_write: [ $28 ]
-
Expand Down Expand Up @@ -1261,9 +1261,9 @@ test_cases:
details:
regs_impl_write: [ $28 ]
-
asm_text: "lda $30,0xffd0($30)"
asm_text: "lda $30,-0x30($30)"
mnemonic: "lda"
op_str: "$30,0xffd0($30)"
op_str: "$30,-0x30($30)"
details:
regs_impl_write: [ $28 ]
-
Expand Down
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