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arch/arm/stm32h7: fix the period of the PPS output - #20236

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acassis merged 1 commit into
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daniel-p-carvalho:fix/stm32h7-pps-interval
Sep 22, 2026
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acassis merged 1 commit into
apache:masterfrom
daniel-p-carvalho:fix/stm32h7-pps-interval

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Summary

The pulse-per-second output of the STM32H7 Ethernet MAC (STM32_ETH_PTP_GPIO, added in #20212) is a pulse train with a period of one second, started at a whole second of the system time. The driver programmed the interval and the width of the train as the number of increments of the system time minus one, but the MAC takes the values as they are. Each period was one increment (10 ns with HCLK at 200 MHz) shorter than a second, so the pulses came 10 ns early each second, about 36 us in an hour, and the output drifted away from the system time that the PTP daemon steers.

This PR programs the interval and the width without subtracting one.

Impact

  • One line each in the two constants of the PPS output, and the comment above them. It is only built with STM32_ETH_PTP_GPIO, which no board of the tree selects yet, so no existing configuration changes.

Testing

Built for a custom board with an STM32H753 and a DP83848 PHY, with STM32_ETH_PTP, STM32_ETH_PTP_GPIO and PTP_CLOCK, on the current master, without errors or warnings. ./tools/checkpatch.sh -g upstream/master..HEAD passes.

On hardware, against a GNSS-referenced ptp4l grandmaster, with ptpd from apache/nuttx-apps#3782 steering the system time of the MAC (the phase difference measured by the daemon was 0.9 to 1.0 us on average, without a trend, in both runs). The phase of the PPS edge against the system time was sampled every minute:

  • Before the change, in a run of 8.2 hours the pulse moved 0.29 ms ahead of the system time, which is 9.8 ns per second, and an oscilloscope showed the same shift against the grandmaster.
  • After the change, in a run of 11 hours (708 samples) the phase had a trend of -1.1 us per hour, within about 3 us per hour of uncertainty for samples with 1 ms of resolution, that is a drift smaller than 1 ppb.
  • The registers were read back as 100000000 and 50000000.

The interval and the width of the pulse train of the PPS output were
programmed as the number of increments of the system time minus one,
but the MAC takes them as they are. Each period was one increment (10 ns
with HCLK at 200 MHz) shorter than a second, so the pulses came 10 ns
early each second, about 36 us in an hour, and the output drifted away
from the system time.

Program the interval and the width without subtracting one.

On a run of 8.2 hours against a grandmaster clock the pulse moved 0.29 ms
ahead of the system time, which is 10 ns per second, while the system time
stayed within 1 us of the grandmaster. With the change, a run of 11 hours
showed no drift of the pulse against the system time, within 3 us per hour
on samples of 1 ms of resolution.

Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
Assisted-by: Claude:claude-sonnet-5
@github-actions github-actions Bot added Arch: arm Issues related to ARM (32-bit) architecture Size: XS The size of the change in this PR is very small labels Sep 21, 2026
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MemBrowse Memory Report

No memory changes detected for:

@acassis
acassis merged commit 1f9793b into apache:master Sep 22, 2026
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Arch: arm Issues related to ARM (32-bit) architecture Size: XS The size of the change in this PR is very small

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3 participants