arch/arm/stm32: implement PTP hardware clock driver (/dev/ptp0) - #20180
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please fix: |
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Every other timer driver block in this Make.defs sets TMRDEPPATH and TMRVPATH so DEPPATH/VPATH include this directory. CONFIG_PTP_CLOCK and CONFIG_PTP_CLOCK_DUMMY were the only two missing it, leaving ptp_clock.c/ptp_clock_dummy.c unreachable via VPATH and without a generated dependency file when no other timer driver in this file is also selected. Assisted-by: Claude:claude-sonnet-5 Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com> (cherry picked from commit 6d38122)
stm32_receive() called pkt_input() before stm32_eth_ptp_convert_rxtime(), so every packet handed to a packet socket carried the previous frame's RX timestamp instead of its own in dev->d_rxtime. Reorder so the timestamp is converted first. Assisted-by: Claude:claude-sonnet-5 Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com> (cherry picked from commit 9bfa20d)
Set ETH_MACCR_ROD unconditionally when configuring the MAC. In half-duplex mode the MAC otherwise reflects every frame it transmits back to its own receiver, flooding the receive path with our own traffic right as a genuine reply arrives. The bit has no effect in full-duplex (confirmed on our hardware: fduplex=1), so setting it unconditionally is safe and changes nothing observable for boards already running full-duplex. The sibling stm32f7 driver has the same gap (ETH_MACCR_ROD cleared but never set) and stm32h7's equivalent ETH_MACCR_DO bit has the same issue; both are left out of scope here since only m3m4_v1 hardware was available to validate against. Assisted-by: Claude:claude-sonnet-5 Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com> (cherry picked from commit 41536cb)
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The MAC hardware counter is the PTP clock reference. Delivering its raw timestamp directly (instead of synthesizing one against CLOCK_REALTIME, which starts at an arbitrary boot-time phase) lets the PTP daemon close the feedback loop and phase-lock the MAC counter - and therefore the physical PPS output - to the master. Assisted-by: Gemini:gemini-3.8-flash-medium Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
Implement lower-half PTP hardware clock operations (struct ptp_lowerhalf_s and struct ptp_ops_s) in the STM32 Ethernet driver and register it with the generic PTP clock framework (drivers/timers/ptp_clock.c) to expose /dev/ptp0. Supported operations: - adjfine: adjust PTP clock frequency in parts per billion (ppb) - adjphase: adjust PTP clock phase via hardware TSSTU - adjtime: shift PTP clock time by signed delta in nanoseconds - gettime: atomic double-read of hardware timestamp registers - settime: initialize hardware timestamp counter via TSSTI - getres: return 1 ns clock resolution Also fix a sign bug in stm32_eth_ptp_adjust() where uint64_t addend promoted negative ppb adjustments to unsigned, corrupting frequency trim for crystals running faster than nominal. Follow-up to apache#20148 per review recommendation to use the standard POSIX /dev/ptp0 character driver instead of custom socket ioctls. Assisted-by: Gemini:gemini-3.8-pro Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
Variable conn is declared and initialized in append_timestamping() but never referenced, triggering -Wunused-variable compiler warning. Assisted-by: Gemini:gemini-3.8-pro Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
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Heads-up for ordering: #20148 (hardware TX timestamping for the STM32 MAC) is now rebased on top of this PR and depends on it, so it has to be merged after this one. It is a draft until then. |
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Summary
This PR implements lower-half PTP hardware clock operations (
struct ptp_lowerhalf_sandstruct ptp_ops_s) in the STM32 Ethernet driver (arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c) and registers it with the generic PTP clock framework (drivers/timers/ptp_clock.c) to expose the standard POSIX character driver/dev/ptp0.Supported operations:
adjfine: adjust PTP clock frequency in parts per billion (ppb) via the addend register (PTPTSAR)adjphase: adjust PTP clock phase via hardwareTSSTUadjtime: shift PTP clock time by signed delta in nanosecondsgettime: atomic double-read of hardware timestamp counter with second rollover handlingsettime: initialize/jump hardware timestamp counter viaTSSTIgetres: report 1 ns clock resolutionIt also includes necessary fixes to support hardware PTP clock operation:
d_rxtimestampso the PTP servo can close the feedback loop against the master clock.stm32_eth_ptp_convert_rxtime()runs beforepkt_input().stm32_eth_ptp_adjust()whereuint64_t addendpromoted negative ppb adjustments to unsigned, corrupting frequency trim for crystals running fast.TMRDEPPATH/TMRVPATHfor PTP clock drivers indrivers/timers/Make.defs.ETH_MACCR_RODto disable reception of self-transmitted frames.Follow-up to #20148 per @xiaoxiang781216's review suggestion to replace custom socket ioctls (
SIOCS_PTP_ADJFREQ,SIOCS_PTP_ADJPHASE) with the standard POSIX character driver/dev/ptp0. Hardware transmit timestamping will follow in a separate PR aligned with #20161 (SO_TIMESTAMPING).Impact
Enables standard POSIX hardware clock disciplining via
clock_adjtime()on/dev/ptp0on STM32 Ethernet interfaces. Fully compatible withptpd -p /dev/ptp0.Testing
Tested on real hardware (
stm32f4discovery-ext:ethraw/ STM32F407) connected via L2 Ethernet P2P to a GNSS-referenced PTP Grandmaster (IEC/IEEE 61850-9-3 profile):Running
ptpd -2 -s -p /dev/ptp0 -B -H -P -i eth0:Phase locked to -383 ns residual error with crystal drift disciplined at -82636 ppb.