arch/arm/stm32h5: Add OTP support

Documentation/platforms/arm/stm32h5/index.rst

@@ -83,6 +83,7 @@ TAMP        No
 UCPD        No
 VREFBUF     No
 WWDG        Yes
+OTP         Yes
 
 ==========  =======  =====
 
@@ -106,6 +107,34 @@ Options:
 
 - STM32H5_USBDRD_DESCSIZE - Maximum size of a descriptor.  Default: 128
 
+OTP
+---
+
+STM32H5 parts have a 2 KiB one-time programmable (OTP) area. It's organized
+into 32 blocks of 32 16-bit words. Each word can be successfully programmed once.
+Each block may be permanently locked at any point. Written words may be read.
+
+Writing the same word more than once is unsupported. Doing so may cause corruption.
+Reading an unwritten word raises an exception.
+To simplify the programming model, the OTP API
+locks blocks after any part is written. The user may check which blocks are locked.
+Blocks are tagged as "written" using this lock status
+without the need for out-of-band metadata. Some of the words within a locked
+block may be left unwritten, so the exception may still be raised if an unwritten word
+within a locked block is read.
+
+.. code:: c
+
+   int stm32_otp_write(const uint16_t *data, uint16_t len, uint32_t offset);
+   int stm32_otp_read(uint16_t *data, uint16_t len, uint32_t offset);
+   uint32_t stm32_otp_getlockstatus(void);
+
+The API allows cross-block reads/writes that don't necessarily start/end at block boundaries.
+Any block affected by ``stm32_otp_write`` will be locked. The user should be aware
+of the block size and count when partitioning the OTP area for their needs.
+``len`` is the number of bytes - not words. It has no alignment requirement. ``offset`` is
+the offset in bytes. It must be a multiple of 4.
+
 References
 =================
 [RM0481] Reference Manual: STM32H523/33xx, STM32H562/63xx, and STM32H573xx Arm® -based 32-bit MCUs

arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h

@@ -64,6 +64,10 @@
 #define STM32_SYSMEM_FSIZE   0x08FFF80C     /* Size of Flash memory in Kbytes. */
 #define STM32_SYSMEM_PACKAGE 0x08FFF80E     /* Indicates the device's package type. */
 
+/* OTP Base Addresses *******************************************************/
+
+#define STM32_OTP_BASE       0x08fff000     /* Base address of OTP Area */
+
 /* Peripheral Base Addresses ************************************************/
 
 #define STM32_APB1_BASE      0x40000000     /* 0x40000000-0x4000fbff: APB1 */

arch/arm/src/stm32h5/stm32_flash.h

@@ -56,6 +56,12 @@ void stm32_flash_lock(void);
 
 void stm32_flash_unlock(void);
 
+int stm32_otp_write(const uint16_t *data, uint16_t len, uint32_t offset);
+
+int stm32_otp_read(uint16_t *data, uint16_t len, uint32_t offset);
+
+uint32_t stm32_otp_getlockstatus(void);
+
 #undef EXTERN
 #if defined(__cplusplus)
 }