Skip to content

Latest commit

 

History

11 Commits

Folders and files

NameName
Last commit message
Last commit date
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

GateBench

Educational FPGA lab board for the UPduino v3.1. Switches, LEDs, 7-segment display, VGA, R-2R DAC, ADC and WS2812 behind shift-register scan chains, with a Verilog BSP and worked examples.

About

Educational FPGA lab board for the UPduino v3.1. Switches, LEDs, 7-segment display, VGA, R-2R DAC, ADC and WS2812 behind shift-register scan chains, with a Verilog BSP and worked examples.

Topics

Resources

Stars

0 stars

Watchers

0 watching

Forks

Releases

Contributors