Skip to content

First attempt at integrating svsch#263

Draft
TheDeepestSpace wants to merge 1 commit into
mainfrom
boris/svsch
Draft

First attempt at integrating svsch#263
TheDeepestSpace wants to merge 1 commit into
mainfrom
boris/svsch

Conversation

@TheDeepestSpace

@TheDeepestSpace TheDeepestSpace commented Jul 6, 2026

Copy link
Copy Markdown
Member

No description provided.

@TheDeepestSpace TheDeepestSpace self-assigned this Jul 6, 2026
@github-actions

github-actions Bot commented Jul 6, 2026

Copy link
Copy Markdown

🔧 DE1-SoC Synthesis Report Summary Diff

  • RV32I

    1. Fitter Summary
      No baseline available from main branch

      View PR synthesis results 
      Fitter Status : Successful - Mon Jul  6 01:28:48 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : utoss-risc-v
Top-level Entity Name : top
Family : Cyclone V
Device : 5CSEMA5F31C6
Timing Models : Final
Logic utilization (in ALMs) : 1,552 / 32,070 ( 5 % )
Total registers : 1569
Total pins : 15 / 457 ( 3 % )
Total virtual pins : 0
Total block memory bits : 32,768 / 4,065,280 ( < 1 % )
Total RAM Blocks : 8 / 397 ( 2 % )
Total DSP Blocks : 0 / 87 ( 0 % )
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI PMA TX Serializers : 0
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 4 ( 0 % )

    2. Fitter by entity
      No baseline available from main branch

      View PR synthesis results 
      Compilation Hierarchy Node                        ALMs needed [=A-B+C]  [A] ALMs used in final placement  [B] Estimate of ALMs recoverable by dense packing  [C] Estimate of ALMs unavailable  ALMs used for memory  Combinational ALUTs  Dedicated Logic Registers  I/O Registers  Block Memory Bits  M10Ks  DSP Blocks  Pins  Virtual Pins  Full Hierarchy Name                                                                                                Entity Name         Library Name
|top                                              1552.0 (0.5)          1700.0 (0.5)                      178.5 (0.0)                                        30.5 (0.0)                        0.0 (0.0)             1840 (1)             1569 (0)                   0 (0)          32768              8      0           15    0             |top                                                                                                               top                 work
   |memory_map:memory_map|                        10.0 (10.0)           11.8 (11.8)                       1.8 (1.8)                                          0.0 (0.0)                         0.0 (0.0)             13 (13)              13 (13)                    0 (0)          32768              8      0           0     0             |top|memory_map:memory_map                                                                                         memory_map          work
      |altsyncram:M0_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0                                                                     altsyncram          work
         |altsyncram_9hp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0|altsyncram_9hp1:auto_generated                                      altsyncram_9hp1     work
      |altsyncram:M0_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_1                                                                     altsyncram          work
         |altsyncram_9hp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_1|altsyncram_9hp1:auto_generated                                      altsyncram_9hp1     work
      |altsyncram:M1_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0                                                                     altsyncram          work
         |altsyncram_ahp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0|altsyncram_ahp1:auto_generated                                      altsyncram_ahp1     work
      |altsyncram:M1_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_1                                                                     altsyncram          work
         |altsyncram_ahp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_1|altsyncram_ahp1:auto_generated                                      altsyncram_ahp1     work
      |altsyncram:M2_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0                                                                     altsyncram          work
         |altsyncram_bhp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0|altsyncram_bhp1:auto_generated                                      altsyncram_bhp1     work
      |altsyncram:M2_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_1                                                                     altsyncram          work
         |altsyncram_bhp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_1|altsyncram_bhp1:auto_generated                                      altsyncram_bhp1     work
      |altsyncram:M3_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0                                                                     altsyncram          work
         |altsyncram_chp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0|altsyncram_chp1:auto_generated                                      altsyncram_chp1     work
      |altsyncram:M3_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_1                                                                     altsyncram          work
         |altsyncram_chp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_1|altsyncram_chp1:auto_generated                                      altsyncram_chp1     work
   |utoss_riscv:core|                             1541.5 (629.2)        1687.7 (645.6)                    176.7 (30.3)                                       30.5 (14.0)                       0.0 (0.0)             1826 (749)           1556 (466)                 0 (0)          0                  0      0           0     0             |top|utoss_riscv:core                                                                                              utoss_riscv         work
      |decode_stage:u_decode_stage|               308.5 (3.3)           398.3 (3.6)                       91.6 (0.2)                                         1.7 (0.0)                         0.0 (0.0)             88 (8)               992 (0)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage                                                                  decode_stage        work
         |Instruction_Decode:instruction_decode|  12.7 (8.3)            13.2 (8.8)                        0.5 (0.5)                                          0.0 (0.0)                         0.0 (0.0)             31 (23)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|Instruction_Decode:instruction_decode                            Instruction_Decode  work
            |ALUdecoder:instanceALUDec|           4.3 (4.3)             4.3 (4.3)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             8 (8)                0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec  ALUdecoder          work
         |control_fsm:u_ctrl|                     3.4 (3.4)             3.4 (3.4)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             9 (9)                0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|control_fsm:u_ctrl                                               control_fsm         work
         |registerFile:RegFile|                   289.0 (289.0)         378.2 (378.2)                     90.8 (90.8)                                        1.7 (1.7)                         0.0 (0.0)             40 (40)              992 (992)                  0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|registerFile:RegFile                                             registerFile        work
      |execute_stage:u_execute_stage|             449.4 (95.0)          466.3 (102.1)                     28.7 (7.8)                                         11.9 (0.7)                        0.0 (0.0)             679 (178)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|execute_stage:u_execute_stage                                                                execute_stage       work
         |ALU:alu|                                354.4 (354.4)         364.2 (364.2)                     21.0 (21.0)                                        11.2 (11.2)                       0.0 (0.0)             501 (501)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|execute_stage:u_execute_stage|ALU:alu                                                        ALU                 work
      |fetch_stage:u_fetch_stage|                 72.9 (72.9)           91.5 (91.5)                       20.5 (20.5)                                        1.9 (1.9)                         0.0 (0.0)             125 (125)            97 (97)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|fetch_stage:u_fetch_stage                                                                    fetch_stage         work
      |hazard_unit:u_hazard_unit|                 7.1 (7.1)             8.3 (8.3)                         1.3 (1.3)                                          0.1 (0.1)                         0.0 (0.0)             15 (15)              1 (1)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|hazard_unit:u_hazard_unit                                                                    hazard_unit         work
      |memory_stage:u_memory_stage|               12.9 (12.9)           14.2 (14.2)                       1.7 (1.7)                                          0.4 (0.4)                         0.0 (0.0)             27 (27)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|memory_stage:u_memory_stage                                                                  memory_stage        work
      |write_back_stage:u_write_back_stage|       61.6 (60.2)           63.6 (62.1)                       2.6 (2.4)                                          0.6 (0.6)                         0.0 (0.0)             143 (141)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|write_back_stage:u_write_back_stage                                                          write_back_stage    work
         |MemoryLoader:memory_loader|             1.3 (1.3)             1.5 (1.5)                         0.2 (0.2)                                          0.0 (0.0)                         0.0 (0.0)             2 (2)                0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|write_back_stage:u_write_back_stage|MemoryLoader:memory_loader                               MemoryLoader        work

    3. Timing
      No baseline available from main branch

      View PR synthesis results 
      ------------------------------------------------------------
Timing Analyzer Summary
------------------------------------------------------------

Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
Slack : 2.419
TNS   : 0.000

Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
Slack : 0.293
TNS   : 0.000

Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.868
TNS   : 0.000

Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
Slack : 2.786
TNS   : 0.000

Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
Slack : 0.254
TNS   : 0.000

Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.826
TNS   : 0.000

Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
Slack : 9.385
TNS   : 0.000

Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
Slack : 0.198
TNS   : 0.000

Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.783
TNS   : 0.000

Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
Slack : 10.432
TNS   : 0.000

Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
Slack : 0.175
TNS   : 0.000

Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.777
TNS   : 0.000

------------------------------------------------------------

  • RV32IB

    1. Fitter Summary
      No baseline available from main branch

      View PR synthesis results 
      Fitter Status : Successful - Mon Jul  6 01:28:29 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : utoss-risc-v
Top-level Entity Name : top
Family : Cyclone V
Device : 5CSEMA5F31C6
Timing Models : Final
Logic utilization (in ALMs) : 1,552 / 32,070 ( 5 % )
Total registers : 1569
Total pins : 15 / 457 ( 3 % )
Total virtual pins : 0
Total block memory bits : 32,768 / 4,065,280 ( < 1 % )
Total RAM Blocks : 8 / 397 ( 2 % )
Total DSP Blocks : 0 / 87 ( 0 % )
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI PMA TX Serializers : 0
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 4 ( 0 % )

    2. Fitter by entity
      No baseline available from main branch

      View PR synthesis results 
      Compilation Hierarchy Node                        ALMs needed [=A-B+C]  [A] ALMs used in final placement  [B] Estimate of ALMs recoverable by dense packing  [C] Estimate of ALMs unavailable  ALMs used for memory  Combinational ALUTs  Dedicated Logic Registers  I/O Registers  Block Memory Bits  M10Ks  DSP Blocks  Pins  Virtual Pins  Full Hierarchy Name                                                                                                Entity Name         Library Name
|top                                              1552.0 (0.5)          1700.0 (0.5)                      178.5 (0.0)                                        30.5 (0.0)                        0.0 (0.0)             1840 (1)             1569 (0)                   0 (0)          32768              8      0           15    0             |top                                                                                                               top                 work
   |memory_map:memory_map|                        10.0 (10.0)           11.8 (11.8)                       1.8 (1.8)                                          0.0 (0.0)                         0.0 (0.0)             13 (13)              13 (13)                    0 (0)          32768              8      0           0     0             |top|memory_map:memory_map                                                                                         memory_map          work
      |altsyncram:M0_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0                                                                     altsyncram          work
         |altsyncram_9hp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0|altsyncram_9hp1:auto_generated                                      altsyncram_9hp1     work
      |altsyncram:M0_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_1                                                                     altsyncram          work
         |altsyncram_9hp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_1|altsyncram_9hp1:auto_generated                                      altsyncram_9hp1     work
      |altsyncram:M1_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0                                                                     altsyncram          work
         |altsyncram_ahp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0|altsyncram_ahp1:auto_generated                                      altsyncram_ahp1     work
      |altsyncram:M1_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_1                                                                     altsyncram          work
         |altsyncram_ahp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_1|altsyncram_ahp1:auto_generated                                      altsyncram_ahp1     work
      |altsyncram:M2_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0                                                                     altsyncram          work
         |altsyncram_bhp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0|altsyncram_bhp1:auto_generated                                      altsyncram_bhp1     work
      |altsyncram:M2_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_1                                                                     altsyncram          work
         |altsyncram_bhp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_1|altsyncram_bhp1:auto_generated                                      altsyncram_bhp1     work
      |altsyncram:M3_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0                                                                     altsyncram          work
         |altsyncram_chp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0|altsyncram_chp1:auto_generated                                      altsyncram_chp1     work
      |altsyncram:M3_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_1                                                                     altsyncram          work
         |altsyncram_chp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_1|altsyncram_chp1:auto_generated                                      altsyncram_chp1     work
   |utoss_riscv:core|                             1541.5 (629.2)        1687.7 (645.6)                    176.7 (30.3)                                       30.5 (14.0)                       0.0 (0.0)             1826 (749)           1556 (466)                 0 (0)          0                  0      0           0     0             |top|utoss_riscv:core                                                                                              utoss_riscv         work
      |decode_stage:u_decode_stage|               308.5 (3.3)           398.3 (3.6)                       91.6 (0.2)                                         1.7 (0.0)                         0.0 (0.0)             88 (8)               992 (0)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage                                                                  decode_stage        work
         |Instruction_Decode:instruction_decode|  12.7 (8.3)            13.2 (8.8)                        0.5 (0.5)                                          0.0 (0.0)                         0.0 (0.0)             31 (23)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|Instruction_Decode:instruction_decode                            Instruction_Decode  work
            |ALUdecoder:instanceALUDec|           4.3 (4.3)             4.3 (4.3)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             8 (8)                0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec  ALUdecoder          work
         |control_fsm:u_ctrl|                     3.4 (3.4)             3.4 (3.4)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             9 (9)                0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|control_fsm:u_ctrl                                               control_fsm         work
         |registerFile:RegFile|                   289.0 (289.0)         378.2 (378.2)                     90.8 (90.8)                                        1.7 (1.7)                         0.0 (0.0)             40 (40)              992 (992)                  0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|registerFile:RegFile                                             registerFile        work
      |execute_stage:u_execute_stage|             449.4 (95.0)          466.3 (102.1)                     28.7 (7.8)                                         11.9 (0.7)                        0.0 (0.0)             679 (178)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|execute_stage:u_execute_stage                                                                execute_stage       work
         |ALU:alu|                                354.4 (354.4)         364.2 (364.2)                     21.0 (21.0)                                        11.2 (11.2)                       0.0 (0.0)             501 (501)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|execute_stage:u_execute_stage|ALU:alu                                                        ALU                 work
      |fetch_stage:u_fetch_stage|                 72.9 (72.9)           91.5 (91.5)                       20.5 (20.5)                                        1.9 (1.9)                         0.0 (0.0)             125 (125)            97 (97)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|fetch_stage:u_fetch_stage                                                                    fetch_stage         work
      |hazard_unit:u_hazard_unit|                 7.1 (7.1)             8.3 (8.3)                         1.3 (1.3)                                          0.1 (0.1)                         0.0 (0.0)             15 (15)              1 (1)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|hazard_unit:u_hazard_unit                                                                    hazard_unit         work
      |memory_stage:u_memory_stage|               12.9 (12.9)           14.2 (14.2)                       1.7 (1.7)                                          0.4 (0.4)                         0.0 (0.0)             27 (27)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|memory_stage:u_memory_stage                                                                  memory_stage        work
      |write_back_stage:u_write_back_stage|       61.6 (60.2)           63.6 (62.1)                       2.6 (2.4)                                          0.6 (0.6)                         0.0 (0.0)             143 (141)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|write_back_stage:u_write_back_stage                                                          write_back_stage    work
         |MemoryLoader:memory_loader|             1.3 (1.3)             1.5 (1.5)                         0.2 (0.2)                                          0.0 (0.0)                         0.0 (0.0)             2 (2)                0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|write_back_stage:u_write_back_stage|MemoryLoader:memory_loader                               MemoryLoader        work

    3. Timing
      No baseline available from main branch

      View PR synthesis results 
      ------------------------------------------------------------
Timing Analyzer Summary
------------------------------------------------------------

Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
Slack : 2.419
TNS   : 0.000

Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
Slack : 0.293
TNS   : 0.000

Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.868
TNS   : 0.000

Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
Slack : 2.786
TNS   : 0.000

Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
Slack : 0.254
TNS   : 0.000

Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.826
TNS   : 0.000

Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
Slack : 9.385
TNS   : 0.000

Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
Slack : 0.198
TNS   : 0.000

Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.783
TNS   : 0.000

Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
Slack : 10.432
TNS   : 0.000

Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
Slack : 0.175
TNS   : 0.000

Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.777
TNS   : 0.000

------------------------------------------------------------

Comparing synthesis results from main branch vs. this PR

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

No reviews

Assignees

@TheDeepestSpace TheDeepestSpace

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

1 participant

@TheDeepestSpace