Coreless Ethernet switch SoC built on eswitch.
Part of the Tape-Out IP library: Bluespec IP over the
bus-neutral contracts in hwcore, assembled by
xirang. Maturity runs planned -> simulated ->
fpga-proven -> asic-ready -> silicon-proven.
Assembled from one eswitch instance with no RTL of its own. With no core on the chip, a management host configures the switch over the external APB4 port. ran test soc-switch runs the schedule gate and an end-to-end testbench that enables three of the four ports over that bus and checks where a broadcast and a unicast go.
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SPDX-License-Identifier: MIT OR Apache-2.0 OR MulanPSL-2.0
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