Olof Kindgren's SERV, the bit-serial RV32I core, taken as a black box.
Part of the Tape-Out IP library, wired up by
xirang. Two submodules, neither modified:
third_party/serv is the core, third_party/vlog_tb_utils is what its testbench depends on.
Every overridable parameter of serv_rf_top is a knob. CSR_REGS is not one of them —
it is a localparam, and passing it to the backend makes yosys fail with a message about
defparam that points nowhere near the real problem. RESET_STRATEGY is not one either:
Verilog has no string type, so "MINI" arrives as the integer 1296649801 and there is
nothing in the elaborated design to tell it apart from a number. It stays at its default,
and the manifest says so.
xirang resolves the knobs and bakes them into plain Verilog, because ecc and
yosys-sta read a file and a top module and cannot be handed parameters from outside.
$ ran wrap serv # 2456 lines, no parameters left
$ ran wrap serv -s w=4 -s compressed=true -s align=true # 3060 linesUpstream's servant_tb runs at every point of the parameter matrix. It needs no RISC-V
toolchain — SERV ships the firmware as a prebuilt hex.
The testbench exercises servant, the SoC wrapper, not serv_rf_top; its parameters have
different names. The manifest carries that mapping separately from the synthesis one, so
neither has to pretend to be the other.
Bit-serial: an instruction takes one cycle per w bits, which is the trade this core makes.
The MDU interface is declared but nothing drives it here.
This repository: 任选其一 MIT · Apache 2.0 · 木兰宽松许可证 第2版.
third_party/serv stays under ISC and third_party/vlog_tb_utils under its own terms;
see each one's licence file.