perf(amd): port MI355X Qwen3.5 MXFP4 disagg sweep to srt-slurm

[cquil11]

Summary

• replace the active MI355X Qwen3.5 MXFP4 legacy AMD disaggregated launcher with native srt-slurm orchestration
• preserve the production 1P1D TP8 topology and complete c8/c16/c32/c64/c128/c256/c512 8k1k search space
• use the current steady SGLang ROCm v0.5.17 image, SGLang Router, AMD MoRI, AITer attention, and FP8 KV cache
• call the repository's unchanged benchmark_serving.py directly through the custom benchmark contract
• remove the model-specific wrapper that only translated matrix fields into amd_utils/submit.sh

Validation

• srt-slurm dry-run passes against feat(runtime): add AMD accelerator support srt-slurm#1 at c609754b5622f96d5c12a93149e245308d4f1e9b
• Hugging Face model identity resolves and the pinned 64 GiB SGLang squashfs is already present on MI355X
• generated matrix contains exactly one topology job; the recipe owns all seven concurrency points
• changed YAML parses and git diff --check passes

Stack

Stacked on #2628 so the two Qwen3.5 ports share the same current srt-slurm launcher pin. This remains draft until the exact-head MI355X recipe sweep passes.

[github-actions]

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