Fixing LVS errors for diff_pair - #105
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Nimok15 lvs parser
Nimok15 lvs parser
Nimok15 lvs parser
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The p-cell was showing an extra top-level pin for which the label was present in GDS, but the net was internal in the reference netlist. Fixed the error for both. Added the with_pin_labels option to suppress unnecessary layout labels so that internal nets are not extracted as top-level ports. The layout-driven substrate_tap parameter ensures dummy transistors are tied to the bulk net whenever a substrate tap is present, matching the extracted layout for both sky130 and gf180, thereby eliminating dummy net LVS mismatches.