nxp-ran · Oct 30, 2026 · Oct 30, 2026 · Nov 2, 2026 · Nov 2, 2026 · Nov 2, 2026
@@ -182,7 +182,7 @@ CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
 CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y
-CONFIG_RT_VER_NUM=0x50300
+CONFIG_RT_VER_NUM=0x50400
 # CONFIG_RT_USING_STDC_ATOMIC is not set
 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
 # end of RT-Thread Kernel
@@ -468,6 +468,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ABUP_FOTA is not set
 # CONFIG_PKG_USING_LIBCURL2RTT is not set
 # CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_ERPC is not set
 # CONFIG_PKG_USING_AGILE_TELNET is not set
 # CONFIG_PKG_USING_NMEALIB is not set
 # CONFIG_PKG_USING_PDULIB is not set
@@ -583,12 +584,15 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_GUIENGINE is not set
 # CONFIG_PKG_USING_3GPP_AMRNB is not set
+# CONFIG_PKG_USING_LITETYPE is not set
 # end of multimedia packages
 
 #
 # tools packages
 #
 # CONFIG_PKG_USING_VECTOR is not set
+# CONFIG_PKG_USING_SORCH is not set
+# CONFIG_PKG_USING_DICT is not set
 # CONFIG_PKG_USING_CMBACKTRACE is not set
 # CONFIG_PKG_USING_MCOREDUMP is not set
 # CONFIG_PKG_USING_EASYFLASH is not set
@@ -640,6 +644,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_UORB is not set
 # CONFIG_PKG_USING_RT_TUNNEL is not set
 # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set
+# CONFIG_PKG_USING_FEE is not set
+# CONFIG_PKG_USING_MRAMTRACE is not set
 # end of tools packages
 
 #
@@ -735,6 +741,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_HEARTBEAT is not set
 # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
 # CONFIG_PKG_USING_CHERRYECAT is not set
+# CONFIG_PKG_USING_EVENT_LOOP is not set
+# CONFIG_PKG_USING_THREAD_MANAGER is not set
 # end of system packages
 
 #
@@ -786,6 +794,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set
 # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set
 # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set
 # end of STM32 HAL & SDK Drivers
 
 #
@@ -818,7 +828,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_NRFX is not set
 # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set
 # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
-# CONFIG_PKG_USING_MM32 is not set
+
+#
+# MM32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set
+# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set
+# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set
+# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set
+# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set
+# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set
+# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set
+# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set
+# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set
+# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set
+# end of MM32 HAL & SDK Drivers
 
 #
 # WCH HAL & SDK Drivers
@@ -883,9 +907,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
 #
 # NUVOTON Drivers
 #
-# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set
 # CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set
-# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set
 # end of NUVOTON Drivers
 
 #
@@ -903,6 +925,12 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
 # CONFIG_PKG_USING_HPM_SDK is not set
 # end of HPMicro SDK
 
+#
+# FM33 Drivers
+#
+# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set
+# end of FM33 Drivers
+
 #
 # FT32 HAL & SDK Drivers
 #
@@ -911,6 +939,23 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
 # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set
 # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set
 # end of FT32 HAL & SDK Drivers
+
+#
+# NOVOSNS Drivers
+#
+# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set
+# end of NOVOSNS Drivers
+
+#
+# N32 Drivers
+#
+# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set
+# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set
+# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set
+# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set
+# end of N32 Drivers
 # end of HAL & SDK Drivers
 
 #
@@ -990,6 +1035,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
 # CONFIG_PKG_USING_QMI8658 is not set
 # CONFIG_PKG_USING_ICM20948 is not set
 # CONFIG_PKG_USING_SCD4X is not set
+# CONFIG_PKG_USING_BMI270 is not set
 # end of sensors drivers
 
 #
@@ -1044,6 +1090,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
 # CONFIG_PKG_USING_WK2124 is not set
 # CONFIG_PKG_USING_LY68L6400 is not set
 # CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_CH390 is not set
 # CONFIG_PKG_USING_SSD1306 is not set
 # CONFIG_PKG_USING_QKEY is not set
 # CONFIG_PKG_USING_RS485 is not set
@@ -1091,8 +1138,10 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
 # CONFIG_PKG_USING_ISOTP_C is not set
 # CONFIG_PKG_USING_IKUNLED is not set
 # CONFIG_PKG_USING_INS5T8025 is not set
+# CONFIG_PKG_USING_IRUART is not set
 # CONFIG_PKG_USING_ST7305 is not set
 # CONFIG_PKG_USING_TM1668 is not set
+# CONFIG_PKG_USING_TCA9548A is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set
 # end of peripheral libraries and drivers
 
@@ -1110,6 +1159,9 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
 # CONFIG_PKG_USING_NAXOS is not set
 # CONFIG_PKG_USING_R_TINYMAIX is not set
 # CONFIG_PKG_USING_LLMCHAT is not set
+# CONFIG_PKG_USING_LIME_TM is not set
+# CONFIG_PKG_USING_AIFES is not set
+# CONFIG_PKG_USING_AGENT is not set
 # end of AI packages
 
 #
@@ -1169,6 +1221,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
 # CONFIG_PKG_USING_MULTIBUTTON is not set
 # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_CANOPENNODE is not set
 # CONFIG_PKG_USING_ZLIB is not set
 # CONFIG_PKG_USING_MINIZIP is not set
 # CONFIG_PKG_USING_HEATSHRINK is not set
@@ -1194,6 +1247,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
 # CONFIG_PKG_USING_QPARAM is not set
 # CONFIG_PKG_USING_CorevMCU_CLI is not set
 # CONFIG_PKG_USING_DRMP is not set
+# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set
 # end of miscellaneous packages
 
 #
@@ -1490,4 +1544,5 @@ CONFIG_BSP_LPUART1_TX_DMA_CHANNEL=1
 # CONFIG_BSP_LINKER_SCRIPT_RAM is not set
 CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR=y
 # CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM is not set
+# CONFIG_BSP_LINKER_SCRIPT_RAM_INDUSTRY is not set
 # end of Hardware Drivers Config
@@ -826,6 +826,14 @@ choice
         help
             Link the image to XIP from external NOR flash and use HyperRAM
             as additional RAM.
+
+    config BSP_LINKER_SCRIPT_RAM_INDUSTRY
+        bool "RAM - Industrial Ethernet (256KB TCM + 128KB OCRAM2 + 32KB shared memory)"
+        help
+            Link the image to run from 256KB TCM for industrial Ethernet
+            development. CM33 uses 128KB OCRAM2 exclusively and shares 32KB
+            OCRAM2 with CM7. The ARMCLANG scatter file (.scf) and the IAR
+            linker configuration file (.icf) are provided.
 endchoice
 
 endmenu
@@ -1498,8 +1498,8 @@ void PHY_Reset(void)
 void rt_hw_board_init()
 {
     extern void BOARD_InitPeripherals(void);
-    BOARD_CommonSetting();
     BOARD_ConfigMPU();
+    BOARD_CommonSetting();
     BOARD_InitBootPins();
     BOARD_BootClockRUN();
 //    BOARD_InitPeripherals();

@@ -0,0 +1,176 @@
+/*
+** ###################################################################
+**     Processors:          MIMXRT1189CVM8B_cm33
+**                          MIMXRT1189CVM8C_cm33
+**                          MIMXRT1189XVM8B_cm33
+**                          MIMXRT1189XVM8C_cm33
+**
+**     Compiler:            IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    IMXRT1180RM, Rev 5, 01/2024
+**     Version:             rev. 2.0, 2024-01-18
+**     Build:               b250310
+**
+**     Abstract:
+**         Linker file for the IAR ANSI C/C++ Compiler for ARM
+**         Industrial Ethernet configuration:
+**         - CM33 uses 256KB TCM only (128KB code TCM + 128KB system TCM),
+**           OCRAM1 is reserved for CM7.
+**         - CM33 uses 128KB OCRAM2 exclusively (64KB heap + 64KB non-cacheable data).
+**         - 32KB OCRAM2 is reserved as RPMsg shared memory.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2025 NXP
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Board memory map */
+
+define symbol m_code_tcm_start         = 0x0FFE0000;
+define symbol m_code_tcm_size          = 0x00020000;
+
+define symbol m_system_tcm_start       = 0x20000000;
+define symbol m_system_tcm_size        = 0x00020000;
+
+/* OCRAM1 is not used by CM33 in this configuration, it is reserved for CM7 */
+define symbol m_ocram2_start           = 0x20500000;
+define symbol m_ocram2_size            = 0x00040000;
+
+/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */
+define symbol m_sdram_start            = isdefinedsymbol(__dual_image__) ? 0x81E00000 : 0x80000000;
+define symbol m_sdram_size             = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x02000000;
+define symbol m_hyperram_start         = isdefinedsymbol(__dual_image__) ? 0x04600000 : 0x04000000;
+define symbol m_hyperram_size          = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x00800000;
+define symbol m_flash_start            = 0x28000000;
+define symbol m_flash_size             = 0x01000000;
+
+define symbol m_core1_image_maximum_size = 0x00040000;
+
+/* General definition */
+define symbol app_image_offset         = isdefinedsymbol(__dual_image__) ? 0x0010B000 : 0x0000B000;
+define symbol vector_table_size        = 0x00000400;
+if (isdefinedsymbol(__stack_size__)) {
+  define symbol __size_cstack__        = __stack_size__;
+} else {
+  define symbol __size_cstack__        = 0x01000;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+  define symbol __size_heap__          = __heap_size__;
+} else {
+  define symbol __size_heap__          = 0x10000;
+}
+
+define symbol m_qacode_start           = m_code_tcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0);
+define symbol m_qacode_end             = m_code_tcm_start + m_code_tcm_size - 1;
+define symbol m_qadata_start           = m_system_tcm_start;
+define symbol m_qadata_end             = m_system_tcm_start + m_system_tcm_size - 1;
+define symbol m_ram_vector_table_start = m_code_tcm_start;
+
+/* Target specific definition, code & data allocation */
+define symbol m_code_size              = m_code_tcm_size;
+define symbol m_data_size              = m_system_tcm_size;
+
+/* Industrial Ethernet configuration:
+ * CM33 only uses 256KB TCM and 128KB OCRAM2, plus 32KB OCRAM2 as shared memory.
+ * OCRAM2 layout (256KB @ 0x20500000):
+ *   [0x20500000, 0x2050FFFF]  64KB CM33 heap
+ *   [0x20510000, 0x2051FFFF]  64KB non-cacheable data (NCACHE)
+ *   [0x20520000, 0x20537FFF]  96KB reserved for CM7
+ *   [0x20538000, 0x2053FFFF]  32KB RPMsg shared memory
+ * NCACHE and shared memory sizes must be 2^N and the start addresses must be
+ * multiples of the size so that the MPU configuration in BOARD_ConfigMPU()
+ * stays valid.
+ */
+define symbol m_heap_start             = m_ocram2_start; /* 0x20500000 */
+
+if (isdefinedsymbol(__heap_noncacheable__)) {
+  /* heap is placed at the end of the non-cacheable region */
+  define symbol m_ncache_size          = 0x20000;        /* 128KB, must be 2^N */
+  define symbol m_ncache_start         = m_heap_start;
+} else {
+  define symbol m_ncache_size          = 0x10000;        /* 64KB, must be 2^N */
+  define symbol m_ncache_start         = m_heap_start + m_ncache_size; /* 0x20510000 */
+}
+define symbol m_ncache_end             = m_ncache_start + m_ncache_size - 1;
+define symbol m_heap_end               = m_ncache_start - 1;
+
+define symbol m_shmem_size             = 0x8000;         /* 32KB shared memory, must be 2^N */
+if (isdefinedsymbol(__use_shmem__)) {
+  define symbol m_rpmsg_sh_mem_start   = m_ocram2_start + m_ocram2_size - m_shmem_size; /* 0x20538000 */
+  define symbol m_rpmsg_sh_mem_end     = m_rpmsg_sh_mem_start + m_shmem_size - 1;
+}
+
+define symbol m_ram_vector_table_size  = isdefinedsymbol(__ram_vector_table__) ? 0 : 0;
+
+define symbol m_text_start             = m_code_tcm_start;
+define symbol m_text_end               = m_text_start + m_code_size - 1;
+define symbol m_interrupts_start       = m_text_start;
+
+define symbol m_data_start             = m_system_tcm_start;
+define symbol m_data_end               = m_data_start + m_data_size - 1;
+
+/* Exported symbol definition */
+define exported symbol __VECTOR_TABLE          = m_interrupts_start;
+define exported symbol __VECTOR_RAM            = m_ram_vector_table_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size;
+define exported symbol __NCACHE_REGION_START   = m_ncache_start;
+define exported symbol __NCACHE_REGION_SIZE    = m_ncache_end - m_ncache_start + 1;
+if (isdefinedsymbol(__use_shmem__)) {
+  define exported symbol rpmsg_sh_mem_start    = m_rpmsg_sh_mem_start;
+  define exported symbol rpmsg_sh_mem_end      = m_rpmsg_sh_mem_end;
+  define exported symbol __RPMSG_SH_MEM_START  = m_rpmsg_sh_mem_start;
+  define exported symbol __RPMSG_SH_MEM_SIZE   = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1;
+}
+
+/* Region definition */
+define memory mem with size = 4G;
+define region TEXT_region   = mem:[from m_text_start to m_text_end];
+define region DATA_region   = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
+define region HEAP_region   = mem:[from m_heap_start to m_heap_end];
+define region QACODE_region = mem:[from m_qacode_start to m_qacode_end];
+define region QADATA_region = mem:[from m_qadata_start to m_qadata_end];
+if (isdefinedsymbol(__use_shmem__)) {
+  define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end];
+}
+
+/* Block definition */
+define block RW            { readwrite };
+define block ZI            { zi };
+define block NCACHE_VAR    { section NonCacheable , section NonCacheable.init };
+define block QACCESS_CODE  { section CodeQuickAccess };
+define block QACCESS_DATA  { section DataQuickAccess };
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block CORE1_IMAGE_BLOCK  with alignment = 16, maximum size = m_core1_image_maximum_size  { section  __core1_image };
+
+initialize by copy { readwrite, section .textrw, section DataQuickAccess };
+do not initialize  { section .noinit };
+if (isdefinedsymbol(__use_shmem__)) {
+  do not initialize  { section rpmsg_sh_mem_section };
+}
+
+place at address mem: m_interrupts_start    { readonly section .intvec };
+
+place in TEXT_region                        { readonly };
+place in TEXT_region                        { block CORE1_IMAGE_BLOCK };
+place in TEXT_region                        {  block QACCESS_CODE };
+place in DATA_region                        { block RW };
+place in DATA_region                        { block ZI };
+place in DATA_region                        { block QACCESS_DATA };
+place in NCACHE_region                      { block NCACHE_VAR };
+place in CSTACK_region                      { block CSTACK };
+if (isdefinedsymbol(__heap_noncacheable__)) {
+  place in NCACHE_region                    { last block HEAP };
+} else {
+  place in HEAP_region                      { last block HEAP };
+}
+if (isdefinedsymbol(__use_shmem__)) {
+  place in rpmsg_sh_mem_region              { section rpmsg_sh_mem_section };
+}