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CipherCore – Hardware implementations of cryptographic cores.
- A curated collection of cryptographic keystream generators written in Verilog, serving as research artifacts and for industrial purposes, while providing reproducible flows to recreate everything mentioned in the reports using open-source tools.
open-eda-appimage – Unofficial packaging of EDA tools that don't provide pre-built binaries.
- An initiative to reduce the installation barrier for open-source EDA tools, specifically for easy grab-and-use or CI/CD pipelines.
SUBLEQ-CPU – A SUBLEQ CPU implemented in both Verilog and VHDL.
- This educational artifact demonstrates a SUBLEQ (Subtract and Branch if Less than or Equal to zero) CPU architecture. Both the Verilog and VHDL implementations have been validated against each other using formal equivalence checking, serving as a learning resource for digital design and formal verification techniques, and as a baseline for verification, assembler, program verifiers, and much more.
FABulous - FABulous: an Embedded FPGA Framework
- FABulous is an open-source embedded FPGA (eFPGA) framework for generating FPGA fabric and integrates the open source CAD tools Yosys and nextpnr for the user design flow. It is silicon-proven through multiple successful tapeouts across TSMC 180nm, Skywater 130nm, IHP SG13G2, GF180MCU, and 28nm CMOS, FABulous provides a full-stack toolchain from CSV-based fabric definition to production-ready GDSII. The framework supports frame-based partial reconfiguration for runtime reconfiguration of individual FPGA regions.
