Clang build for evbmips

crypto/external/apache2/openssl/dist/crypto/aes/asm/aes-mips.pl

@@ -110,6 +110,12 @@
 #include "mips_arch.h"
 
 .text
+.local	_mips_AES_encrypt
+.local	_mips_AES_decrypt
+.local	_mips_AES_set_encrypt_key
+.local	AES_Te
+.local	AES_Td
+.local	AES_Te4
 #if !defined(__mips_eabi) && (!defined(__vxworks) || defined(__pic__))
 .option	pic2
 #endif

crypto/external/apache2/openssl/dist/crypto/sha/asm/sha512-mips.pl

@@ -311,6 +311,7 @@ sub BODY_16_XX {
 #include "mips_arch.h"
 
 .text
+.local	K${label}
 .set	noat
 #if !defined(__mips_eabi) && (!defined(__vxworks) || defined(__pic__))
 .option	pic2

crypto/external/apache2/openssl/lib/libcrypto/arch/mips/aes-mips.S

@@ -1,6 +1,12 @@
 #include "mips_arch.h"
 
 .text
+.local	_mips_AES_encrypt
+.local	_mips_AES_decrypt
+.local	_mips_AES_set_encrypt_key
+.local	AES_Te
+.local	AES_Td
+.local	AES_Te4
 #if !defined(__mips_eabi) && (!defined(__vxworks) || defined(__pic__))
 .option	pic2
 #endif

crypto/external/apache2/openssl/lib/libcrypto/arch/mips/aes-mips64.S

@@ -1,6 +1,12 @@
 #include "mips_arch.h"
 
 .text
+.local	_mips_AES_encrypt
+.local	_mips_AES_decrypt
+.local	_mips_AES_set_encrypt_key
+.local	AES_Te
+.local	AES_Td
+.local	AES_Te4
 #if !defined(__mips_eabi) && (!defined(__vxworks) || defined(__pic__))
 .option	pic2
 #endif

crypto/external/apache2/openssl/lib/libcrypto/arch/mips/sha512-mips.S

@@ -1,6 +1,7 @@
 #include "mips_arch.h"
 
 .text
+.local	K256
 .set	noat
 #if !defined(__mips_eabi) && (!defined(__vxworks) || defined(__pic__))
 .option	pic2

crypto/external/apache2/openssl/lib/libcrypto/arch/mips/sha512-mips64.S

@@ -1,6 +1,7 @@
 #include "mips_arch.h"
 
 .text
+.local	K256
 .set	noat
 #if !defined(__mips_eabi) && (!defined(__vxworks) || defined(__pic__))
 .option	pic2

external/apache2/llvm/dist/clang/include/clang/Driver/Options.td

@@ -3460,6 +3460,9 @@ def mno_check_zero_division : Flag<["-"], "mno-check-zero-division">,
                               Group<m_mips_Features_Group>;
 def mcompact_branches_EQ : Joined<["-"], "mcompact-branches=">,
                            Group<m_mips_Features_Group>;
+foreach i = {1-31} in
+  def ffixed_#i : Flag<["-"], "ffixed-"#i>, Group<m_Group>,
+    HelpText<"Reserve the MIPS GPR "#i#" register (MIPS only)">;
 def mbranch_likely : Flag<["-"], "mbranch-likely">, Group<m_Group>,
   IgnoredGCCCompat;
 def mno_branch_likely : Flag<["-"], "mno-branch-likely">, Group<m_Group>,

external/apache2/llvm/dist/clang/lib/Basic/Targets/Mips.cpp

@@ -238,37 +238,12 @@ bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
     Diags.Report(diag::err_target_unsupported_cpu_for_micromips) << CPU;
     return false;
   }
-  // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
-  //        this yet. It's better to fail here than on the backend assertion.
-  if (processorSupportsGPR64() && ABI == "o32") {
-    Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
-    return false;
-  }
-
   // 64-bit ABI's require 64-bit CPU's.
   if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
     Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
     return false;
   }
 
-  // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
-  //        can't handle this yet. It's better to fail here than on the
-  //        backend assertion.
-  if (getTriple().isMIPS64() && ABI == "o32") {
-    Diags.Report(diag::err_target_unsupported_abi_for_triple)
-        << ABI << getTriple().str();
-    return false;
-  }
-
-  // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
-  //        can't handle this yet. It's better to fail here than on the
-  //        backend assertion.
-  if (getTriple().isMIPS32() && (ABI == "n32" || ABI == "n64")) {
-    Diags.Report(diag::err_target_unsupported_abi_for_triple)
-        << ABI << getTriple().str();
-    return false;
-  }
-
   // -fpxx is valid only for the o32 ABI
   if (FPMode == FPXX && (ABI == "n32" || ABI == "n64")) {
     Diags.Report(diag::err_unsupported_abi_for_opt) << "-mfpxx" << "o32";

external/apache2/llvm/dist/clang/lib/Driver/ToolChains/Arch/Mips.cpp

@@ -196,6 +196,44 @@ void mips::getMIPSTargetFeatures(const Driver &D, const llvm::Triple &Triple,
   getMipsCPUAndABI(Args, Triple, CPUName, ABIName);
   ABIName = getGnuCompatibleMipsABIName(ABIName);
 
+  // Handle features corresponding to GCC's -ffixed-REG options. MIPS spells
+  // its GPRs numerically, so preserve that spelling in the driver interface.
+#define RESERVE_GPR(REG)                                                       \
+  if (Args.hasArg(options::OPT_ffixed_##REG))                                  \
+    Features.push_back("+reserve-gpr" #REG);
+  RESERVE_GPR(1)
+  RESERVE_GPR(2)
+  RESERVE_GPR(3)
+  RESERVE_GPR(4)
+  RESERVE_GPR(5)
+  RESERVE_GPR(6)
+  RESERVE_GPR(7)
+  RESERVE_GPR(8)
+  RESERVE_GPR(9)
+  RESERVE_GPR(10)
+  RESERVE_GPR(11)
+  RESERVE_GPR(12)
+  RESERVE_GPR(13)
+  RESERVE_GPR(14)
+  RESERVE_GPR(15)
+  RESERVE_GPR(16)
+  RESERVE_GPR(17)
+  RESERVE_GPR(18)
+  RESERVE_GPR(19)
+  RESERVE_GPR(20)
+  RESERVE_GPR(21)
+  RESERVE_GPR(22)
+  RESERVE_GPR(23)
+  RESERVE_GPR(24)
+  RESERVE_GPR(25)
+  RESERVE_GPR(26)
+  RESERVE_GPR(27)
+  RESERVE_GPR(28)
+  RESERVE_GPR(29)
+  RESERVE_GPR(30)
+  RESERVE_GPR(31)
+#undef RESERVE_GPR
+
   // Historically, PIC code for MIPS was associated with -mabicalls, a.k.a
   // SVR4 abicalls. Static code does not use SVR4 calling sequences. An ABI
   // extension was developed by Richard Sandiford & Code Sourcery to support

external/apache2/llvm/dist/clang/lib/Driver/ToolChains/NetBSD.cpp

@@ -276,6 +276,10 @@ void netbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA,
     case llvm::Triple::armeb:
     case llvm::Triple::thumb:
     case llvm::Triple::thumbeb:
+    case llvm::Triple::mips:
+    case llvm::Triple::mipsel:
+    case llvm::Triple::mips64:
+    case llvm::Triple::mips64el:
     case llvm::Triple::ppc:
     case llvm::Triple::ppc64:
     case llvm::Triple::ppc64le:
@@ -414,6 +418,10 @@ ToolChain::CXXStdlibType NetBSD::GetDefaultCXXStdlibType() const {
     case llvm::Triple::armeb:
     case llvm::Triple::thumb:
     case llvm::Triple::thumbeb:
+    case llvm::Triple::mips:
+    case llvm::Triple::mipsel:
+    case llvm::Triple::mips64:
+    case llvm::Triple::mips64el:
     case llvm::Triple::ppc:
     case llvm::Triple::ppc64:
     case llvm::Triple::ppc64le:

external/apache2/llvm/dist/libcxx/include/typeinfo

@@ -248,7 +248,7 @@ struct __type_info_implementations {
     _LIBCPP_INLINE_VISIBILITY _LIBCPP_ALWAYS_INLINE
     static size_t __hash(__type_name_t __v) _NOEXCEPT {
       if (__is_type_name_unique(__v))
-        return reinterpret_cast<size_t>(__v);
+        return __v;
       return __non_unique_impl::__hash(__type_name_to_string(__v));
     }
     _LIBCPP_INLINE_VISIBILITY _LIBCPP_ALWAYS_INLINE

external/apache2/llvm/dist/llvm/lib/Support/Unix/Memory.inc

@@ -29,14 +29,6 @@
 #include <zircon/syscalls.h>
 #endif
 
-#if defined(__mips__)
-#  if defined(__OpenBSD__)
-#    include <mips64/sysarch.h>
-#  elif !defined(__FreeBSD__)
-#    include <sys/cachectl.h>
-#  endif
-#endif
-
 #if defined(__APPLE__)
 extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
 #else

external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

@@ -2927,11 +2927,11 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
 
     bool IsPtr64 = ABI.ArePtrs64bit();
     bool IsLocalSym =
-        Res.getSymA()->getSymbol().isInSection() ||
         Res.getSymA()->getSymbol().isTemporary() ||
-        (Res.getSymA()->getSymbol().isELF() &&
-         cast<MCSymbolELF>(Res.getSymA()->getSymbol()).getBinding() ==
-             ELF::STB_LOCAL);
+        (Res.getSymA()->getSymbol().isELF()
+             ? cast<MCSymbolELF>(Res.getSymA()->getSymbol()).getBinding() ==
+                   ELF::STB_LOCAL
+             : Res.getSymA()->getSymbol().isInSection());
     bool UseXGOT = STI->getFeatureBits()[Mips::FeatureXGOT] && !IsLocalSym;
 
     // The case where the result register is $25 is somewhat special. If the

external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp

@@ -37,9 +37,12 @@ ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
   llvm_unreachable("Unhandled ABI");
 }
 
-ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const {
-  if (IsO32())
+ArrayRef<MCPhysReg> MipsABIInfo::getVarArgRegs(bool IsGP64Bit) const {
+  if (IsO32()) {
+    if (IsGP64Bit)
+      return makeArrayRef(Mips64IntRegs);
     return makeArrayRef(O32IntRegs);
+  }
   if (IsN32() || IsN64())
     return makeArrayRef(Mips64IntRegs);
   llvm_unreachable("Unhandled ABI");
@@ -124,4 +127,3 @@ unsigned MipsABIInfo::GetEhDataReg(unsigned I) const {
 
   return IsN64() ? EhDataReg64[I] : EhDataReg[I];
 }
-

external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h

@@ -46,7 +46,7 @@ class MipsABIInfo {
   ArrayRef<MCPhysReg> GetByValArgRegs() const;
 
   /// The registers to use for the variable argument list.
-  ArrayRef<MCPhysReg> GetVarArgRegs() const;
+  ArrayRef<MCPhysReg> getVarArgRegs(bool IsGP64Bit) const;
 
   /// Obtain the size of the area allocated by the callee for arguments.
   /// CallingConv::FastCall affects the value for O32.

external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

@@ -63,6 +63,11 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
   case Mips::fixup_MIPS_PCLO16:
     Value &= 0xffff;
     break;
+  case Mips::fixup_Mips_AnyImm16:
+    if (!isInt<16>(Value) && !isUInt<16>(Value))
+      Ctx.reportError(Fixup.getLoc(),
+                      "fixup value out of range [-32768, 65535]");
+    break;
   case FK_DTPRel_4:
   case FK_DTPRel_8:
   case FK_TPRel_4:
@@ -355,6 +360,7 @@ getFixupKindInfo(MCFixupKind Kind) const {
     { "fixup_Mips_26",           0,     26,   0 },
     { "fixup_Mips_HI16",         0,     16,   0 },
     { "fixup_Mips_LO16",         0,     16,   0 },
+    { "fixup_Mips_AnyImm16",     0,     16,   0 },
     { "fixup_Mips_GPREL16",      0,     16,   0 },
     { "fixup_Mips_LITERAL",      0,     16,   0 },
     { "fixup_Mips_GOT",          0,     16,   0 },
@@ -434,6 +440,7 @@ getFixupKindInfo(MCFixupKind Kind) const {
     { "fixup_Mips_26",           6,     26,   0 },
     { "fixup_Mips_HI16",        16,     16,   0 },
     { "fixup_Mips_LO16",        16,     16,   0 },
+    { "fixup_Mips_AnyImm16",    16,     16,   0 },
     { "fixup_Mips_GPREL16",     16,     16,   0 },
     { "fixup_Mips_LITERAL",     16,     16,   0 },
     { "fixup_Mips_GOT",         16,     16,   0 },

external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h

@@ -134,6 +134,10 @@ namespace MipsII {
     OPERAND_MEM_SIMM9 = OPERAND_FIRST_MIPS_MEM_IMM,
     OPERAND_LAST_MIPS_MEM_IMM = OPERAND_MEM_SIMM9
   };
+
+  static inline unsigned getFormat(uint64_t TSFlags) {
+    return TSFlags & FormMask;
+  }
 }
 }
 

external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp

@@ -388,7 +388,8 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx,
     return ELF::R_MICROMIPS_JALR;
   }
 
-  llvm_unreachable("invalid fixup kind!");
+  Ctx.reportError(Fixup.getLoc(), "unsupported relocation type");
+  return ELF::R_MIPS_NONE;
 }
 
 /// Sort relocation table entries by offset except where another order is

external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h

@@ -40,6 +40,9 @@ namespace Mips {
     // Pure lower 16 bit fixup resulting in - R_MIPS_LO16.
     fixup_Mips_LO16,
 
+    // 16-bit fixup that must be resolved by the assembler.
+    fixup_Mips_AnyImm16,
+
     // 16 bit fixup for GP offest resulting in - R_MIPS_GPREL16.
     fixup_Mips_GPREL16,
 

external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

@@ -11,6 +11,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "MipsMCCodeEmitter.h"
+#include "MCTargetDesc/MipsBaseInfo.h"
 #include "MCTargetDesc/MipsFixupKinds.h"
 #include "MCTargetDesc/MipsMCExpr.h"
 #include "MCTargetDesc/MipsMCTargetDesc.h"
@@ -743,9 +744,29 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
   } else if (MO.isDFPImm()) {
     return static_cast<unsigned>(bit_cast<double>(MO.getDFPImm()));
   }
-  // MO must be an Expr.
+  // TODO: Set EncoderMethod to "getImmOpValue" for immediate operands so
+  // getMachineOpValue will not be called for expression code paths.
   assert(MO.isExpr());
-  return getExprOpValue(MO.getExpr(),Fixups, STI);
+  return getImmOpValue(MI, MO, Fixups, STI);
+}
+
+unsigned MipsMCCodeEmitter::getImmOpValue(
+    const MCInst &MI, const MCOperand &MO,
+    SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
+  if (MO.isImm())
+    return MO.getImm();
+  assert(MO.isExpr() && "getImmOpValue expects an expression or immediate");
+  const MCExpr *Expr = MO.getExpr();
+  int64_t Res;
+  if (Expr->evaluateAsAbsolute(Res))
+    return Res;
+  unsigned Form = MipsII::getFormat(MCII.get(MI.getOpcode()).TSFlags);
+  if (!isa<MCTargetExpr>(Expr) && Form == MipsII::FrmI) {
+    Fixups.push_back(MCFixup::create(
+        0, Expr, MCFixupKind(Mips::fixup_Mips_AnyImm16)));
+    return 0;
+  }
+  return getExprOpValue(Expr, Fixups, STI);
 }
 
 /// Return binary encoding of memory related operand.

external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

@@ -181,6 +181,10 @@ class MipsMCCodeEmitter : public MCCodeEmitter {
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
 
+  unsigned getImmOpValue(const MCInst &MI, const MCOperand &MO,
+                         SmallVectorImpl<MCFixup> &Fixups,
+                         const MCSubtargetInfo &STI) const;
+
   unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;

external/apache2/llvm/dist/llvm/lib/Target/Mips/Mips.td

@@ -218,6 +218,11 @@ include "MipsInstrInfo.td"
 include "MipsCallingConv.td"
 include "MipsRegisterBanks.td"
 
+foreach i = {1-31} in
+  def FeatureReserveGPR#i :
+      SubtargetFeature<"reserve-gpr"#i, "UserReservedGPR["#i#"]", "true",
+                       "Reserve MIPS GPR "#i>;
+
 // Avoid forward declaration issues.
 include "MipsScheduleP5600.td"
 include "MipsScheduleGeneric.td"

external/apache2/llvm/dist/llvm/lib/Target/Mips/MipsCallLowering.cpp

@@ -463,7 +463,8 @@ bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
     return false;
 
   if (F.isVarArg()) {
-    ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
+    ArrayRef<MCPhysReg> ArgRegs =
+        ABI.getVarArgRegs(MF.getSubtarget<MipsSubtarget>().isGP64bit());
     unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
 
     int VaArgOffset;

external/apache2/llvm/dist/llvm/lib/Target/Mips/MipsCallingConv.td

@@ -339,14 +339,16 @@ def CC_Mips_FixedArg : CallingConv<[
 
   CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>,
 
-  CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
+  CCIfSubtarget<"isABI_O32()",
+      CCIfSubtargetNot<"isGP64bit()", CCDelegateTo<CC_MipsO32_FP>>>,
   CCDelegateTo<CC_MipsN>
 ]>;
 
 def CC_Mips_VarArg : CallingConv<[
   CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
 
-  CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
+  CCIfSubtarget<"isABI_O32()",
+      CCIfSubtargetNot<"isGP64bit()", CCDelegateTo<CC_MipsO32_FP>>>,
   CCDelegateTo<CC_MipsN_VarArg>
 ]>;