Add a TRT+PyMatching decoder profile to the HSB FPGA decoding-server test

[cketcham2333]

Description

Adds a trt_decoder profile to hsb_fpga_decoding_server_test.sh: the TensorRT
predecoder + PyMatching global decoder combo running as a single decoding_server session,
with the FPGA feeding syndromes through the unchanged hololink_fpga_syndrome_playback tool.
The profile rides the existing pymatching plumbing end to end — trt_decoder has no
graph-dispatch support, so it uses the same cpu_roce HOST_CALL transport, the same
Bridge Ready handshake, and the same decoder-agnostic wire format. The combo itself comes
from the generator: surface_code-4-yaml --decoder_type trt_decoder --onnx_path X writes the
config entry with global_decoder: pymatching and its parameters automatically.

hololink_fpga_syndrome_playback (UNCHANGED)   decoding_server --transport=cpu_roce
  programs SIF w/ server QP/RKey/addr           --qp_config=hsb_fpga
  writes per-round RPC frames to FPGA BRAM      decoder session: trt_decoder
  arms ILA, verifies captured RPCResponses        ONNX -> TRT engine -> per-shot inference
                                                  -> PyMatching global decode -> corrections

Changes (one file: libs/qec/unittests/utils/hsb_fpga_decoding_server_test.sh)

• --decoder trt_decoder profile + --onnx PATH flag (default AUTO). AUTO generates
  the tiny identity predecoder ONNX at run time (mirrors the
  app_examples/surface_code-4-yaml-test.sh snippet): output row = [pre_L=0, syndrome untouched], so TRT preserves the syndrome, PyMatching performs the actual correction, and
  expected corrections stay computable at generation time with no trained model — while still
  exercising ONNX parse, TRT engine build, and per-shot inference. Requires the python3
  onnx module (checked with a clear error).
• Config generation passes --onnx_path for the profile and pins the generated YAML to
  the combo (must contain a trt_decoder entry with onnx_load_path). The syndromes run
  (--yaml) constructs the decoder in-process and decodes, so the TRT plugin .so is
  checked explicitly before generation — the decoder-plugin loader silently skips
  missing/broken .sos.
• Build phase: -DCUDAQ_QEC_BUILD_TRT_DECODER flips from the hardwired OFF to ON for
  the trt profile (hard configure failure when the TensorRT dev packages are absent — loud
  beats two layered silent skips) and stays OFF otherwise; cudaq-qec-trt-decoder joins
  the profile's build targets.
• New session-identity check for ALL profiles: after Bridge Ready, the server log must
  name the constructed session (decoder 0 type: <decoder>). This matters most for
  trt_decoder, where the identity ONNX makes a silently-substituted plain-pymatching
  session pass the FPGA corrections verification bit-identically; with the session identity
  pinned, the plugin's no-fallback semantics mean matching corrections in the FPGA capture
  RAM prove TRT inference ran on every shot.

Pass criterion unchanged: hololink_fpga_syndrome_playback --verify (ILA-verified header +
correction matching). No C++ changes — plugin, server, playback, and wire format
untouched.