[OMNIML-5899] Add CUDA kernels for IQ packing

[hychiang-git]

Summary

• add native CUDA packing kernels for IQ1_S and IQ2_XS
• load both extensions through the quantization extension module
• validate caller metadata and launch bounds before contiguous materialization
• normalize non-finite input elements consistently with the Python reference path
• accept caller-computed IQ2_XS FP16 superblock scales to avoid a duplicate reduction
• share common packing helpers and add direct extension compilation and boundary tests

PR split

This work is split into four focused PRs. Each PR targets main and owns a disjoint file set:

1. Kernel — #2448: Add CUDA kernels for IQ packing
2. Quantization — #2446: Add IQ quantization codecs and backend
3. Export — #2447: Export IQ checkpoints from HF and Megatron
4. Recipes — #2449: Add IQ post-training quantization recipes

The required merge order is #2448, #2446, #2447, then #2449.

Scope

This PR owns only native kernel sources, shared packing helpers, extension loading and build registration, and direct extension tests. It does not contain Python codecs, export code, or recipes.

GPU test coverage

Direct kernel-boundary coverage is included in this PR:

• extension compilation, zero payloads, input validation, and row-alignment checks

Pack/dequantize numerical, native/reference byte-parity, and non-finite-policy tests are owned by the quantization PR: IQ1_S and IQ2_XS.

Dependency behavior

On main, this PR provides optional CUDA extension loaders and direct extension tests. The Python encoders and fallback dispatch land in #2446. Until #2446 lands, no quantization path calls these getters, so a load failure reports only that the extension is unavailable.

The IQ2_XS packer accepts one caller-computed FP16 scale per 256-value block. #2446 owns that predictor and passes the same values to the native and reference encoders.

Provenance

• The CUDA kernels were independently written.
• They implement the packed-format contract and sign-parity convention from the pinned llama.cpp definition.
• 16.875 = 15 × (1 + 1/8) is a derived IQ1_S constant.
• 0.125 is part of the encoded format.
• 0.61 is our empirical IQ1_S scale predictor, not copied from upstream code.
• The IQ2_XS predictor constants are owned by [OMNIML-5899] Add IQ quantization codecs and backend #2446 and are not duplicated in this kernel.

Human review is still required to confirm that the attribution and license treatment are sufficient.

Validation

• repository hooks, including native formatting, pass for all changed files
• extension loader and test modules compile as Python
• all 20 direct-extension and CUDA integration test cases collect locally
• CUDA runtime execution is delegated to GPU CI because the local host is macOS
• restricted-term scan passes

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📝 Walkthrough

Walkthrough

IQ1_S now has a CUDA GGML packer. IQ2_XS now accepts caller-provided float16 block scales. Both extensions expose validated pack bindings, lazy loaders, and GPU test coverage.

Changes

GGML IQ Packing

Layer / File(s)	Summary
IQ1_S CUDA packing modelopt/torch/kernels/quantization/ggml/iq1_s.cpp, modelopt/torch/kernels/quantization/ggml/iq1_s.cu	Adds IQ1_S scale computation, codebook encoding, GGML payload packing, input validation, CUDA dispatch, and the pack binding.
IQ2_XS CUDA packing modelopt/torch/kernels/quantization/ggml/iq2_xs.cpp, modelopt/torch/kernels/quantization/ggml/iq2_xs.cu	Changes packing to use validated float16 per-block scales and removes internal scale estimation.
CUDA extension loading modelopt/torch/quantization/extensions.py	Adds cached IQ1_S and IQ2_XS loaders, lazy resolution, exports, CUDA 11.8 build settings, and precompile() integration.
GPU packing validation tests/gpu/_extensions/test_torch_extensions.py	Adds availability checks and updates shared tests for scale-aware IQ2_XS packing, zero-block output, unsupported dtypes, and invalid row sizes.

Priority: ➖ Normal

Estimated code review effort: 4 (Complex) | ~60 minutes

Change: Feature

Sequence Diagram(s)

IQ1_S packing

sequenceDiagram
  participant Python
  participant PyBind11
  participant iq1_s_pack_cuda
  participant IQ1SScaleKernel
  participant IQ1SEncodingKernel
  Python->>PyBind11: Call pack(input, grid)
  PyBind11->>iq1_s_pack_cuda: Validate and forward contiguous tensors
  iq1_s_pack_cuda->>IQ1SScaleKernel: Compute block scales
  IQ1SScaleKernel-->>iq1_s_pack_cuda: Store scales
  iq1_s_pack_cuda->>IQ1SEncodingKernel: Encode GGML payload
  iq1_s_pack_cuda-->>Python: Return packed uint8 tensor

Loading

IQ2_XS packing

sequenceDiagram
  participant Python
  participant PyBind11
  participant iq2_xs_pack_cuda
  participant IQ2XSEncodingKernel
  Python->>PyBind11: Call pack(input, grid, scales)
  PyBind11->>iq2_xs_pack_cuda: Validate and forward contiguous tensors
  iq2_xs_pack_cuda->>IQ2XSEncodingKernel: Encode using supplied block scales
  iq2_xs_pack_cuda-->>Python: Return packed uint8 tensor

Loading

Merge Risk: 🟡 Moderate · up to 7643d

Valid accepted numeric inputs can produce zeroed or invalid quantized blocks. Define and enforce numeric range handling before merging.

🚥 Pre-merge checks | ✅ 5 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 25.93% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 27 functions across 6 files.	Write docstrings for the functions missing them to satisfy the coverage threshold.

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Security Anti-Patterns	✅ Passed	PASS. The pull request changes only two Python files under modelopt and tests; it adds no examples Python files. The added Python code only loads CUDA extensions and defines GPU tests. No change…
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Title check	✅ Passed	The title clearly and concisely describes the main change: adding native CUDA kernels for IQ1_S and IQ2_XS packing.

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[hychiang-git]

/claude review

[claude]

Claude review — CUDA IQ1_S / IQ2_XS packing kernels

Findings: CRITICAL 0 · IMPORTANT 2 · SUGGESTION 4

Full-coverage review — all 5 changed files opened (2 .cu, 2 .cpp, extensions.py), plus the reference encoders on the base branch (ggml/iq1_s.py, ggml/iq2_xs.py, ggml/common.py) and utils/cpp_extension.py for the loader contract.

The kernels themselves look correct

I traced both packers end-to-end against the GGML block layouts and against the PyTorch reference encoders, and found no algorithm or memory bugs. Specifically verified:

• Wire format. block_iq1_s = 2 + 32 + 16 = 50 B and block_iq2_xs = 2 + 64 + 8 = 74 B, matching kPayloadBytes. qh bit packing (3 high index bits × 4 at bits 0–11, local scale at 12–14, delta sign at 15) matches dequantize_row_iq1_s. IQ2_XS scale nibbles pack as locals[2i] | locals[2i+1] << 4 at offset 66, matching db[l/2] = d*(0.5+sc)*0.25 — and d*(2*ls+1)*0.125 is algebraically identical to that.
• Scale anchors. kNativeMax is self-consistent in both: 15 * 1.125 = 16.875 for the ternary grid plus delta, 3.875 * 43 = 166.625 for the max IQ2_XS grid byte. Both match the hardcoded constants in the reference.
• Even-parity sign field. IQ2_XS correctly stores only the low 7 sign bits and flips the sign of the element with the smallest |x_j|*q_j when the negative count is odd, so ksigns_iq2xs reconstructs bit 7 as the parity of the stored bits. The even_parity_dot correction (dot - 2*weakest) is consistent with the flip actually applied, and it round-trips correctly even when the flip lands on element 7.
• Search equivalence. Phase 1’s per-choice minimum and phase 2’s re-derived argmin optimise the same objective with the same code, so they agree; and the (error_bits << 32) | entry key reproduces the reference’s "lowest index on equal error" tie-break. error >= 0 is guaranteed by fmaxf, so the bit-pattern ordering is valid, and -0.0 cannot arise (shifted_norm is a sum of squares, qnorm >= 512 for IQ2_XS).
• Synchronisation. Every __shared__ write/read pair is separated by a __syncthreads(), all early returns (d_bits == 0, block >= num_blocks) are block-uniform, and the shuffle reductions run with uniform loop bounds so the 0xffffffff masks are safe. IQ2_XS’s ~19 KB of shared memory fits the 48 KB default.
• No uninitialised output. at::empty is fully overwritten in both formats — bytes 0–49 and 0–73 respectively — including the all-zero-block branch.
• Host boundary. CUDAGuard is taken before at::empty and getCurrentCUDAStream(), dtype/shape/device checks are at the interface, and num_blocks <= INT_MAX bounds the grid dim.

What should be fixed

1. Zero test coverage (extensions.py) — the most consequential finding. grep -rl "iq1_s|iq2_xs|ggml" tests/ returns nothing, and quantize_iq* silently prefers the extension on every CUDA weight, so this kernel is the export path. A packing bug corrupts every exported IQ checkpoint with nothing failing. The PR notes GPU CI would cover runtime behaviour, but there is no test for GPU CI to run. Suggested tests/gpu cases are in the inline comment.

2. The two encoders are not bit-identical (iq1_s.cu) — the CUDA error uses fused fmaf chains while the reference uses separately-rounded fp32 ops with a cuBLAS dot. Tie-breaking is aligned, but ~1 ULP differences can reorder distinct near-ties, so exported bytes depend on whether the extension compiled on the host. Quality impact is nil; the fix is to stop asserting equality — amend the iq2_xs.py:173-174 comment that claims the strict comparison "match[es] the CUDA key", and compare dequantized MSE rather than raw bytes in the new test.

Suggestions (non-blocking): a redundant second codebook sweep that could be halved, an unused kLocalScales, hardcoded payload offsets in a byte-exact format, and a raise_if_failed retry clause that diverges from the three sibling getters and has no caller.

Risk

Low-to-moderate. The code is additive — new files plus additive __all__ entries, no mode registration, config schema, modelopt_state, or public API change, so no backward-compatibility exposure. The kernels are careful and, as far as static review can establish, correct. The risk is entirely that "as far as static review can establish" is the only assurance there is: nothing executes this code in CI, and it silently overrides the tested-by-nobody-either reference path. Landing a GPU cross-check test would move this to low risk.

[cjluo-nv]

Bot review (claude-opus-5) — DM the bot to share feedback.

Requesting changes: ~610 lines of new CUDA encoding logic land with zero tests, and the scale heuristics that decide output quality are undocumented magic constants.

Needs action:

• Add GPU tests: at minimum test_cuda_ext_iq1_s/test_cuda_ext_iq2_xs in tests/gpu/_extensions/test_torch_extensions.py (every other extension has one), plus a numerical test that the packed 50/74-byte blocks dequantize back within tolerance.
• Explain the scale heuristics in iq1_s.cu (* 0.61f) and iq2_xs.cu (1 - 0.035 * peak_to_rms clamped to 0.65–0.92) in code comments, and show they don't regress accuracy versus the reference encoder.
• Confirm the "PyTorch reference encoder" named in both fail_msg strings (extensions.py:92) actually exists on the base branch and is selected when the extension fails to load.
• Confirm provenance of the GGML IQ1_S/IQ2_XS bit layouts and constants (16.875, 166.625, 0.125 delta, sign-parity trick); if adapted from llama.cpp, add attribution — this is a human legal call.
• Drop the unused kLocalScales in iq1_s.cu and consider sharing the warp-reduce/key-packing scaffolding duplicated across both .cu files.

[hychiang-git]

/claude review

[cjluo-nv]

Bot review (claude-opus-5) — DM the bot to share feedback.

Requesting changes again: the critical gap from the last review — ~600 lines of CUDA encoding with zero tests — is still open, and the new llama.cpp provenance comment needs a human licensing call.

Needs action:

• Add GPU coverage for these kernels: test_cuda_ext_iq1_s/test_cuda_ext_iq2_xs in tests/gpu/_extensions/test_torch_extensions.py (every sibling extension has one), plus a pack→dequantize numerical check. If #2450 covers them, say so in the PR body and link the tests.
• Get OSRB/human sign-off on the GGML layout and constants: the new comment in both .cu files cites llama.cpp (MIT) while the files carry the NVIDIA Apache-2.0 header — confirm attribution is sufficient.
• Confirm the fallback named in extensions.py fail_msg ("PyTorch reference encoder") exists before this merges — modelopt/torch/quantization/ggml is absent on this branch, so a load failure currently has nothing to fall back to.
• Optional: drop the unreachable raise_if_failed retry clause so all five getters share one caching pattern, and dedupe the warp-reduce/key-packing scaffolding across the two .cu files.

No action needed:

• ✔️ Resolved since the last review: unused kLocalScales removed, named payload offsets (kScaleOffset/kIndexOffset/kMetadataOffset), and the scale-heuristic constants now documented in both find_scale kernels.

[claude]

Claude review — CUDA IQ1_S / IQ2_XS packing kernels (round 3, HEAD b39dca34)

Findings this round: CRITICAL 0 · IMPORTANT 1 new + 2 still open · SUGGESTION 1 new

Scope: full coverage — all 5 changed files (2 .cu, 2 .cpp, extensions.py). No mode registration, config schema, modelopt_state, or public API signature change, so I did not open sub-package mode.py/config.py.

HEAD is the same commit the previous review ran against, so the code is unchanged. I focused on what the earlier passes missed rather than restating them.

New this round

1. [IMPORTANT Export] numel % 256 == 0 does not enforce the GGML per-row block alignment (iq1_s.cu:260, same at iq2_xs.cu:293). Blocks are cut by linear offset from the flattened tensor, but GGML dequantizes per row, so each row must be a whole number of 256-element blocks. A [512, 384] weight passes the check (numel = 196608) while block 1 straddles rows 0 and 1 — every subsequent row is shifted, llama.cpp loads it without complaint, and the corruption is invisible. Reachable in practice: the Qwen2 vocab of 151936 is % 256 == 128. llama.cpp itself declines to pack rows that are not a multiple of QK_K. Fix is a one-line input.size(-1) % kBlockSize == 0 check at the boundary, plus a note in the pybind docstrings, which currently mention only numel.

2. [SUGGESTION] The 256-thread geometry is hardcoded in three places that must agree (iq1_s.cu:91-93, iq2_xs.cu:108-110) — shared-array sizing, the w < 8 cross-warp loops, and the launch literal 190 lines away — plus an unstated requirement that blockDim.x divides kEntries. A future change to the launch config would silently reduce over uninitialized shared memory. A kThreads/kWarps constexpr pair and one static_assert make it a compile error instead.

Re-verified: the encoding logic itself is correct

I re-derived both packers against the GGML block definitions independently of the earlier pass and again found no algorithm or memory bug. Notably:

• IQ2_XS grouping, the subtlest part, is right. scales[ib32] holds two nibbles serving l=0,1 and l=2,3 respectively — 16 groups of 16 elements, not 8 of 32 — and kGroups = 16 with locals[2*tid] | locals[2*tid+1] << 4 maps exactly onto that. d*(2*local+1)*0.125 is algebraically identical to the GGML d*(0.5+sc)*0.25.
• IQ1_S shifted objective matches dl*(grid[j] + delta): shifted_dot = sum x_j(q_j+delta) and shifted_norm = sum (q_j+delta)^2 both expand correctly, and the qh field layout (3 index bits × 4 at bits 0–11, local scale at 12–14, delta sign at 15) matches dequantize_row_iq1_s.
• Even-parity sign encoding round-trips through ksigns_iq2xs including when the flip lands on element 7, and dot - 2*weakest is consistent with the flip actually applied.
• Synchronization is sound. I specifically checked the loop-carried hazard on warp_best/warp_keys: the write in iteration n+1 is separated from the read in iteration n by the trailing __syncthreads(), so there is no race. All early returns are block-uniform and the shuffle masks run with uniform bounds.
• No uninitialised output: at::empty is fully overwritten in both formats, including the all-zero-scale branch, and find_scale writes every in-range block.
• Choosing -O3 over the --use_fast_math used by the sibling get_cuda_ext_mx is the right call for a bit-exact format.

Still open from prior rounds

• [IMPORTANT] Zero test coverage. A grep for iq1_s/iq2_xs under tests/ is still empty. Every sibling extension has a test_cuda_ext_* case in tests/gpu/_extensions/test_torch_extensions.py; these two have none, so there is nothing for GPU CI to run. If #2450 covers them, please link the tests from the PR body — that would close this.
• [IMPORTANT Compatibility] The fallback named in both fail_msg strings does not exist here. modelopt/torch/quantization/ggml is absent on this branch, so "using the PyTorch reference encoder" is a promise with nothing behind it. Fine if #2446 lands first; worth confirming the merge order.
• [Human call] llama.cpp provenance. Both .cu files now cite ggml-org/llama.cpp (MIT) while carrying the NVIDIA Apache-2.0 header. Needs OSRB sign-off, not a bot decision.
• Optional, unchanged: the redundant second codebook sweep in iq1_s.cu, and the raise_if_failed retry clause in the two new getters that diverges from the three siblings.

Risk

Moderate. The kernels are careful and, as far as static review can establish, correct — I have now traced them twice against the format spec without finding a numerical bug. The risk is not the math; it is that static review is the only assurance. Nothing executes ~600 lines of CUDA in CI, the extension is silently preferred over the reference on every CUDA weight, and the new row-alignment gap is exactly the class of bug that produces a checkpoint which loads cleanly and decodes wrong. Adding the size(-1) check and a pack-then-dequantize GPU test would move this to low risk.

🤖 Generated with Claude Code

[hychiang-git]

/claude review

[cjluo-nv]

Bot review (claude-opus-5) — DM the bot to share feedback.

Nudge: the prior review's asks are all addressed, but the llama.cpp provenance still needs a human licensing call and one hardening question is open.

Needs action:

• Get OSRB/legal sign-off on the GGML format provenance: both .cu files cite ggml-org/llama.cpp (MIT) under the NVIDIA Apache-2.0 header; confirm the PR-body Provenance section is sufficient attribution.
• Confirm per-row block alignment: iq1_s.cu:260 / iq2_xs.cu:293 only check numel % 256, so a [512, 384] weight packs blocks that straddle rows. Add a input.size(-1) % kBlockSize == 0 check or state that the #2446 caller guarantees it.
• Confirm merge order — tests/gpu/_extensions/test_torch_extensions.py still has no IQ cases on this branch, so #2450 must land with or right after this PR.
• Optional: drop the raise_if_failed retry clause in both new getters in extensions.py:83,98 so all five getters share one caching pattern.

No action needed:

• ✔️ Resolved since the last review: GPU coverage now linked from the PR body (#2450), fail_msg no longer promises a reference encoder absent on this branch, kLocalScales dropped, payload offsets named, scale heuristics documented.

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Inline comments:
In `@modelopt/torch/kernels/quantization/ggml/iq1_s.cu`:
- Around line 52-53: Update both CUDA load_float helpers used by IQ1_S and
IQ2_XS to test finiteness while the input remains at source precision, then
consistently clamp or reject finite values outside the float32 range before
narrowing. Preserve non-finite handling and apply the identical range policy in
both helpers so finite float64 inputs such as 1e100 are not converted to zero.

In `@modelopt/torch/kernels/quantization/ggml/iq2_xs.cpp`:
- Around line 40-42: Update the scales validation before iq2_xs_pack_cuda
dispatch to reject any NaN or infinite entries in the float16 one-dimensional
scales tensor, while preserving the existing dtype, rank, and numel checks. Do
not normalize invalid values unless an explicit zero-scale policy already
exists.

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• modelopt/torch/kernels/quantization/ggml/iq1_s.cpp
• modelopt/torch/kernels/quantization/ggml/iq1_s.cu
• modelopt/torch/kernels/quantization/ggml/iq2_xs.cpp
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[cjluo-nv]

should we put the following license on the file from the llama.cpp repo?

MIT License

Copyright (c) 2023-2026 The ggml authors

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

[cjluo-nv]

can we move these common headers to a separate header file and include the header in this file?

[cjluo-nv]

Both asks in this thread are in 74240e17 and 74e94db9.

Shared header. ggml/common.cuh now holds the include block, the block geometry and codebook sizes, load_float, the clamped squared-error form, the (error << 32) | entry key, the warp-then-block reductions, and the fp16-scale / zero-payload write. Each .cu keeps only its format-specific search and payload layout.

License. I added the MIT block first, then checked it against upstream and took it back out in 74e94db9. Comparing these files against ggml-quants.c and ggml-common.h at the pinned 9b05354:

• No shared source text. No normalized source line over 25 characters appears upstream, and none of upstream's encoder identifiers — kmap_q2xs, kneighbors_q2xs, sumqx/sumq2, nearest_int, x_p/x_m, is_on_grid, Laux, waux — appear here.
• Different algorithms. quantize_row_iq1_s_impl weights each value by qw*sqrtf(sigma2 + xb[i]*xb[i]), sorts the block, builds prefix sums and exhaustively searches the two split boundaries, then falls back to kneighbors_q2xs and refits by least squares. quantize_row_iq2_xs_impl sweeps is = -9..9 scale perturbations with nearest_int plus the same neighbour tables and refit. These kernels scan the whole codebook unweighted and reduce a packed (error, entry) key — no weights, no sort, no neighbour tables, no refit.
• Nothing upstream to port. llama.cpp's CUDA quantize.cu only encodes activations to Q8_1 / NVFP4 / MXFP4. mmq-instance-iq1_s.cu and mmq-instance-iq2_xs.cu are autogenerated matmul instantiations that consume packed data, and the Vulkan dequant_iq*.comp shaders decode.

What is shared is the wire format — payload sizes, field offsets, the qh bit layout, IQ1S_DELTA, the 7-bit sign field, the scale nibbles — which any GGUF writer has to match. A notice would assert ggml's copyright over files containing none of its expression, so attribution is now a pinned pointer scoped to the constants it actually covers: block geometry and codebook sizes in common.cuh, payload layout in each .cu.

Two convergences I'd flag for OSRB rather than decide here:

• 1.125. Upstream: float d = max_scale/15; y[ibl].d = GGML_FP32_TO_FP16(d*1.125f); // 1.125f is another fudge factor. Don't ask me why it is needed. Here: kNativeMax = kMaxLocalScale * kMaxShiftedMagnitude, i.e. 15 * (1 + kDelta). Same two numbers, combined differently — upstream scales the fitted scale, this divides amax — and derived here rather than unexplained.
• The odd-parity flip. Upstream flips the coordinate minimizing weight[i]*xb[i]*xb[i]; here it is |x[j]| * q[j]. Same strategy, different criterion; the strategy is close to forced by the format storing only 7 sign bits.

This is a code-similarity finding, not a legal opinion — if OSRB reads it differently the notice goes back in.

[cjluo-nv]

same here

[cjluo-nv]

Same treatment in 74e94db9: MIT block removed, attribution is now a pinned pointer to ggml-common.h directly above the IQ2_XS format constants. Reasoning and the upstream comparison are in the iq1_s.cu thread.

[cjluo-nv]

Bot review (claude-opus-5) — DM the bot to share feedback.

Confirmed: the two .cu files and the two .cpp files carry substantial copy-pasted code that is already drifting, and the licensing question raised earlier is still unanswered.

Needs action:

• Extract the duplicated device helpers into a shared ggml/common.cuh — load_float, the fmaxf(..., 0.0f) error clamp, the warp/block min reduction, and the (error<<32)|entry key reduce are near-identical in iq1_s.cu and iq2_xs.cu. This also answers the earlier "move the common headers into a header file" request.
• Collapse the validation duplicated between iq1_s.cpp and iq1_s_pack_cuda (same for IQ2_XS) into one shared inline checker; the copies already diverge (literals 256/2048/8 in the .cpp vs kBlockSize/kEntries, and <ATen/ATen.h> included in one .cpp but not the other).
• Obtain the OSRB/legal answer on the llama.cpp (MIT) provenance question asked on iq1_s.cu:34 — no codeowner reply yet.
• Assert something from the encode loop on this branch, or state in the PR body that only #2446/#2450 covers it: every passing test here packs zeros, so the encoder never runs.

No action needed:

• ✔️ Resolved since the last review: per-row block alignment enforcement, named payload offsets, _IQ_EXTENSIONS param list, extension load/dtype/alignment tests.

[cjluo-nv]

Bot comment.

Confirming the duplication concern: this helper is byte-identical to iq2_xs.cu:46, and it is not the only one. Shared between the two .cu files today:

• the include block (lines 18-29) — identical, which is also what the earlier "can we move these common headers to a separate header file" request was about;
• load_float;
• the fmaxf(fmaf(scale*scale, ..., fmaf(-2.0f*scale, ...)), 0.0f) error form in quant_error;
• the warp __shfl_down_sync min reduction + cross-warp reduce over warp_best (~25 lines each);
• the (__float_as_uint(error) << 32) | entry key build, its shuffle-min, and the warp_keys[0..7] fold (~20 lines each);
• kBlockSize/kVectorSize/kScaleOffset, the d_bits == 0 zero-payload branch and the fp16 scale write.

Suggest a modelopt/torch/kernels/quantization/ggml/common.cuh holding the includes, the shared constants, load_float, clamped_quant_error, and two templated reduction helpers (block_min(float) / block_min_key(unsigned long long)), leaving each .cu with only its format-specific search and payload layout. That is roughly 80-100 duplicated lines removed and, more importantly, one place to fix if the reduction or the non-finite policy ever changes — right now a fix has to be applied twice, in lockstep, on code nothing on this branch executes.

[cjluo-nv]

Done in 74240e17. ggml/common.cuh now holds all of it: the include block, kBlockSize/kVectorSize/kScaleOffset/kScaleBytes plus the two codebook sizes, load_float, clamped_quant_error, error_key, block_min_accumulate<kSlots>, block_min_key, and store_block_scale<kPayloadBytes> for the zero-payload branch and fp16 scale write. Both .cu files are down to #include "common.cuh" plus their format-specific search and payload layout.

Since the shared header changes the non-finite policy in one place now, the float64 narrowing bug CodeRabbit found got fixed once rather than twice.

[cjluo-nv]

Bot comment.

This validation block repeats iq1_s.cpp:26-41 almost verbatim (dtype set, numel() > 0, innermost-dimension multiple, grid shape, device match, num_blocks <= INT_MAX), and iq2_xs.cpp / iq2_xs_pack_cuda repeat the same pair again — four copies of one contract.

The copies have already drifted: the .cpp files spell the bounds as literals (256, 2048, 8, 512) while the .cu files use kBlockSize/kEntries/kVectorSize, so a future change to a constant silently updates only half the checks and the error strings stop matching the enforced rule (the alignment-rejection test matches on that string).

Suggest one inline void check_iq_pack_inputs(const at::Tensor& input, const at::Tensor& grid, int64_t entries) in the shared header, called from the pybind wrapper and — for the post-contiguous() invariants — from the _cuda entry point, with the format-specific scales check layered on top for IQ2_XS.

[cjluo-nv]

Done in 74240e17. One check_pack_inputs(format, input, grid, entries) in common.cuh, called from the pybind wrapper on the caller's tensors and again from the _cuda entry point on the materialized contiguous ones, so the post-contiguous() invariant still gets checked against the layout that is actually packed. The .cpp literals are gone — 256/2048/8/512 are now kBlockSize, kIq1sEntries, kVectorSize, kIq2xsEntries — and the alignment-rejection test matches a message that exists in exactly one place. IQ2_XS layers its scales checks on top.

[cjluo-nv]

Bot comment.

This 16-line warp-then-block min reduction over warp_best is the same code as iq1_s.cu:160-176, differing only in kLocalScales vs kChoices as the array stride. Both also hardcode the 8-warp fold (for w < 8) against a <<<..., 256>>> launch ~140 lines away.

A single templated helper in the proposed shared header, e.g.

template <int kSlots>
__device__ void block_min_per_slot(const float (&local)[kSlots], float *warp_scratch, float *out);

would collapse both copies and let the warp count be derived from one kThreads constant with a static_assert, instead of the literal 8 appearing in four places across the two files.

[cjluo-nv]

Done in 74240e17. Both copies are now block_min_accumulate<kSlots>(local, scratch, accum) in common.cuh, instantiated with kChoices (16) and kLocalScales (16). The literal 8 is gone from all four sites: the header derives kWarps = kThreads / 32 from a single kThreads, the shared arrays are sized kWarps * kSlots, and the launches use kThreads. Each kernel also carries static_assert(kEntries % kThreads == 0) so a future launch-config change is a compile error rather than a silent reduction over uninitialized shared memory.

[cjluo-nv]

Bot comment.

Small symptom of the copy-paste worth fixing along with the shared header: this file includes <ATen/ATen.h> while iq2_xs.cpp does not, even though both use at::Tensor and the same TORCH_CHECKs. Whichever is right, the two should not disagree — the shared header is the natural place to fix the include set once.

[cjluo-nv]

Fixed in 74240e17. Both .cpp files are now just #include "common.cuh" — the header carries the ATen/torch/<limits> include set once, so the two cannot disagree again.

[cjluo-nv]

Bot comment.

Both the weight and the grid are zero here, so find_scale yields d_bits == 0 and both kernels take the early zero-payload return; the same is true of the two rejection tests, which fail in TORCH_CHECK before any launch. Net effect: nothing on this branch executes the encode loop, the reductions, or the payload writes — the ~580 lines this PR is actually about.

The CodeRabbit thread asking for a non-zero case is marked "Addressed in 7643d73", but the test as it stands still packs zeros, so please either add one non-zero case here (a populated grid plus a random block, asserting the fp16 d field and that at least one index/sign byte is set) or say explicitly in the PR body that the encode path is covered only by #2446/#2450 and must land with it.

[cjluo-nv]

Addressed in 74240e17: test_cuda_ext_iq_encodes_non_zero_block runs the encode loop for both formats — a populated codebook and random bfloat16 weights, asserting the fp16 block scale (exact equality against the caller-supplied scales for IQ2_XS), that the indices/signs past it are written, and that two different blocks do not encode identically.

74e94db9 corrects the IQ2_XS codebook alphabet the test builds from: iq2xs_grid bytes are {0x08, 0x19, 0x2b} — there is no 1 among them, contrary to an earlier review note. IQ1_S is {0x00, 0x01, 0xff}, i.e. signed ternary.

[cjluo-nv]

Re-verified on hardware: the three new cases per format now run on an H200, and the whole tests/gpu/_extensions/test_torch_extensions.py file is 20 passed (147s), including the two sibling extensions.

The one that matters here is test_cuda_ext_iq_encoding_is_optimal: it decodes the payload from the GGML field positions and asserts the reconstruction error equals the brute-force minimum over every local scale, delta sign, and codebook entry at the block scale the payload carries — so the search, the block-wide reductions, and every bit offset are checked, not just that bytes were written. Before running it I mutation-tested the assertion against a CPU packer with four injected layout bugs (local scale one bit low, dropped delta sign, sign mask at bit 8, swapped scale nibbles); it rejects all four.

Pushed in bb35d00b.

[hychiang-git]

/claude review

[cjluo-nv]

Bot review (claude-opus-5) — DM the bot to share feedback.

Nudge: every code-level item from the last round is addressed, leaving the llama.cpp provenance sign-off and the merge-order sequencing as human calls.

Needs action:

• Obtain OSRB/legal sign-off on the GGML format provenance (NVBug 6046893 row 21): the MIT block was added then removed in 74e94db9, so common.cuh / both .cu files now carry only the canonical NVIDIA Apache-2.0 header plus a pinned ggml-common.h pointer — confirm that is sufficient attribution. No codeowner reply yet.
• Confirm merge order with #2446/#2450: test_cuda_ext_iq_encodes_non_zero_block asserts the fp16 block scale and that index/sign bytes differ per block, but no packed-byte parity against the reference encoder is checked on this branch.

No action needed:

• ✔️ Resolved since the last review: shared ggml/common.cuh (includes, load_float, clamped error, error_key, block reductions, store_block_scale), one check_pack_inputs replacing the four drifted validation copies, and a non-zero encode test exercising the search and payload writes.
• Re-checked the new header: block_min_accumulate/block_min_key scratch layouts, barrier placement across loop iterations, and the float64 saturating load_float all look correct; *.cuh is now in package-data.

[claude]

[SUGGESTION] block_min_key's contract comment overstates what the helper guarantees, and the gap is a silent-race trap for the next caller.

block_min_accumulate (just above) is genuinely self-contained: it ends with a __syncthreads() at line 137, so back-to-back calls cannot race on scratch. block_min_key says the same thing — "Barriers are internal, so every thread of the block must call this" — but it has only a leading barrier (line 154) and none after the tid == 0 read of scratch[w]. Two calls in sequence with no intervening barrier let some other warp's lane 0 overwrite scratch[warp] while thread 0 is still folding the previous call's values, and the winning codebook index would be silently wrong for that vector.

Both current callers happen to be safe — iq1_s.cu:421 and iq2_xs.cu:711 each close the vector loop with a __syncthreads() — so this is latent, not a live bug. But common.cuh is a shared header whose whole purpose is that "the enforced rule ... [is] written once", and the two reduction helpers now advertise identical barrier semantics while having different ones.

Either add the trailing barrier so the comment is true:

  if (tid == 0) {
#pragma unroll
    for (int w = 1; w < kWarps; ++w)
      key = scratch[w] < key ? scratch[w] : key;
  }
  __syncthreads();
  return key;
}

or keep it barrier-light and say so explicitly, e.g. "The caller must __syncthreads() before reusing scratch." The first is preferable — both call sites already pay that barrier, so it costs nothing and removes the asymmetry between the two helpers.

[claude]

[SUGGESTION] The boundary check validates scales finiteness but not its sign, which is the other precondition the kernel silently depends on.

iq2_xs.cu reconstructs as d * (2*ls + 1) * 0.125 * sign(x_j) * q_j, where the sign comes from the packed 7-bit field and q_j is a non-negative magnitude. A negative d therefore inverts every element of the block on decode. The search doesn't reject it either: even_parity_dot returns sum |x_j| * q_j >= 0, so with scale < 0 the -2 * scale * dot term is positive and the error is above xnorm for every candidate — the kernel still picks a minimum and emits a structurally valid payload that dequantizes to garbage. Same for -0.0 (d_bits == 0x8000 doesn't trip the store_block_scale zero path, so the block encodes normally against a zero scale rather than being zeroed).

The related gap is on grid: iq2_xs.cu:41-43 states the contract ("the grid must hold non-negative magnitudes"), and iq2_xs.cpp:43 repeats it in the pybind docstring, but nothing enforces it. A signed grid entry breaks the parity/sign split the same way.

Both matter more than usual here because the predictor and grid are owned by a different PR (#2446), so a drift between the two lands as wrong numerics rather than an exception. Since line 34 already pays a device sync, folding both in is free:

  TORCH_CHECK(scales.isfinite().all().item<bool>() && (scales >= 0).all().item<bool>(),
              "scales must be finite and non-negative");

and a TORCH_CHECK(grid.min().item<float>() >= 0.0f, "grid must hold non-negative magnitudes") alongside it (or in the _cuda entry, where the grid is already contiguous).

[claude]

[SUGGESTION] The deliberate double validation runs against CONTRIBUTING's "Validate external input once" principle, and for IQ2_XS it has already produced a real duplicate.

The comment documents the intent: called from the pybind wrapper and "again from the CUDA entry point on the materialized contiguous tensors." But CONTRIBUTING.md § Coding standards says: "Validate external input once. Check types and values at the interface boundary. Internal code can trust those checks and avoid redundant assertions." The pybind wrapper is the interface boundary; .contiguous() can't change dtype, dim(), size(-1), numel(), or device, so the second call cannot fail if the first passed.

The cost is already visible: the scales shape/dtype check and the device check are written out verbatim twice — iq2_xs.cpp:29-31 and iq2_xs.cu:209-211, plus iq2_xs.cpp:33 and iq2_xs.cu:212 — which is exactly the drift risk the shared helper was extracted to avoid, just moved from the shared fields to the format-specific ones.

Suggest dropping check_pack_inputs (and the duplicated scales/device checks) from the two *_pack_cuda entry points, keeping only the is_contiguous() assertions there since those are the internal precondition the kernels rely on, and updating this comment to say the helper is the single boundary validator shared by both formats.

[claude]

Claude review summary

Scope: full review (the trigger comment carried no scoping instructions). All 8 changed files reviewed: 5 new native sources (common.cuh, iq1_s.cpp/.cu, iq2_xs.cpp/.cu), modelopt/torch/quantization/extensions.py, pyproject.toml, and tests/gpu/_extensions/test_torch_extensions.py.

Findings this round: CRITICAL 0 · IMPORTANT 0 · SUGGESTION 3

Category	Location
Misleading contract — block_min_key advertises internal barriers but has no trailing one, unlike its sibling block_min_accumulate	common.cuh:140-161
Boundary validation — scales finiteness is checked, sign is not; grid non-negativity is documented in two places and enforced in none	iq2_xs.cpp:28-35
Duplicate validation — check_pack_inputs runs twice by design, against CONTRIBUTING's "validate external input once"; the IQ2_XS scales/device checks are already written out verbatim twice	common.cuh:58-61

None block merge.

Since the previous review

The refactor into common.cuh is a clear improvement — load_float, clamped_quant_error, error_key, the two block reductions, and store_block_scale are now single-sourced, and the two format kernels are much easier to read against the GGML spec than the earlier copies were. pyproject.toml correctly adds **/*.cuh so the new header ships; I confirmed package_data globs recursively from the modelopt package root, so ggml/ needs no __init__.py. The new scales.isfinite() guard closes a real hole — a NaN block scale would previously have been copied straight into the payload.

Six suggestions from the prior round are still open and I have not re-posted them: the 8-way shared_grid bank conflict in the IQ2_XS hot loop (thread tid reads shared_grid[tid*8 + j], so 32 lanes land on 4 banks); the uncoalesced 256-stride find_scale pass, foldable into encode; the unreachable block >= num_blocks guard; IQ1_S re-streaming its 64 KB codebook from global rather than staging it in shared the way IQ2_XS does; the absence of a least-squares refit of d; and the getter-boilerplate duplication plus precompile() now building two extra extensions for tests/gpu_megatron/conftest.py and examples/vllm_serve/Dockerfile. One correction to that earlier round: the block >= num_blocks guard is barrier-safe — block is blockIdx.x, so the branch is block-uniform and the whole block returns together. It is dead code, not a hazard.

What I verified as correct

I re-traced both packed layouts against the pinned ggml-common.h revision rather than relying on the previous pass.

IQ1_S — 2 + 32 + 16 = 50 B matches kPayloadBytes. qs[4*ib+l] carries the low 8 grid bits and qh[ib] bits 3l..3l+2 the high 3 (11 bits = 2048 entries), bits 12-14 the 3-bit ls with dl = d*(2*ls+1), and bit 15 selects -IQ1S_DELTA — all fields land in the right positions, and kNativeMax = 15 * 1.125 = 16.875 is the true peak. The (q + delta) residual expansion is algebraically exact, including the 8*delta^2 term for the 8-lane vector.

IQ2_XS — 2 + 64 + 8 = 74 B. entry | ((sign_mask & 0x7f) << 9) matches q2[l] & 511 / q2[l] >> 9; the low nibble of scales[ib] covers l=0,1 and the high nibble l=2,3, which is exactly what locals[2*tid] | (locals[2*tid+1] << 4) emits; and d*(2*ls+1)*0.125 is identically GGML's d*(0.5+ls)*0.25, independently confirmed by the test's native_max = 15.5 * 0.25 * 43 = 166.625. The ksigns_iq2xs even-parity rule is handled correctly — flipping the argmin of |x_j|*q_j makes the popcount even whichever way that sign was pointing, so the dropped 8th bit is recoverable, and dot - 2*weakest is the exact dot-product delta for that flip. Search and final encode agree bit-for-bit: both phases build dot/qnorm/qsum through the same fmaf sequence, so the error the search minimized is the error the final pass reproduces.

Also checked: __syncthreads() placement admits no cross-iteration race on warp_best, warp_keys, group_error, selected_choice/selected_local, selected_entries, or locals; every payload byte is written on both the zero-scale and normal paths (kPayloadBytes < blockDim for both 50 and 74); IQ2_XS static shared usage is ~19 KB, inside the 48 KB budget, and grid_norm[entry] is conflict-free; AT_DISPATCH_FLOATING_TYPES_AND2 covers exactly the four dtypes check_pack_inputs admits, with c10::Half/BFloat16 taking load_float's narrow branch and double the FLT_MAX-clamping one; error_key's bit-pattern ordering is safe because clamped_quant_error cannot return -0.0 (its addends are never both negative zero, since xnorm is a sum of squares); numel() > 0 plus size(-1) % 256 == 0 guarantees num_blocks >= 1; the int grid bound is guarded against INT_MAX; #include "common.cuh" resolves relative to the including source, so no extra_include_paths is needed; and grep confirms no caller in modelopt/ invokes the new getters yet.

Risk assessment: low

The diff is additive and inert on main — no mode registration, no modelopt_state schema change, no export path touched, and no public API break (__all__ only grows). A build failure degrades to a warnings.warn that the extension is unavailable. The only change to existing behavior is precompile() gaining two builds, which slows the Megatron GPU suite's session setup and the vLLM image build. The format contract is the expensive thing to get wrong and it is right; what remains is throughput and encode quality, and the byte-parity and numerical tests in #2446 are the right place to settle those.

One note for the human reviewer, echoing the PR body: the provenance section is doing real work here. The packed layout and sign-parity convention are necessarily identical to upstream because they are the wire format, while the scale predictors are asserted as original. That division matches what the code shows, but the licensing judgment is not mine to make.

🤖 Generated with Claude Code

[hychiang-git]

/ok to test 74e94db

[cjluo-nv]

Bot review (claude-opus-5) — DM the bot to share feedback.

Nudge: the kernels, shared header and tests all look correct now, but the GGML provenance sign-off the author asked for is still unanswered.

Needs action:

• Obtain OSRB/legal sign-off on the GGML format provenance (NVBug 6046893 row 21): common.cuh and both .cu files carry the canonical NVIDIA Apache-2.0 header plus a pinned ggml-common.h pointer, with the MIT block added then removed in 74e94db9 — confirm that is sufficient attribution.
• Confirm merge order with #2446: nothing in modelopt/ calls get_cuda_ext_iq1_s/get_cuda_ext_iq2_xs on this branch, and precompile() now builds two extensions no consumer uses yet.
• Optional: give block_min_key (common.cuh:161) a trailing __syncthreads() or amend its "barriers are internal" comment — both current callers happen to be safe, but the two reduction helpers advertise identical semantics with different ones.
• Optional: reject negative scales in iq2_xs.cpp:42 alongside the finiteness check; a negative d inverts every decoded element and still packs cleanly.

No action needed:

• ✔️ Resolved since the last review: the encode loop is now exercised by test_cuda_ext_iq_encoding_is_optimal (brute-force optimality against decoded GGML fields), plus dtype-equivalence and non-finite-policy tests; *.cuh ships via package-data.

[cjluo-nv]

Both optional items are addressed in 7cc1220a.

block_min_key barrier. Took the barrier rather than the comment: the helper now ends with its own __syncthreads(), matching block_min_accumulate beside it and the contract both comments already advertised. The callers' trailing barriers are dropped in the same move, so this is barrier-neutral rather than an extra sync — verified by compiling both kernels to PTX before and after, bar.sync count unchanged at 76 for IQ1_S and 48 for IQ2_XS.

Agreed on the reasoning: neither caller was racing, but two helpers in one header documenting identical semantics while having different ones is exactly the drift the shared header exists to prevent.

Negative scales. Rejected now, folded into the existing finiteness reduction so the boundary still costs one synchronization rather than two:

TORCH_CHECK((scales.isfinite() & (scales >= 0)).all().item<bool>(),
            "scales must be finite and non-negative");

Worth recording why this is worse than "inverts every decoded element": the search doesn't degrade loudly either. With dot >= 0, a negative scale makes the -2*scale*dot term positive, so the search minimises dot — it selects the smallest-magnitude entries and the smallest local scale, and emits a well-formed, plausible-looking, sign-inverted payload. GGML asserts scale >= 0 in its own encoders at four sites in ggml-quants.c.

One edge neither of us had caught: -0.0 passes the new check, since -0.0 >= 0 holds in IEEE, and it was not caught by store_block_scale's d_bits == 0 test either — negative zero is 0x8000. It skipped the zero-payload branch and ran a full codebook search in which every candidate scores identically, landing on index 0 everywhere and decoding to zeros. The output was already correct; the cost was the wasted search. store_block_scale now tests (d_bits & 0x7FFF) == 0. IQ1_S can't reach it — find_scale builds amax with fmaxf from +0.0, so its scale is never negative zero.

Tests went 20 → 25: the single non-finite case is now parametrized over nan / inf / -inf / -1.0 / -1e-4, plus a case asserting a -0.0 scale takes the zero-payload branch.

Verification. 25 passed on an RTX PRO 6000 Blackwell (sm_120), including both test_cuda_ext_iq_encoding_is_optimal cases — the ones that would catch a mis-placed barrier. The suite has now passed on two architectures: H200 sm_90 at bb35d00b and sm_120 here.

Still open, both unchanged and both human calls:

• OSRB/legal sign-off. The upstream comparison behind the attribution decision is in this thread — no shared source text, different encoder algorithms, and no GPU IQ encoder upstream to derive from, with the 1.125 constant and the odd-parity flip strategy flagged as the two convergences worth a reviewer's eye.
• Merge order with [OMNIML-5899] Add IQ quantization codecs and backend #2446. Accurate as written: nothing in modelopt/ calls either getter on this branch, and precompile() now builds two extensions no consumer uses yet. That's a sequencing decision for the author and reviewers, not something this diff should paper over.

[cjluo-nv]

Bot review (claude-opus-5) — DM the bot to share feedback.

Nudge: both optional items from the last round landed and I found no new correctness issues, but the llama.cpp provenance sign-off the author explicitly asked for is still unanswered.

Needs action:

• Obtain OSRB/legal sign-off on the GGML format provenance (NVBug 6046893 row 21): common.cuh and both .cu files carry the canonical LICENSE_HEADER text plus a pinned ggml-common.h pointer, with the MIT block added then removed in 74e94db9 — confirm that is sufficient attribution.
• Confirm merge order with #2446: nothing under modelopt/ calls get_cuda_ext_iq1_s/get_cuda_ext_iq2_xs on this branch, and precompile() now builds two extensions no consumer uses yet.

No action needed:

• ✔️ Resolved since the last review: block_min_key (common.cuh:161) now ends with its own __syncthreads() so both reduction helpers share one contract, and iq2_xs.cpp:42 rejects negative as well as non-finite scales, with store_block_scale masking -0.0 into the zero-payload branch.
• Re-checked the new -0.0, invalid-scale, dtype-equivalence and non-finite tests against the kernels; barrier placement across group iterations still looks race-free.
• Headers match LICENSE_HEADER exactly; **/*.cuh ships via package-data.

[kevalmorabia97]

/ok to test 7cc1220