Pinned Loading

1. harris-corner-asic harris-corner-asic Public

   Streaming Harris corner detector ASIC in SystemVerilog, RTL to GDSII with Cadence Genus/Conformal/Tempus/Innovus (90 nm, 250 MHz)

   Verilog

2. tmr-uart-seu tmr-uart-seu Public

   BECE303L: SEU-tolerant UART transmitter with voted-feedback TMR - fault injection, RTL to routed layout in Cadence GPDK090 (90 nm)

   Verilog

3. alu-verification-sv alu-verification-sv Public

   BEVD205L: verification of a 4-bit ALU with a constrained-random, self-checking SystemVerilog testbench (ModelSim, TCL automation, coverage, Perl regression summary)

   SystemVerilog

4. cache-hierarchy-ncg cache-hierarchy-ncg Public

   BEVD207L: gem5 cache hierarchy study (L1/L2/L3 size and associativity) with the Normalized Cache Gain metric and Pareto-optimal design

   Python