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Add explanatory comment for portFPU_REG_OFFSET in RISC-V port #1457

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Add explanatory comment for portFPU_REG_OFFSET in RISC-V port #1457

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f006492
rtos: Add explanatory comment for portFPU_REG_OFFSET in RISC-V port
wanghengZzz Jul 30, 2026
ee4636f
comment: clarify FPU context offset calculation in RISC-V portContext.h
wanghengZzz Jul 31, 2026
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8 changes: 8 additions & 0 deletions portable/GCC/RISC-V/portContext.h
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Expand Up @@ -91,6 +91,14 @@

#define portFPU_REG_SIZE ( __riscv_flen / 8 )
#define portFPU_REG_COUNT 33 /* 32 Floating point registers plus one CSR. */

/*
* Reserve space at the beginning of the FPU context block for:
* 1. The FCSR (one portWORD_SIZE slot).
* 2. Padding (one portWORD_SIZE slot) to align the FP registers:
* - RV32: 8-byte boundary for double-precision registers.
* - RV64: 16-byte boundary mandated by the RISC-V ABI.
*/
#define portFPU_REG_OFFSET( regIndex ) ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) )
#define portFPU_CONTEXT_SIZE ( portFPU_REG_SIZE * portFPU_REG_COUNT )
#else
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