Pinned Loading

1. SPI-protocol SPI-protocol Public

   This project implements an APB-based SPI Master Controller in synthesizable Verilog HDL. The controller provides an APB register interface for configuring the SPI peripheral, writing transmit data,…

   Verilog 2

2. auto-fpga auto-fpga Public

   FPGA hardware accelerator for the CTP (Complementary Twin Pyramidal) module (167M FLOPs) — 774 FPS @ 166 MHz, 0.77 W on Xilinx Virtex-7 VC707 | Verilog | Vivado 2024.2

   Verilog 1

3. 32kb_ram-verification 32kb_ram-verification Public

   SystemVerilog-based functional verification of a 32KB synchronous RAM using constrained-random stimulus, reference modeling, functional coverage, and SVA.

   SystemVerilog 1

4. Alu-verification Alu-verification Public

   SystemVerilog layered testbench for ALU functional verification — constrained-random, coverage-driven, self-checking scoreboard.

   SystemVerilog

5. Asynchronous-FIFO Asynchronous-FIFO Public

   Verilog Implementation of Parameterized and Synthesizable Asynchronous FIFO