Miniatron: Discrete TTL-Inspired 8-Bit Computer

Miniatron is a custom-designed, open-architecture 8-bit computer built entirely within Helmut Neemann's Digital simulation software. Modeled after classic 1970s and 80s transistor-transistor logic (TTL) paradigms, the processor features a true single-cycle execution path, a 16-bit address space, a completely discrete gate-level instruction decoder, and a software-driven 6-bit color VGA display output system.

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1. Project Story & Background

I originally conceived and designed Miniatron during the 2020 COVID-19 pandemic lockdown during my freshman year of high school. The architecture was heavily inspired by two hobbyist computing projects:

• Ben Eater’s 8-bit breadboard computer: Providing the foundation for layout, bus communication, and clear hardware visibility.
• The Gigatron TTL microcomputer: Providing the baseline architecture for software-timed video output (bit-banging video lines via software) and minimalistic layout paradigms.

Design Objectives

Unlike modern microprocessors or microcode-driven architectures, Miniatron was engineered with two strict conditions:

1. Simplified All-in-One ALU: Utilizing a dual 74181 cascading arithmetic logic unit setup to manage all math and logical instructions efficiently without massive physical chip sprawl.
2. Physical Feasibility: Every component is restricted to real-world discrete 74-series logic integrated circuits (ICs), making the entire computer fully capable of being constructed physically on solderless breadboards.

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2. Technical Specifications

Parameter	Specification	Hardware Realization
Data Word Size	8-bit	Common 8-bit shared data bus system
Address Bus Width	16-bit ($64\text{ KB}$ Address Space)	Quad cascading 74163 synchronous 4-bit counters
Architecture Type	Harvard Architecture	Simultaneous 8-bit Opcode & 8-bit Operand ROM fetch
ALU Core	8-bit Ripple Carry	Dual 4-bit 74181 Arithmetic Logic Unit ICs
Instruction Decoder	Pure Discrete Logic Matrix	Combinational logic gate array (AND/OR/NOT network)
System RAM	$32\text{ KB}$ Asynchronous SRAM	Custom Model of the Real CY7C199 chip
Display Controller	Software Bit-Banged VGA	6-bit color R-2R resistor ladder (64 discrete colors)
Target Clock Speed	$20\text{ MHz}$	Optimized for scaled 200x150 resolution inside 800x600 @ 60Hz timing

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3. Architecture Deep-Dive

True Single-Cycle Execution

By implementing a Harvard-style layout, the instruction ROM splits its 16-bit word output into a dedicated 8-bit instruction bus and an 8-bit immediate data bus. This completely bypasses the multiplexed bus bottlenecks found in traditional breadboard computers, allowing every single instruction to fetch, decode, execute, and write back inside a single clock cycle.

The 16-Bit Memory Latch ($Y$-Register)

To preserve the 8-bit data pathway while accessing a massive 16-bit address space, Miniatron uses a split-page register architecture.

• The lower 8 bits of any memory pointer are handled natively by the current instruction operand.
• The upper 8 bits (the memory page) must be latched manually into a dedicated Y-Register prior to memory operations or page-crossing jumps.

For example, performing a long jump across 256-byte page boundaries requires a two-step sequence:

LDY %0x04  ; Step 1: Latch upper 8-bits of destination address into Y
JMP 0x20   ; Step 2: Set lower 8-bits and execute the jump to 0x0420

Flag Generation

The arithmetic status flags utilize the native physical properties of the 74181 chips:

• Equality ($A = B$): Driven directly by wiring the open-collector $A=B$ pins of the low and high ALU units together.
• Magnitude ($A > B$): Evaluated cleanly using the final carry-out pin ($C_{n+4}$) generated at the end of the 8-bit arithmetic ripple chain.

4. Software-Driven VGA

Miniatron has no dedicated graphics chip. Instead, the CPU achieves VGA signal generation by utilizing a single 8-bit output port via the VO instruction. The 8-bit data bus is physically mapped directly to the VGA interface hardware lines:

Bit:   7         6       5     4     3     2     1     0
    [V-Sync]  [H-Sync] [ R1 ][ R0 ][ G1 ][ G0 ][ B1 ][ B0 ]
    └── Video Sync ──┘ └─────────── 6-Bit Color ──────────┘

• Bits [7:6] (2 MSBs): Wired directly to the Vertical Sync (V-Sync) and Horizontal Sync (H-Sync) lines.
• Bits [5:0] (6 LSBs): Fed into a 6-bit R-2R resistor ladder DAC network (2 Red, 2 Green, 2 Blue) capable of generating 64 discrete colors.

The Native Timing Constraints

Because the sync pulses are directly bound to the upper bits of the execution bus, the software bears the entire burden of monitor synchronization.

• During Active Video, the program code must carefully preserve the states of Bit 7 and Bit 6 while modifying the lower 6 color bits to draw pixels.
• During Blanking Intervals, the software must manually toggle Bit 6 (for horizontal blanking lines) or Bit 7 (for vertical front/back porches).

Because the instruction decoder does not feature cycle-equalization hardware, executing a conditional branch takes a different number of clock cycles depending on whether the condition is met. In a system targeting a $20\text{ MHz}$ video clock, a variance of a single clock cycle shifts the horizontal raster alignment, causing prominent screen jitter. To achieve stable output, all branch operations within the display rendering loop must be manually cycle-counted and padded with balancing NOP instructions to enforce perfectly uniform execution periods.