From eaa38c5dff96d3ddb4afcd6c986b81db8afba30f Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Thu, 13 Aug 2026 16:17:25 +0530 Subject: [PATCH 1/3] clk: qcom: sa8775p: use GATE_CLK_POLLED for CBCR-backed gate clocks Convert the USB3 and UFS PHY reference clocks in the sa8775p gate clock table from GATE_CLK() to GATE_CLK_POLLED(), so their enable status is polled against the per-clock CBCR register instead of assuming the enable write completed immediately. Signed-off-by: Balaji Selvanathan --- drivers/clk/qcom/clock-sa8775p.c | 40 ++++++++++++++++---------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c index b6aea35036f7..edaf3536a8a1 100644 --- a/drivers/clk/qcom/clock-sa8775p.c +++ b/drivers/clk/qcom/clock-sa8775p.c @@ -139,14 +139,14 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate) } static const struct gate_clk sa8775p_clks[] = { - GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, 1), - GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, 1), - GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, 1), - GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, 1), - GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1), - GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1), - GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1), - GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1b064, 1), + GATE_CLK_POLLED(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, BIT(0), 0x1b088), + GATE_CLK_POLLED(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, BIT(0), 0x1b018), + GATE_CLK_POLLED(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, BIT(0), 0x1b084), + GATE_CLK_POLLED(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, BIT(0), 0x1b020), + GATE_CLK_POLLED(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, BIT(0), 0x1b024), + GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, BIT(0), 0x1b05c), + GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, BIT(0), 0x1b060), + GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1b064, BIT(0), 0x1b064), /* QUP Wrapper 0 clocks */ GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x4b008, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT), @@ -178,22 +178,22 @@ static const struct gate_clk sa8775p_clks[] = { GATE_CLK(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000, GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT), /* UFS PHY clocks */ - GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x83018, 1), - GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, 1), - GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x83020, 1), - GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, 1), - GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x83024, 1), - GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x83028, 1), - GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x830c0, 1), - GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x830a4, 1), - GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x8306c, 1), + GATE_CLK_POLLED(GCC_UFS_PHY_AXI_CLK, 0x83018, BIT(0), 0x83018), + GATE_CLK_POLLED(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, BIT(0), 0x830d4), + GATE_CLK_POLLED(GCC_UFS_PHY_AHB_CLK, 0x83020, BIT(0), 0x83020), + GATE_CLK_POLLED(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, BIT(0), 0x83064), + GATE_CLK_POLLED(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x83024, BIT(0), 0x83024), + GATE_CLK_POLLED(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x83028, BIT(0), 0x83028), + GATE_CLK_POLLED(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x830c0, BIT(0), 0x830c0), + GATE_CLK_POLLED(GCC_UFS_PHY_PHY_AUX_CLK, 0x830a4, BIT(0), 0x830a4), + GATE_CLK_POLLED(GCC_UFS_PHY_ICE_CORE_CLK, 0x8306c, BIT(0), 0x8306c), /* EDP reference clock (used by UFS PHY) */ - GATE_CLK(GCC_EDP_REF_CLKREF_EN, 0x97448, 1), + GATE_CLK_POLLED(GCC_EDP_REF_CLKREF_EN, 0x97448, BIT(0), 0x97448), /* SDCC1 clocks */ - GATE_CLK(GCC_SDCC1_AHB_CLK, 0x2000c, 1), - GATE_CLK(GCC_SDCC1_APPS_CLK, 0x20004, 1), + GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK, 0x2000c, BIT(0), 0x2000c), + GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x20004, BIT(0), 0x20004), }; static int sa8775p_enable(struct clk *clk) From 8ab8ef6e73524265ec22b0242aacf707f6268804 Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Thu, 13 Aug 2026 16:17:25 +0530 Subject: [PATCH 2/3] clk: qcom: sc7280: use GATE_CLK_POLLED for CBCR-backed gate clocks Convert the USB3, UFS PHY, and SDCC gate clocks in the sc7280 gate clock table from GATE_CLK() to GATE_CLK_POLLED(), so their enable status is polled against the per-clock CBCR register instead of assuming the enable write completed immediately. Signed-off-by: Balaji Selvanathan --- drivers/clk/qcom/clock-sc7280.c | 62 +++++++++++++++++---------------- 1 file changed, 32 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c index 91e3fcc27cb2..4520bf9ceca2 100644 --- a/drivers/clk/qcom/clock-sc7280.c +++ b/drivers/clk/qcom/clock-sc7280.c @@ -160,22 +160,23 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate) } static const struct gate_clk sc7280_clks[] = { - GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf07c, 1), - GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0xf010, 1), - GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf080, 1), - GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0xf018, 1), - GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1), - GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1), - GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1), - GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf05c, 1), - GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x9e07c, 1), - GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x9e010, 1), - GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x9e080, 1), - GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x9e018, 1), - GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x9e01c, 1), - GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x9e054, 1), - GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x9e058, 1), - GATE_CLK(GCC_PCIE_CLKREF_EN, 0x8c004, 1), + GATE_CLK_POLLED(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf07c, BIT(0), 0xf07c), + GATE_CLK_POLLED(GCC_USB30_PRIM_MASTER_CLK, 0xf010, BIT(0), 0xf010), + GATE_CLK_POLLED(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf080, BIT(0), 0xf080), + GATE_CLK_POLLED(GCC_USB30_PRIM_SLEEP_CLK, 0xf018, BIT(0), 0xf018), + GATE_CLK_POLLED(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, BIT(0), 0xf01c), + GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, BIT(0), 0xf054), + GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, BIT(0), 0xf058), + GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf05c, BIT(0), 0xf05c), + GATE_CLK_POLLED(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x9e07c, BIT(0), 0x9e07c), + GATE_CLK_POLLED(GCC_USB30_SEC_MASTER_CLK, 0x9e010, BIT(0), 0x9e010), + GATE_CLK_POLLED(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x9e080, BIT(0), 0x9e080), + GATE_CLK_POLLED(GCC_USB30_SEC_SLEEP_CLK, 0x9e018, BIT(0), 0x9e018), + GATE_CLK_POLLED(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x9e01c, BIT(0), 0x9e01c), + GATE_CLK_POLLED(GCC_USB3_SEC_PHY_AUX_CLK, 0x9e054, BIT(0), 0x9e054), + GATE_CLK_POLLED(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x9e058, BIT(0), 0x9e058), + GATE_CLK_POLLED(GCC_PCIE_CLKREF_EN, 0x8c004, BIT(0), 0x8c004), + GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x52000, BIT(30)), GATE_CLK(GCC_PCIE_1_AUX_CLK, 0x52000, BIT(29)), GATE_CLK(GCC_PCIE_1_CFG_AHB_CLK, 0x52000, BIT(28)), @@ -196,20 +197,21 @@ static const struct gate_clk sc7280_clks[] = { GATE_CLK(GCC_QUPV3_WRAP0_S6_CLK, 0x52008, BIT(16)), GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK, 0x52008, BIT(17)), GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x52008, BIT(23)), - GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)), - GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)), - GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)), - GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, BIT(0)), - GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)), - GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0)), - GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, BIT(0)), - GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77020, BIT(0)), - GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770b8, BIT(0)), - GATE_CLK(GCC_UFS_1_CLKREF_EN, 0x8c000, BIT(0)), - GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0)), - GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)), - GATE_CLK(GCC_SDCC1_AHB_CLK, 0x75004, BIT(0)), - GATE_CLK(GCC_SDCC1_APPS_CLK, 0x75008, BIT(0)), + + GATE_CLK_POLLED(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0), 0x77010), + GATE_CLK_POLLED(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0), 0x770cc), + GATE_CLK_POLLED(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0), 0x77018), + GATE_CLK_POLLED(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, BIT(0), 0x77064), + GATE_CLK_POLLED(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0), 0x7705c), + GATE_CLK_POLLED(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0), 0x7709c), + GATE_CLK_POLLED(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, BIT(0), 0x7701c), + GATE_CLK_POLLED(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77020, BIT(0), 0x77020), + GATE_CLK_POLLED(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770b8, BIT(0), 0x770b8), + GATE_CLK_POLLED(GCC_UFS_1_CLKREF_EN, 0x8c000, BIT(0), 0x8c000), + GATE_CLK_POLLED(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0), 0x14008), + GATE_CLK_POLLED(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0), 0x14004), + GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK, 0x75004, BIT(0), 0x75004), + GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x75008, BIT(0), 0x75008), }; static int sc7280_enable(struct clk *clk) From 1a5273a6fb8dcabfe658d7f238a8cafe498f8452 Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Thu, 13 Aug 2026 16:17:25 +0530 Subject: [PATCH 3/3] clk: qcom: qcs615: use GATE_CLK_POLLED for CBCR-backed gate clocks Convert the USB3, display, and UFS PHY gate clocks in the qcs615 gate clock table from GATE_CLK() to GATE_CLK_POLLED(), so their enable status is polled against the per-clock CBCR register instead of assuming the enable write completed immediately. Signed-off-by: Balaji Selvanathan --- drivers/clk/qcom/clock-qcs615.c | 54 +++++++++++++++++---------------- 1 file changed, 28 insertions(+), 26 deletions(-) diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c index 20c45f8895fd..b13de832e396 100644 --- a/drivers/clk/qcom/clock-qcs615.c +++ b/drivers/clk/qcom/clock-qcs615.c @@ -147,16 +147,17 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate) } static const struct gate_clk qcs615_clks[] = { - GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf078, BIT(0)), - GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0xf010, BIT(0)), - GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf07c, BIT(0)), - GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0xf014, BIT(0)), - GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf018, BIT(0)), - GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0)), - GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)), - GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)), - GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c014, BIT(0)), - GATE_CLK(GCC_AHB2PHY_WEST_CLK, 0x6a004, BIT(0)), + GATE_CLK_POLLED(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf078, BIT(0), 0xf078), + GATE_CLK_POLLED(GCC_USB30_PRIM_MASTER_CLK, 0xf010, BIT(0), 0xf010), + GATE_CLK_POLLED(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf07c, BIT(0), 0xf07c), + GATE_CLK_POLLED(GCC_USB30_PRIM_SLEEP_CLK, 0xf014, BIT(0), 0xf014), + GATE_CLK_POLLED(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf018, BIT(0), 0xf018), + GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0), 0xf050), + GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0), 0xf054), + GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0), 0xf058), + GATE_CLK_POLLED(GCC_USB3_PRIM_CLKREF_CLK, 0x8c014, BIT(0), 0x8c014), + GATE_CLK_POLLED(GCC_AHB2PHY_WEST_CLK, 0x6a004, BIT(0), 0x6a004), + GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT), @@ -169,23 +170,24 @@ static const struct gate_clk qcs615_clks[] = { GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x5200c, GCC_QUPV3_WRAP1_S3_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT), - GATE_CLK(GCC_DISP_HF_AXI_CLK, 0xb038, BIT(0)), - GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)), + + GATE_CLK_POLLED(GCC_DISP_HF_AXI_CLK, 0xb038, BIT(0), 0xb038), + GATE_CLK_POLLED(GCC_DISP_AHB_CLK, 0xb032, BIT(0), 0xb032), /* UFS clocks */ - GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)), - GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770c0, BIT(0)), - GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77014, BIT(0)), - GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77040, BIT(0)), - GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77044, BIT(0)), - GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77018, BIT(0)), - GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7701c, BIT(0)), - GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x77078, BIT(0)), - GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)), - GATE_CLK(GCC_SDCC1_AHB_CLK, 0x12008, BIT(0)), - GATE_CLK(GCC_SDCC1_APPS_CLK, 0x12004, BIT(0)), - GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x1200c, BIT(0)), - GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0)), - GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)) + GATE_CLK_POLLED(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0), 0x77010), + GATE_CLK_POLLED(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770c0, BIT(0), 0x770c0), + GATE_CLK_POLLED(GCC_UFS_PHY_AHB_CLK, 0x77014, BIT(0), 0x77014), + GATE_CLK_POLLED(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77040, BIT(0), 0x77040), + GATE_CLK_POLLED(GCC_UFS_PHY_ICE_CORE_CLK, 0x77044, BIT(0), 0x77044), + GATE_CLK_POLLED(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77018, BIT(0), 0x77018), + GATE_CLK_POLLED(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7701c, BIT(0), 0x7701c), + GATE_CLK_POLLED(GCC_UFS_PHY_PHY_AUX_CLK, 0x77078, BIT(0), 0x77078), + GATE_CLK_POLLED(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0), 0x8c000), + GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK, 0x12008, BIT(0), 0x12008), + GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x12004, BIT(0), 0x12004), + GATE_CLK_POLLED(GCC_SDCC1_ICE_CORE_CLK, 0x1200c, BIT(0), 0x1200c), + GATE_CLK_POLLED(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0), 0x14008), + GATE_CLK_POLLED(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0), 0x14004) }; static int qcs615_enable(struct clk *clk)