diff --git a/drivers/firmware/qcom/memory_dump_dev.c b/drivers/firmware/qcom/memory_dump_dev.c
index 6a2dc5d6d335..3e84a1405d53 100644
--- a/drivers/firmware/qcom/memory_dump_dev.c
+++ b/drivers/firmware/qcom/memory_dump_dev.c
@@ -99,7 +99,35 @@ enum dump_ids {
 	OSM_REG		= 0x163,
 	PCU_REG		= 0x164,
 	FSM_DATA	= 0x165,
+	SPR_CPU0	= 0x1f0,
+	SPR_CPU1	= 0x1f1,
+	SPR_CPU2	= 0x1f2,
+	SPR_CPU3	= 0x1f3,
+	SPR_CPU4	= 0x1f4,
+	SPR_CPU5	= 0x1f5,
+	SPR_CPU6	= 0x1f6,
+	SPR_CPU7	= 0x1f7,
+	SPR_CPU8	= 0x1f8,
+	SPR_CPU9	= 0x1f9,
+	SPR_CPU10	= 0x1fa,
+	SPR_CPU11	= 0x1fb,
 	SCANDUMP_SMMU	= 0x220,
+	CACHE_CPU0	= 0x230,
+	CACHE_CPU1	= 0x231,
+	CACHE_CPU2	= 0x232,
+	CACHE_CPU3	= 0x233,
+	CACHE_CPU4	= 0x234,
+	CACHE_CPU5	= 0x235,
+	CACHE_CPU6	= 0x236,
+	CACHE_CPU7	= 0x237,
+	CACHE_CPU8	= 0x238,
+	CACHE_CPU9	= 0x239,
+	CACHE_CPU10	= 0x23a,
+	CACHE_CPU11	= 0x23b,
+	CACHE_CLUSTER0	= 0x240,
+	CACHE_CLUSTER1	= 0x241,
+	CACHE_CLUSTER2	= 0x242,
+	C_CONTEXT	= 0x250,
 };
 
 static const struct dump_item lemans_items[] = {
@@ -362,11 +390,40 @@ static const struct dump_item hamoa_items[] = {
 	{ C900_CONTEXT, 0x800, "c900-context" },
 	{ C1000_CONTEXT, 0x800, "c1000-context" },
 	{ C1100_CONTEXT, 0x800, "c1100-context" },
+	{ CPUSS_REG, 0xa00000, "cpuss-reg" },
 	{ RPMH, 0xc10000, "rpmh" },
 	{ PMIC, 0x200000, "pmic" },
 	{ ETF_SWAO, 0x10000, "etf-swao" },
 	{ ETR_REG, 0x4000, "etr-reg" },
 	{ ETFSWAO_REG, 0x4000, "etfswao-reg" },
+	{ SPR_CPU0, 0x2000, "spr-cpu0" },
+	{ SPR_CPU1, 0x2000, "spr-cpu1" },
+	{ SPR_CPU2, 0x2000, "spr-cpu2" },
+	{ SPR_CPU3, 0x2000, "spr-cpu3" },
+	{ SPR_CPU4, 0x2000, "spr-cpu4" },
+	{ SPR_CPU5, 0x2000, "spr-cpu5" },
+	{ SPR_CPU6, 0x2000, "spr-cpu6" },
+	{ SPR_CPU7, 0x2000, "spr-cpu7" },
+	{ SPR_CPU8, 0x2000, "spr-cpu8" },
+	{ SPR_CPU9, 0x2000, "spr-cpu9" },
+	{ SPR_CPU10, 0x2000, "spr-cpu10" },
+	{ SPR_CPU11, 0x2000, "spr-cpu11" },
+	{ CACHE_CPU0, 0x2aa000, "cache-cpu0" },
+	{ CACHE_CPU1, 0x2aa000, "cache-cpu1" },
+	{ CACHE_CPU2, 0x2aa000, "cache-cpu2" },
+	{ CACHE_CPU3, 0x2aa000, "cache-cpu3" },
+	{ CACHE_CPU4, 0x2aa000, "cache-cpu4" },
+	{ CACHE_CPU5, 0x2aa000, "cache-cpu5" },
+	{ CACHE_CPU6, 0x2aa000, "cache-cpu6" },
+	{ CACHE_CPU7, 0x2aa000, "cache-cpu7" },
+	{ CACHE_CPU8, 0x2aa000, "cache-cpu8" },
+	{ CACHE_CPU9, 0x2aa000, "cache-cpu9" },
+	{ CACHE_CPU10, 0x2aa000, "cache-cpu10" },
+	{ CACHE_CPU11, 0x2aa000, "cache-cpu11" },
+	{ CACHE_CLUSTER0, 0x2430000, "cache-cluster0" },
+	{ CACHE_CLUSTER1, 0x2430000, "cache-cluster1" },
+	{ CACHE_CLUSTER2, 0x2430000, "cache-cluster2" },
+	{ C_CONTEXT, 0x2af0, "cpu-context" },
 };
 
 static const struct dump_item glymur_items[] = {
@@ -388,11 +445,40 @@ static const struct dump_item glymur_items[] = {
 	{ C1500_CONTEXT, 0x800, "c1500-context" },
 	{ C1600_CONTEXT, 0x800, "c1600-context" },
 	{ C1700_CONTEXT, 0x800, "c1700-context" },
+	{ CPUSS_REG, 0xa00000, "cpuss-reg" },
 	{ RPMH, 0xc10000, "rpmh" },
 	{ PMIC, 0x200000, "pmic" },
 	{ ETF_SWAO, 0x10000, "etf-swao" },
 	{ ETR_REG, 0x4000, "etr-reg" },
 	{ ETFSWAO_REG, 0x4000, "etfswao-reg" },
+	{ SPR_CPU0, 0x2000, "spr-cpu0" },
+	{ SPR_CPU1, 0x2000, "spr-cpu1" },
+	{ SPR_CPU2, 0x2000, "spr-cpu2" },
+	{ SPR_CPU3, 0x2000, "spr-cpu3" },
+	{ SPR_CPU4, 0x2000, "spr-cpu4" },
+	{ SPR_CPU5, 0x2000, "spr-cpu5" },
+	{ SPR_CPU6, 0x2000, "spr-cpu6" },
+	{ SPR_CPU7, 0x2000, "spr-cpu7" },
+	{ SPR_CPU8, 0x2000, "spr-cpu8" },
+	{ SPR_CPU9, 0x2000, "spr-cpu9" },
+	{ SPR_CPU10, 0x2000, "spr-cpu10" },
+	{ SPR_CPU11, 0x2000, "spr-cpu11" },
+	{ CACHE_CPU0, 0x2aa000, "cache-cpu0" },
+	{ CACHE_CPU1, 0x2aa000, "cache-cpu1" },
+	{ CACHE_CPU2, 0x2aa000, "cache-cpu2" },
+	{ CACHE_CPU3, 0x2aa000, "cache-cpu3" },
+	{ CACHE_CPU4, 0x2aa000, "cache-cpu4" },
+	{ CACHE_CPU5, 0x2aa000, "cache-cpu5" },
+	{ CACHE_CPU6, 0x2aa000, "cache-cpu6" },
+	{ CACHE_CPU7, 0x2aa000, "cache-cpu7" },
+	{ CACHE_CPU8, 0x2aa000, "cache-cpu8" },
+	{ CACHE_CPU9, 0x2aa000, "cache-cpu9" },
+	{ CACHE_CPU10, 0x2aa000, "cache-cpu10" },
+	{ CACHE_CPU11, 0x2aa000, "cache-cpu11" },
+	{ CACHE_CLUSTER0, 0x2430000, "cache-cluster0" },
+	{ CACHE_CLUSTER1, 0x2430000, "cache-cluster1" },
+	{ CACHE_CLUSTER2, 0x2430000, "cache-cluster2" },
+	{ C_CONTEXT, 0x4050, "cpu-context" },
 };
 
 static const struct dump_item shikra_items[] = {
diff --git a/drivers/firmware/qcom/memory_dump_v2.c b/drivers/firmware/qcom/memory_dump_v2.c
index 831d1aea86e0..e8a4174ae7bb 100644
--- a/drivers/firmware/qcom/memory_dump_v2.c
+++ b/drivers/firmware/qcom/memory_dump_v2.c
@@ -29,13 +29,7 @@
 
 #define CPUSS_REGDUMP			0xEF
 #define SPR_DUMP_CPU0			0x1F0
-#define SPR_DUMP_CPU1			0x1F1
-#define SPR_DUMP_CPU2			0x1F2
-#define SPR_DUMP_CPU3			0x1F3
-#define SPR_DUMP_CPU4			0x1F4
-#define SPR_DUMP_CPU5			0x1F5
-#define SPR_DUMP_CPU6			0x1F6
-#define SPR_DUMP_CPU7			0x1F7
+#define SPR_DUMP_CPU11			0x1Fb
 #define SPR_DATA_HEADER_SIZE	5
 #define SPR_DATA_HEADER_TAIL_SIZE	1
 #define SPR_INPUT_DATA_TAIL_SIZE	1
@@ -1061,7 +1055,7 @@ static int mem_dump_alloc(struct platform_device *pdev)
 				id);
 
 		if ((id == CPUSS_REGDUMP) ||
-				((id >= SPR_DUMP_CPU0) && (id <= SPR_DUMP_CPU7)))
+				((id >= SPR_DUMP_CPU0) && (id <= SPR_DUMP_CPU11)))
 			initialized = cpuss_dump_init(pdev,
 				(dump_vaddr + MSM_DUMP_DATA_SIZE), size, id);