From 5ae59af9c921542e117311cf5340c547c6386dd5 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Sun, 5 Jul 2026 07:35:56 +0200 Subject: [PATCH 1/4] refactor: bump `common_cells` to v2.0.0-beta --- Bender.yml | 2 +- src/channel_allocator/slink_ch_alloc.sv | 10 +++---- .../slink_stream_dechopper.sv | 6 ++--- src/slink.sv | 2 +- src/slink_link_layer.sv | 27 ++++++++++--------- src/slink_phys_layer.sv | 8 +++--- src/slink_prot_layer.sv | 8 +++--- 7 files changed, 33 insertions(+), 30 deletions(-) diff --git a/Bender.yml b/Bender.yml index b648620..afc283b 100644 --- a/Bender.yml +++ b/Bender.yml @@ -11,7 +11,7 @@ package: - "Paul Scheffler " dependencies: - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.28.0 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 2.0.0-beta } axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0 } axi_stream: { git: "https://github.com/pulp-platform/axi_stream.git", version: 0.1.1 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } diff --git a/src/channel_allocator/slink_ch_alloc.sv b/src/channel_allocator/slink_ch_alloc.sv index 4439048..62325ed 100644 --- a/src/channel_allocator/slink_ch_alloc.sv +++ b/src/channel_allocator/slink_ch_alloc.sv @@ -163,13 +163,12 @@ module slink_ch_alloc // auto-flushing) is already stalled. Without the synchronization FIFO, parts // of the late arriving packet would be accidently merged into the earlier partial // packet if it wasn't for this FIFO acting as the sync barrier. - stream_register #( - .T ( slice_payload_t ) + cc_stream_register #( + .data_t ( slice_payload_t ) ) i_rx_recv_barrier ( .clk_i, .rst_ni, .clr_i ( cfg_rx_clear_i ), - .testmode_i ( 1'b0 ), .data_i ( s_rx_recv_barrier_payload_in ), .valid_i ( s_rx_recv_barrier_valid_in ), .ready_o ( s_rx_recv_barrier_ready_out ), @@ -205,12 +204,13 @@ module slink_ch_alloc assign s_rx_despreader2slice_valid = |s_rx_despreader2slice_payload.valid; - spill_register #( - .T(slice_payload_t), + cc_spill_register #( + .data_t(slice_payload_t), .Bypass(1'b0) ) i_rx_decoupling_slice ( .clk_i, .rst_ni, + .clr_i ( 1'b0 ), .valid_i ( s_rx_despreader2slice_valid ), .ready_o ( s_rx_slice2despreader_ready ), .data_i ( s_rx_despreader2slice_payload ), diff --git a/src/channel_allocator/slink_stream_dechopper.sv b/src/channel_allocator/slink_stream_dechopper.sv index 4935633..91335ea 100644 --- a/src/channel_allocator/slink_stream_dechopper.sv +++ b/src/channel_allocator/slink_stream_dechopper.sv @@ -55,9 +55,9 @@ module slink_stream_dechopper #( assign s_out_buffer_clear = output_valid_q; // Count trailing 1s - lzc #( - .WIDTH(Width), - .MODE(0) + cc_lzc #( + .Width(Width), + .Mode(cc_pkg::LZC_TRAILING_ZERO_CNT) ) i_lzc( .in_i(~valid_i), .cnt_o(s_chopsize), diff --git a/src/slink.sv b/src/slink.sv index eab374b..33c080f 100644 --- a/src/slink.sv +++ b/src/slink.sv @@ -222,7 +222,7 @@ module slink .cfg_flow_control_fifo_clear_i ( cfg_flow_control_fifo_clear ), .cfg_raw_mode_en_i ( reg2hw.raw_mode_en.raw_mode_en.value ), .cfg_raw_mode_in_ch_sel_i ( - reg2hw.raw_mode_in_ch_sel.raw_mode_in_ch_sel.value[cf_math_pkg::idx_width(NumChannels)-1:0] ), + reg2hw.raw_mode_in_ch_sel.raw_mode_in_ch_sel.value[cc_pkg::idx_width(NumChannels)-1:0] ), .cfg_raw_mode_in_data_o ( raw_mode_in_data_out ), .cfg_raw_mode_in_data_valid_o ( raw_mode_in_data_valid ), .cfg_raw_mode_in_data_ready_i ( diff --git a/src/slink_link_layer.sv b/src/slink_link_layer.sv index 9cf38c1..7b3cbb2 100644 --- a/src/slink_link_layer.sv +++ b/src/slink_link_layer.sv @@ -65,6 +65,8 @@ module slink_link_layer #( logic raw_mode_fifo_full, raw_mode_fifo_empty; logic raw_mode_fifo_push, raw_mode_fifo_pop; phy_data_t raw_mode_fifo_data_in, raw_mode_fifo_data_out; + // `cc_fifo` widened `usage_o` to `cc_pkg::cnt_width(Depth)`; slice it back to the legacy width + logic [cc_pkg::cnt_width(RawModeFifoDepth)-1:0] raw_mode_fifo_usage; ///////////////// @@ -77,14 +79,14 @@ module slink_link_layer #( logic flow_control_fifo_valid_out, flow_control_fifo_ready_out; logic flow_control_fifo_valid_in, flow_control_fifo_ready_in; - stream_fifo #( - .T(phy_data_chan_t), - .DEPTH (RecvFifoDepth) + cc_stream_fifo #( + .data_t(phy_data_chan_t), + .Depth (RecvFifoDepth) ) i_flow_control_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( cfg_flow_control_fifo_clear_i ), - .testmode_i ( 1'b0 ), .usage_o ( ), .data_i ( data_in_i ), .valid_i ( flow_control_fifo_valid_in ), @@ -95,13 +97,12 @@ module slink_link_layer #( ); for (genvar i = 0; i < PayloadSplits; i++) begin : gen_recv_reg - stream_register #( - .T (phy_data_chan_t) + cc_stream_register #( + .data_t (phy_data_chan_t) ) i_recv_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .clr_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .valid_i ( recv_reg_in_valid[i] ), .ready_o ( recv_reg_in_ready[i] ), .data_i ( flow_control_fifo_data_out ), @@ -215,22 +216,24 @@ module slink_link_layer #( end end - fifo_v3 #( - .dtype ( phy_data_t ), - .DEPTH ( RawModeFifoDepth ) + cc_fifo #( + .data_t ( phy_data_t ), + .Depth ( RawModeFifoDepth ) ) i_raw_mode_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( cfg_raw_mode_out_data_fifo_clear_i ), - .testmode_i ( 1'b0 ), .full_o ( raw_mode_fifo_full ), .empty_o ( raw_mode_fifo_empty ), - .usage_o ( cfg_raw_mode_out_data_fifo_fill_state_o ), + .usage_o ( raw_mode_fifo_usage ), .data_i ( raw_mode_fifo_data_in ), .push_i ( raw_mode_fifo_push ), .data_o ( raw_mode_fifo_data_out ), .pop_i ( raw_mode_fifo_pop ) ); + assign cfg_raw_mode_out_data_fifo_fill_state_o = + raw_mode_fifo_usage[Log2RawModeFifoDepth-1:0]; assign cfg_raw_mode_out_data_fifo_is_full_o = raw_mode_fifo_full; assign raw_mode_fifo_push = cfg_raw_mode_out_data_valid_i & ~raw_mode_fifo_full; diff --git a/src/slink_phys_layer.sv b/src/slink_phys_layer.sv index c6fc6bb..4680b29 100644 --- a/src/slink_phys_layer.sv +++ b/src/slink_phys_layer.sv @@ -134,10 +134,10 @@ module slink_phys_layer_rx #( // CLOCK DOMAIN CROSSING // /////////////////////////////// - cdc_fifo_gray #( - .T ( phy_data_t ), - .LOG_DEPTH ( $clog2(FifoDepth) + CdcSyncStages ), - .SYNC_STAGES ( CdcSyncStages ) + cc_cdc_fifo_gray #( + .data_t ( phy_data_t ), + .LogDepth ( $clog2(FifoDepth) + CdcSyncStages ), + .SyncStages ( CdcSyncStages ) ) i_cdc_in ( .src_clk_i ( ddr_rcv_clk_i ), .src_rst_ni ( rst_ni ), diff --git a/src/slink_prot_layer.sv b/src/slink_prot_layer.sv index fd309d1..2196d17 100644 --- a/src/slink_prot_layer.sv +++ b/src/slink_prot_layer.sv @@ -219,14 +219,14 @@ module slink_prot_layer #( assign axis_out_req_o.t.data = axis_reg_data_out; assign axis_reg_ready_out = axis_out_rsp_i.tready; - stream_fifo #( - .DEPTH ( 2 ), - .T ( payload_t ) + cc_stream_fifo #( + .Depth ( 2 ), + .data_t ( payload_t ) ) i_axis_out_reg ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), .usage_o ( ), .valid_i ( axis_reg_valid_in ), .ready_o ( axis_reg_ready_in ), From bcdca2faf022f4dea45764b45b0f13add1a90a60 Mon Sep 17 00:00:00 2001 From: Lorenzo Leone Date: Wed, 5 Aug 2026 17:38:54 +0200 Subject: [PATCH 2/4] Bump deps --- Bender.lock | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Bender.lock b/Bender.lock index 82ce3a4..2c2d25a 100644 --- a/Bender.lock +++ b/Bender.lock @@ -7,8 +7,8 @@ packages: dependencies: - common_cells axi: - revision: a256a3b86394fedf19e361047fccfdd7f6ef83e4 - version: 0.39.9 + revision: a8c53cee2520d328d390c507c88818e8ac144c8c + version: 0.39.10 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -23,8 +23,8 @@ packages: dependencies: - common_cells common_cells: - revision: 9ca8a7655f741e7dd5736669a20a301325194c28 - version: 1.39.0 + revision: 63b7c50d43e462b59506f69d341ff1e40202866d + version: 2.0.0-beta.3 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -37,8 +37,8 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] tech_cells_generic: - revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf - version: 0.2.13 + revision: 3a3de73632a06826b1bd9c65a0a2e92b32016845 + version: 0.2.14 source: Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: From be56542029ed4a88437c9b79f65be59eac747423 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Thu, 6 Aug 2026 12:02:48 +0200 Subject: [PATCH 3/4] chore: remove redundant comment --- src/slink_link_layer.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/src/slink_link_layer.sv b/src/slink_link_layer.sv index 7b3cbb2..a02983e 100644 --- a/src/slink_link_layer.sv +++ b/src/slink_link_layer.sv @@ -65,7 +65,6 @@ module slink_link_layer #( logic raw_mode_fifo_full, raw_mode_fifo_empty; logic raw_mode_fifo_push, raw_mode_fifo_pop; phy_data_t raw_mode_fifo_data_in, raw_mode_fifo_data_out; - // `cc_fifo` widened `usage_o` to `cc_pkg::cnt_width(Depth)`; slice it back to the legacy width logic [cc_pkg::cnt_width(RawModeFifoDepth)-1:0] raw_mode_fifo_usage; From 0d1654ad559f21da5035a2dfa5143048eddf9df6 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Thu, 6 Aug 2026 13:41:04 +0200 Subject: [PATCH 4/4] fix: width of counter --- src/regs/slink_reg.rdl | 2 +- src/regs/slink_reg_pkg.sv | 4 ++-- src/slink.sv | 2 +- src/slink_link_layer.sv | 9 +++------ 4 files changed, 7 insertions(+), 10 deletions(-) diff --git a/src/regs/slink_reg.rdl b/src/regs/slink_reg.rdl index 0ed04f2..6e76feb 100644 --- a/src/regs/slink_reg.rdl +++ b/src/regs/slink_reg.rdl @@ -147,7 +147,7 @@ addrmap slink_reg #( sw = r; hw = w; desc = "The number of elements currently stored in the RAW mode TX FIFO that are ready to be sent."; - } fill_state[8+Log2RawModeTXFifoDepth-1:8] = 0x0; + } fill_state[8+Log2RawModeTXFifoDepth:8] = 0x0; field { name = "is_full"; sw = r; diff --git a/src/regs/slink_reg_pkg.sv b/src/regs/slink_reg_pkg.sv index 6f770a5..f89afc1 100644 --- a/src/regs/slink_reg_pkg.sv +++ b/src/regs/slink_reg_pkg.sv @@ -42,8 +42,8 @@ package slink_reg_pkg; typedef struct packed { logic is_full; - logic [19:0] _reserved_30_11; - logic [2:0] fill_state; + logic [18:0] _reserved_30_12; + logic [3:0] fill_state; logic [7:0] _reserved_7_0; } slink_reg__raw_mode_out_data_fifo_ctrl__external__fields__in_t; diff --git a/src/slink.sv b/src/slink.sv index 33c080f..5814ca0 100644 --- a/src/slink.sv +++ b/src/slink.sv @@ -193,7 +193,7 @@ module slink end phy_data_t raw_mode_in_data_out; - logic [$clog2(RawModeFifoDepth)-1:0] raw_mode_out_data_fill_state; + logic [cc_pkg::cnt_width(RawModeFifoDepth)-1:0] raw_mode_out_data_fill_state; logic raw_mode_out_data_is_full; slink_link_layer #( diff --git a/src/slink_link_layer.sv b/src/slink_link_layer.sv index a02983e..778a5c7 100644 --- a/src/slink_link_layer.sv +++ b/src/slink_link_layer.sv @@ -19,7 +19,7 @@ module slink_link_layer #( parameter int RawModeFifoDepth = 8, parameter int PayloadSplits = -1, parameter bit EnDdr = 1'b1, - localparam int Log2NumChannels = (NumChannels > 1)? $clog2(NumChannels) : 1, + localparam int Log2NumChannels = cc_pkg::idx_width(NumChannels), localparam int unsigned Log2RawModeFifoDepth = $clog2(RawModeFifoDepth) ) ( input logic clk_i, @@ -48,7 +48,7 @@ module slink_link_layer #( input logic cfg_raw_mode_out_data_valid_i, input logic cfg_raw_mode_out_en_i, input logic cfg_raw_mode_out_data_fifo_clear_i, - output logic [Log2RawModeFifoDepth-1:0] cfg_raw_mode_out_data_fifo_fill_state_o, + output logic [Log2RawModeFifoDepth:0] cfg_raw_mode_out_data_fifo_fill_state_o, output logic cfg_raw_mode_out_data_fifo_is_full_o ); @@ -65,7 +65,6 @@ module slink_link_layer #( logic raw_mode_fifo_full, raw_mode_fifo_empty; logic raw_mode_fifo_push, raw_mode_fifo_pop; phy_data_t raw_mode_fifo_data_in, raw_mode_fifo_data_out; - logic [cc_pkg::cnt_width(RawModeFifoDepth)-1:0] raw_mode_fifo_usage; ///////////////// @@ -225,14 +224,12 @@ module slink_link_layer #( .flush_i ( cfg_raw_mode_out_data_fifo_clear_i ), .full_o ( raw_mode_fifo_full ), .empty_o ( raw_mode_fifo_empty ), - .usage_o ( raw_mode_fifo_usage ), + .usage_o ( cfg_raw_mode_out_data_fifo_fill_state_o ), .data_i ( raw_mode_fifo_data_in ), .push_i ( raw_mode_fifo_push ), .data_o ( raw_mode_fifo_data_out ), .pop_i ( raw_mode_fifo_pop ) ); - assign cfg_raw_mode_out_data_fifo_fill_state_o = - raw_mode_fifo_usage[Log2RawModeFifoDepth-1:0]; assign cfg_raw_mode_out_data_fifo_is_full_o = raw_mode_fifo_full; assign raw_mode_fifo_push = cfg_raw_mode_out_data_valid_i & ~raw_mode_fifo_full;