From 3f27066969b3cbc6fd6471f1ffc0c1172b710dca Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Wed, 23 Jul 2025 14:42:20 +0200 Subject: [PATCH 1/4] Add make targets to run simulation with VCS --- README.md | 5 +++++ vcs/.gitignore | 11 +++++++++++ 2 files changed, 16 insertions(+) create mode 100644 vcs/.gitignore diff --git a/README.md b/README.md index c341ea3db..40c040c0e 100644 --- a/README.md +++ b/README.md @@ -184,6 +184,11 @@ If you have Questasim/Modelsim, you can also run: cd vsim && ./run_vsim.sh --build --run ../sw/bin/helloworld.hex ``` +If you have VCS, you can also run: +```sh +cd vcs && ./run_vcs.sh --build --run ../sw/bin/helloworld.hex +``` + All `run_` scripts have a `--help` you can use to orient yourself. ### Building on Croc diff --git a/vcs/.gitignore b/vcs/.gitignore new file mode 100644 index 000000000..64fe0bd58 --- /dev/null +++ b/vcs/.gitignore @@ -0,0 +1,11 @@ +AN.DB +work.lib++ +tb_croc_soc.sim* +vc_hdrs.h +csrc +compile_rtl.sh +ucli.key +croc.fst +compile.log +novas* +transcript.log From 4581616bafe59e393ec33b0768934747312e2c4f Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Wed, 23 Jul 2025 16:13:54 +0200 Subject: [PATCH 2/4] Add VCS yosys flow Co-authored-by: Philippe Sauter --- vcs/.gitignore | 5 +++-- vcs/compile_tech.sh | 15 +++++++++++++++ vsim/compile_tech.tcl | 1 - 3 files changed, 18 insertions(+), 3 deletions(-) create mode 100755 vcs/compile_tech.sh diff --git a/vcs/.gitignore b/vcs/.gitignore index 64fe0bd58..9d596de43 100644 --- a/vcs/.gitignore +++ b/vcs/.gitignore @@ -1,11 +1,12 @@ AN.DB work.lib++ -tb_croc_soc.sim* +tb_croc_soc* vc_hdrs.h csrc -compile_rtl.sh ucli.key croc.fst +compile_rtl.sh +compile_netlist.sh compile.log novas* transcript.log diff --git a/vcs/compile_tech.sh b/vcs/compile_tech.sh new file mode 100755 index 000000000..a672b3722 --- /dev/null +++ b/vcs/compile_tech.sh @@ -0,0 +1,15 @@ +$VLOGAN -sverilog \ + -full64 \ + -assert svaext +v2k -kdb -override_timescale=1ns/10ps -debug_access+all \ + "+define+FUNCTIONAL" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_64x64_c2_bm_bist.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x64_c2_bm_bist.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_512x32_c2_bm_bist.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_512x64_c2_bm_bist.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_2048x64_c2_bm_bist.v" \ + "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v" \ + "$ROOT/ihp13/tc_sram_impl.sv" \ + "$ROOT/ihp13/tc_clk.sv" diff --git a/vsim/compile_tech.tcl b/vsim/compile_tech.tcl index 1760c27d9..3deb6fe9d 100644 --- a/vsim/compile_tech.tcl +++ b/vsim/compile_tech.tcl @@ -21,7 +21,6 @@ if {[catch { vlog -incr -sv \ "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v" \ "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_2048x64_c2_bm_bist.v" \ "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v" \ - "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v" \ "$ROOT/ihp13/tc_sram_impl.sv" \ "$ROOT/ihp13/tc_clk.sv" \ }]} {return 1} From 9c892c07d5cdc0e378a08d7c315cc765fc974f1e Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Wed, 23 Jul 2025 16:33:44 +0200 Subject: [PATCH 3/4] Add VCS openroad flow --- Bender.yml | 11 ++++++++--- vcs/.gitignore | 2 +- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/Bender.yml b/Bender.yml index 89e2ecdfc..c3636b4a0 100644 --- a/Bender.yml +++ b/Bender.yml @@ -36,7 +36,7 @@ sources: # add your design files containing anything but modules (packages) here # RTL - - target: not(netlist_yosys) + - target: not(any(netlist_yosys, netlist_openroad)) files: # Level 1 - rtl/core_wrap.sv @@ -53,16 +53,21 @@ sources: # Level 3 - rtl/croc_soc.sv - - target: not(fpga) + - target: not(any(fpga, netlist_yosys, netlist_openroad)) files: # Level 0 - rtl/croc_chip.sv - # netlist for simulation + # yosys netlist for simulation - target: netlist_yosys files: - yosys/out/netlist_debug.v + # openroad netlist for simulation + - target: netlist_openroad + files: + - openroad/out/croc.v + - target: any(simulation, verilator) files: - rtl/test/tb_croc_pkg.sv diff --git a/vcs/.gitignore b/vcs/.gitignore index 9d596de43..ded2ecc6f 100644 --- a/vcs/.gitignore +++ b/vcs/.gitignore @@ -6,7 +6,7 @@ csrc ucli.key croc.fst compile_rtl.sh -compile_netlist.sh +compile_netlist* compile.log novas* transcript.log From 0bc88a022c34e5374dbbc49fdacb4fda0a1d5931 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 24 Feb 2026 17:05:15 +0100 Subject: [PATCH 4/4] Add VCS run script and adapt to script-based flow Adapt VCS simulation flow to use a standalone run_vcs.sh script following the same pattern as run_vsim.sh, run_verilator.sh, etc. Replace Makefile targets with CLI options in the run script. Co-Authored-By: Claude Opus 4.6 Co-authored-by: Philippe Sauter --- rtl/test/croc_vip.sv | 4 +- vcs/.gitignore | 1 + vcs/compile_tech.sh | 22 ++-- vcs/run_vcs.sh | 273 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 287 insertions(+), 13 deletions(-) create mode 100755 vcs/run_vcs.sh diff --git a/rtl/test/croc_vip.sv b/rtl/test/croc_vip.sv index 608b02524..7330cd04f 100644 --- a/rtl/test/croc_vip.sv +++ b/rtl/test/croc_vip.sv @@ -350,7 +350,7 @@ module croc_vip #( if (uart_read_buf.size() > 0) begin automatic string uart_str = ""; foreach (uart_read_buf[i]) begin - uart_str = {uart_str, uart_read_buf[i]}; + uart_str = {uart_str, string'(uart_read_buf[i])}; end $display("@%t | [UART] %s", $time, uart_str); uart_read_buf.push_back(bite); @@ -370,7 +370,7 @@ module croc_vip #( if (uart_read_buf.size() > 0) begin automatic string uart_str = ""; foreach (uart_read_buf[i]) begin - uart_str = {uart_str, uart_read_buf[i]}; + uart_str = {uart_str, string'(uart_read_buf[i])}; end $display("@%t | [UART] %s", $time, uart_str); end diff --git a/vcs/.gitignore b/vcs/.gitignore index ded2ecc6f..8aa315af4 100644 --- a/vcs/.gitignore +++ b/vcs/.gitignore @@ -10,3 +10,4 @@ compile_netlist* compile.log novas* transcript.log +reports/ diff --git a/vcs/compile_tech.sh b/vcs/compile_tech.sh index a672b3722..4464b2c13 100755 --- a/vcs/compile_tech.sh +++ b/vcs/compile_tech.sh @@ -2,14 +2,14 @@ $VLOGAN -sverilog \ -full64 \ -assert svaext +v2k -kdb -override_timescale=1ns/10ps -debug_access+all \ "+define+FUNCTIONAL" \ - "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v" \ - "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v" \ - "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_64x64_c2_bm_bist.v" \ - "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x64_c2_bm_bist.v" \ - "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_512x32_c2_bm_bist.v" \ - "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_512x64_c2_bm_bist.v" \ - "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v" \ - "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_2048x64_c2_bm_bist.v" \ - "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v" \ - "$ROOT/ihp13/tc_sram_impl.sv" \ - "$ROOT/ihp13/tc_clk.sv" + "../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v" \ + "../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v" \ + "../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_64x64_c2_bm_bist.v" \ + "../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x64_c2_bm_bist.v" \ + "../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_512x32_c2_bm_bist.v" \ + "../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_512x64_c2_bm_bist.v" \ + "../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v" \ + "../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_2048x64_c2_bm_bist.v" \ + "../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v" \ + "../ihp13/tc_sram_impl.sv" \ + "../ihp13/tc_clk.sv" diff --git a/vcs/run_vcs.sh b/vcs/run_vcs.sh new file mode 100755 index 000000000..d8ee231fc --- /dev/null +++ b/vcs/run_vcs.sh @@ -0,0 +1,273 @@ +#!/bin/bash +# Copyright (c) 2026 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Authors: +# - Michael Rogenmoser + + +set -e # Exit on error +set -u # Error on undefined vars + + +################ +# Setup +################ +# Source environment +source "../env.sh" + +VLOGAN=${VLOGAN:-vlogan} +VCS=${VCS:-vcs} + +VCS_SCRIPT_ARGS="-assert svaext +v2k -kdb -override_timescale=1ns/10ps -debug_access+all" +VCS_COMPILE_ARGS="-kdb -lca -sverilog -full64 -j8 -l compile.log +vcs+fsdbon -debug_access+all +lint=TFIPC-L +lint=PCWM +warn=noCWUC +warn=noUII-L -override_timescale=1ns/10ps" + +mkdir -p reports + +################ +# Helpers +################ + +show_help() { + cat << EOF +VCS Coordinator + +Usage: + ./run_vcs.sh [OPTIONS] + +Options: + --help, -h Show this help message + --dry-run, -n Only print commands instead of executing + --verbose, -v Print commands while executing + --flist Regenerate compile scripts (compile_rtl.sh, compile_netlist_yosys.sh, compile_netlist_openroad.sh) + --build Compile Croc RTL in VCS + --build-netlist-yosys Compile Croc post-Yosys-synthesis netlist in VCS + --build-netlist-openroad Compile Croc post-OpenROAD netlist in VCS + --run BINARY Run binary in VCS + +Example: + # Build and run RTL simulation with given binary + ./run_vcs.sh --build --run ../sw/bin/helloworld.hex + +EOF + exit 0 +} + + +run_cmd() { + if [ "$DRYRUN" = 1 ]; then + echo $1 + else + eval $1 + fi +} + + +generate_rtl_flist() { + run_cmd "echo [INFO][Bender] Generate compile_rtl.sh" + run_cmd "bender \ + script vcs \ + -t rtl \ + -t vcs \ + -t simulation \ + -t verilator \ + -DSYNTHESIS \ + -DSIMULATION \ + --vlog-arg=\"${VCS_SCRIPT_ARGS}\" \ + --vlogan-bin=\"${VLOGAN}\" \ + > compile_rtl.sh" + + run_cmd "echo [INFO][Bender] Remove absolute paths" + run_cmd "sed -i 's|${CROC_ROOT}|..|g' compile_rtl.sh" + run_cmd "chmod +x compile_rtl.sh" + + run_cmd "echo [INFO][Bender] File list generated: compile_rtl.sh" +} + + +generate_netlist_yosys_flist() { + run_cmd "echo [INFO][Bender] Generate compile_netlist_yosys.sh" + run_cmd "bender \ + script vcs \ + -t ihp13 \ + -t vcs \ + -t simulation \ + -t verilator \ + -t netlist_yosys \ + -DSYNTHESIS \ + -DSIMULATION \ + --vlog-arg=\"${VCS_SCRIPT_ARGS}\" \ + --vlogan-bin=\"${VLOGAN}\" \ + > compile_netlist_yosys.sh" + + run_cmd "echo [INFO][Bender] Append tech compilation" + run_cmd "cat compile_tech.sh >> compile_netlist_yosys.sh" + + run_cmd "echo [INFO][Bender] Remove absolute paths" + run_cmd "sed -i 's|${CROC_ROOT}|..|g' compile_netlist_yosys.sh" + run_cmd "chmod +x compile_netlist_yosys.sh" + + run_cmd "echo [INFO][Bender] File list generated: compile_netlist_yosys.sh" +} + + +generate_netlist_openroad_flist() { + if [ ! -f "../openroad/out/croc.v" ]; then + run_cmd "echo [WARNING][Bender] Skipping OpenROAD netlist compile script: ../openroad/out/croc.v not found" + run_cmd "rm -f compile_netlist_openroad.sh" + return 0 + fi + + run_cmd "echo [INFO][Bender] Generate compile_netlist_openroad.sh" + run_cmd "bender \ + script vcs \ + -t ihp13 \ + -t vcs \ + -t simulation \ + -t verilator \ + -t netlist_openroad \ + -DSYNTHESIS \ + -DSIMULATION \ + --vlog-arg=\"${VCS_SCRIPT_ARGS}\" \ + --vlogan-bin=\"${VLOGAN}\" \ + > compile_netlist_openroad.sh" + + run_cmd "echo [INFO][Bender] Append tech compilation" + run_cmd "cat compile_tech.sh >> compile_netlist_openroad.sh" + + run_cmd "echo [INFO][Bender] Remove absolute paths" + run_cmd "sed -i 's|${CROC_ROOT}|..|g' compile_netlist_openroad.sh" + run_cmd "chmod +x compile_netlist_openroad.sh" + + run_cmd "echo [INFO][Bender] File list generated: compile_netlist_openroad.sh" +} + + +compile_rtl() { + run_cmd "echo [INFO][VCS] Compile RTL" + run_cmd "./compile_rtl.sh > reports/compile_rtl.log 2>&1" + run_cmd "${VCS} ${VCS_COMPILE_ARGS} -o tb_croc_soc.sim tb_croc_soc > reports/elaborate_rtl.log 2>&1" + + run_cmd "echo [INFO][VCS] Check reports/elaborate_rtl.log" + run_cmd "echo --- VCS compilation report --- > reports/compile_rtl.rpt" + run_cmd "echo Errors: >> reports/compile_rtl.rpt" + run_cmd "grep Error reports/elaborate_rtl.log >> reports/compile_rtl.rpt || true" + run_cmd "echo >> reports/compile_rtl.rpt" + run_cmd "echo Warnings: >> reports/compile_rtl.rpt" + run_cmd "grep Warning reports/elaborate_rtl.log >> reports/compile_rtl.rpt || true" + + run_cmd "echo [INFO][VCS] RTL compilation done" +} + + +compile_netlist_yosys() { + run_cmd "echo [INFO][VCS] Compile Yosys post-synthesis netlist" + run_cmd "./compile_netlist_yosys.sh > reports/compile_netlist_yosys.log 2>&1" + run_cmd "${VCS} ${VCS_COMPILE_ARGS} -o tb_croc_soc_yosys.sim tb_croc_soc > reports/elaborate_netlist_yosys.log 2>&1" + + run_cmd "echo [INFO][VCS] Yosys netlist compilation done" +} + + +compile_netlist_openroad() { + run_cmd "echo [INFO][VCS] Compile OpenROAD post-synthesis netlist" + run_cmd "./compile_netlist_openroad.sh > reports/compile_netlist_openroad.log 2>&1" + run_cmd "${VCS} ${VCS_COMPILE_ARGS} -o tb_croc_soc_openroad.sim tb_croc_soc > reports/elaborate_netlist_openroad.log 2>&1" + + run_cmd "echo [INFO][VCS] OpenROAD netlist compilation done" +} + + +run_vcs() { + run_cmd "./tb_croc_soc.sim \ + +fsdb+all=on \ + +binary=$1 \ + -l transcript.log" +} + + +run_vcs_yosys() { + run_cmd "./tb_croc_soc_yosys.sim \ + +fsdb+all=on \ + +binary=$1 \ + -l transcript.log" +} + + +run_vcs_openroad() { + run_cmd "./tb_croc_soc_openroad.sim \ + +fsdb+all=on \ + +binary=$1 \ + -l transcript.log" +} + + +#################### +# Parse Arguments +#################### + +DRYRUN=0 + +# default action if no argument is given +if [ $# -eq 0 ]; then + show_help + return 0 +fi + +# check for global arguments +for arg in "$@"; do + [[ "$arg" == -v || "$arg" == --verbose ]] && set -x + [[ "$arg" == -n || "$arg" == --dry-run ]] && DRYRUN=1 +done + +# parse arguments +while [[ $# -gt 0 ]]; do + case "$1" in + --help|-h) + show_help + ;; + --verbose|-v) + shift + ;; + --dry-run|-n) + shift + ;; + # script-specific commands + --flist) + generate_rtl_flist + generate_netlist_yosys_flist + generate_netlist_openroad_flist + shift + ;; + --build) + compile_rtl + shift + ;; + --build-netlist-yosys) + compile_netlist_yosys + shift + ;; + --build-netlist-openroad) + compile_netlist_openroad + shift + ;; + --run) + run_vcs $2 + shift 2 + ;; + --run-yosys) + run_vcs_yosys $2 + shift 2 + ;; + --run-openroad) + run_vcs_openroad $2 + shift 2 + ;; + # Error handling + *) + echo "[ERROR] Unknown option: $1 (use --help for usage)" >&2 + exit 1 + ;; + esac +done