From 83ef2a934a12f4e6ef971133ce0d84e27a29ab91 Mon Sep 17 00:00:00 2001 From: "Gubrud, Aaron D" Date: Wed, 29 Apr 2026 19:08:51 +0000 Subject: [PATCH 1/2] mainline push test --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 55d6b853..18c1c7f6 100644 --- a/README.md +++ b/README.md @@ -276,3 +276,4 @@ Use `builder/build.sh` to build the dependencies and the application in Docker c ### Subsequent Builds `make` builds the app. It assumes the dependencies have been built previously and that you have Go installed on your development system. See [go.mod](go.mod) for the minimum Go version. + From 470774a78e7797c680217457d98a90744008c624 Mon Sep 17 00:00:00 2001 From: "Gubrud, Aaron D" Date: Thu, 9 Jul 2026 15:55:48 -0700 Subject: [PATCH 2/2] initial gvt5 metrics attempt --- cmd/metrics/loader.go | 2 +- cmd/metrics/loader_component.go | 2 + cmd/metrics/metadata_aarch.go | 2 +- .../resources/component/neoverse-v3/bus.json | 6 + .../component/neoverse-v3/exception.json | 10 ++ .../component/neoverse-v3/general.json | 10 ++ .../component/neoverse-v3/l1d_cache.json | 18 +++ .../component/neoverse-v3/l1i_cache.json | 14 ++ .../component/neoverse-v3/l2_cache.json | 18 +++ .../component/neoverse-v3/memory.json | 18 +++ .../component/neoverse-v3/metrics.json | 149 ++++++++++++++++++ .../component/neoverse-v3/retired.json | 26 +++ .../component/neoverse-v3/spec_operation.json | 18 +++ .../component/neoverse-v3/stall.json | 18 +++ .../resources/component/neoverse-v3/tlb.json | 34 ++++ internal/cpus/cpus.go | 3 + 16 files changed, 346 insertions(+), 2 deletions(-) create mode 100644 cmd/metrics/resources/component/neoverse-v3/bus.json create mode 100644 cmd/metrics/resources/component/neoverse-v3/exception.json create mode 100644 cmd/metrics/resources/component/neoverse-v3/general.json create mode 100644 cmd/metrics/resources/component/neoverse-v3/l1d_cache.json create mode 100644 cmd/metrics/resources/component/neoverse-v3/l1i_cache.json create mode 100644 cmd/metrics/resources/component/neoverse-v3/l2_cache.json create mode 100644 cmd/metrics/resources/component/neoverse-v3/memory.json create mode 100644 cmd/metrics/resources/component/neoverse-v3/metrics.json create mode 100644 cmd/metrics/resources/component/neoverse-v3/retired.json create mode 100644 cmd/metrics/resources/component/neoverse-v3/spec_operation.json create mode 100644 cmd/metrics/resources/component/neoverse-v3/stall.json create mode 100644 cmd/metrics/resources/component/neoverse-v3/tlb.json diff --git a/cmd/metrics/loader.go b/cmd/metrics/loader.go index e011225c..7878ed31 100644 --- a/cmd/metrics/loader.go +++ b/cmd/metrics/loader.go @@ -92,7 +92,7 @@ func NewLoader(uarch string, useLegacyLoader bool) (Loader, error) { case cpus.UarchCWF, cpus.UarchGNR, cpus.UarchGNR_X1, cpus.UarchGNR_X2, cpus.UarchGNR_X3, cpus.UarchGNR_D, cpus.UarchSRF, cpus.UarchSRF_SP, cpus.UarchSRF_AP, cpus.UarchEMR, cpus.UarchEMR_MCC, cpus.UarchEMR_XCC, cpus.UarchSPR, cpus.UarchSPR_MCC, cpus.UarchSPR_XCC, cpus.UarchICX: slog.Debug("Using perfmon loader for microarchitecture", slog.String("uarch", uarch)) return newPerfmonLoader(), nil - case cpus.UarchGraviton2, cpus.UarchGraviton3, cpus.UarchGraviton4, cpus.UarchAxion, cpus.UarchAltraFamily, cpus.UarchAmpereOneAC03, cpus.UarchAmpereOneAC04, cpus.UarchAmpereOneAC04_1: + case cpus.UarchGraviton2, cpus.UarchGraviton3, cpus.UarchGraviton4, cpus.UarchGraviton5, cpus.UarchAxion, cpus.UarchAltraFamily, cpus.UarchAmpereOneAC03, cpus.UarchAmpereOneAC04, cpus.UarchAmpereOneAC04_1: slog.Debug("Using component loader for microarchitecture", slog.String("uarch", uarch)) return newComponentLoader(), nil default: diff --git a/cmd/metrics/loader_component.go b/cmd/metrics/loader_component.go index ed0d890d..6c89ea7d 100644 --- a/cmd/metrics/loader_component.go +++ b/cmd/metrics/loader_component.go @@ -545,6 +545,8 @@ func initializeComponentMetricEvaluable(expression string, evaluatorFunctions ma // the cpus module, to the directory where the associated events and metrics reside func getUarchDir(uarch string) (string, error) { switch uarch { + case cpus.UarchGraviton5: + return "neoverse-v3", nil case cpus.UarchGraviton4, cpus.UarchAxion: return "neoverse-n2-v2", nil case cpus.UarchGraviton2: diff --git a/cmd/metrics/metadata_aarch.go b/cmd/metrics/metadata_aarch.go index b8f4b56d..a848fd11 100644 --- a/cmd/metrics/metadata_aarch.go +++ b/cmd/metrics/metadata_aarch.go @@ -229,7 +229,7 @@ func getARMSlots(scriptOutputs map[string]script.ScriptOutput) (slots int, err e // Used as a fallback when we cannot read the slots from sysfs. func getARMSlotsByArchitecture(uarch string) (slots int, err error) { switch uarch { - case cpus.UarchGraviton4, cpus.UarchAxion: + case cpus.UarchGraviton4, cpus.UarchGraviton5, cpus.UarchAxion: slots = 8 case cpus.UarchGraviton2, cpus.UarchGraviton3: slots = 6 diff --git a/cmd/metrics/resources/component/neoverse-v3/bus.json b/cmd/metrics/resources/component/neoverse-v3/bus.json new file mode 100644 index 00000000..5bb182e6 --- /dev/null +++ b/cmd/metrics/resources/component/neoverse-v3/bus.json @@ -0,0 +1,6 @@ +[ + { + "ArchStdEvent": "BUS_CYCLES", + "PublicDescription": "Counts bus cycles in the CPU. Bus cycles represent a clock cycle in which a transaction could be sent or received on the interface from the CPU to the external bus. Since that interface is driven at the same clock speed as the CPU, this event is a duplicate of CPU_CYCLES." + } +] diff --git a/cmd/metrics/resources/component/neoverse-v3/exception.json b/cmd/metrics/resources/component/neoverse-v3/exception.json new file mode 100644 index 00000000..21168a4b --- /dev/null +++ b/cmd/metrics/resources/component/neoverse-v3/exception.json @@ -0,0 +1,10 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN", + "PublicDescription": "Counts any taken architecturally visible exceptions such as IRQ, FIQ, SError, and other synchronous exceptions. Exceptions are counted whether or not they are taken locally." + }, + { + "ArchStdEvent": "EXC_RETURN", + "PublicDescription": "Counts any architecturally executed exception return instructions. For example: AArch64: ERET" + } +] diff --git a/cmd/metrics/resources/component/neoverse-v3/general.json b/cmd/metrics/resources/component/neoverse-v3/general.json new file mode 100644 index 00000000..c5dcdcf4 --- /dev/null +++ b/cmd/metrics/resources/component/neoverse-v3/general.json @@ -0,0 +1,10 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES", + "PublicDescription": "Counts CPU clock cycles (not timer cycles). The clock measured by this event is defined as the physical clock driving the CPU logic." + }, + { + "ArchStdEvent": "CNT_CYCLES", + "PublicDescription": "Increments at a constant frequency equal to the rate of increment of the System Counter, CNTPCT_EL0." + } +] diff --git a/cmd/metrics/resources/component/neoverse-v3/l1d_cache.json b/cmd/metrics/resources/component/neoverse-v3/l1d_cache.json new file mode 100644 index 00000000..f74d2cdc --- /dev/null +++ b/cmd/metrics/resources/component/neoverse-v3/l1d_cache.json @@ -0,0 +1,18 @@ +[ + { + "ArchStdEvent": "L1D_CACHE_REFILL", + "PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load or store operations that missed in the level 1 data cache. This event only counts one event per cache line." + }, + { + "ArchStdEvent": "L1D_CACHE", + "PublicDescription": "Counts level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic operations) counts as both a write access and read access. Each access to a cache line is counted including the multiple accesses caused by single instructions such as LDM or STM. Each access to other level 1 data or unified memory structures, for example refill buffers, write buffers, and write-back buffers, are also counted." + }, + { + "ArchStdEvent": "L1D_CACHE_WB", + "PublicDescription": "Counts write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache line is evicted from L1 data cache and allocated in the L2 cache or dirty data is written to the L2 and possibly to the next level of cache. This event counts both victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The following cache operations are not counted:\n\n1. Invalidations which do not result in data being transferred out of the L1 (such as evictions of clean data),\n2. Full line writes which write to L2 without writing L1, such as write streaming mode." + }, + { + "ArchStdEvent": "L1D_CACHE_LMISS_RD", + "PublicDescription": "Counts cache line refills into the level 1 data cache from any memory read operations, that incurred additional latency." + } +] diff --git a/cmd/metrics/resources/component/neoverse-v3/l1i_cache.json b/cmd/metrics/resources/component/neoverse-v3/l1i_cache.json new file mode 100644 index 00000000..633f1030 --- /dev/null +++ b/cmd/metrics/resources/component/neoverse-v3/l1i_cache.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL", + "PublicDescription": "Counts cache line refills in the level 1 instruction cache caused by a missed instruction fetch. Instruction fetches may include accessing multiple instructions, but the single cache line allocation is counted once." + }, + { + "ArchStdEvent": "L1I_CACHE", + "PublicDescription": "Counts instruction fetches which access the level 1 instruction cache. Instruction cache accesses caused by cache maintenance operations are not counted." + }, + { + "ArchStdEvent": "L1I_CACHE_LMISS", + "PublicDescription": "Counts cache line refills into the level 1 instruction cache, that incurred additional latency." + } +] diff --git a/cmd/metrics/resources/component/neoverse-v3/l2_cache.json b/cmd/metrics/resources/component/neoverse-v3/l2_cache.json new file mode 100644 index 00000000..84e3836e --- /dev/null +++ b/cmd/metrics/resources/component/neoverse-v3/l2_cache.json @@ -0,0 +1,18 @@ +[ + { + "ArchStdEvent": "L2D_CACHE", + "PublicDescription": "Counts accesses to the level 2 cache due to data accesses. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the first level data cache or translation resolutions due to accesses. This event also counts write back of dirty data from level 1 data cache to the L2 cache." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL", + "PublicDescription": "Counts cache line refills into the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 data cache or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_WB", + "PublicDescription": "Counts write-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CPUs) which return data even if the snoops cause an invalidation. L2 cache line invalidations which do not write data outside the CPU and snoops which return data from an L1 cache are not counted. Data would not be written outside the cache when invalidating a clean cache line." + }, + { + "ArchStdEvent": "L2D_CACHE_LMISS_RD", + "PublicDescription": "Counts cache line refills into the level 2 unified cache from any memory read operations that incurred additional latency." + } +] diff --git a/cmd/metrics/resources/component/neoverse-v3/memory.json b/cmd/metrics/resources/component/neoverse-v3/memory.json new file mode 100644 index 00000000..0963bf19 --- /dev/null +++ b/cmd/metrics/resources/component/neoverse-v3/memory.json @@ -0,0 +1,18 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS", + "PublicDescription": "Counts memory accesses issued by the CPU load store unit, where those accesses are issued due to load or store operations. This event counts memory accesses no matter whether the data is received from any level of cache hierarchy or external memory. If memory accesses are broken up into smaller transactions than what were specified in the load or store instructions, then the event counts those smaller memory transactions." + }, + { + "ArchStdEvent": "LDST_ALIGN_LAT", + "PublicDescription": "Counts the number of memory read and write accesses in a cycle that incurred additional latency, due to the alignment of the address and the size of data being accessed, which results in store crossing a single cache line." + }, + { + "ArchStdEvent": "LD_ALIGN_LAT", + "PublicDescription": "Counts the number of memory read accesses in a cycle that incurred additional latency, due to the alignment of the address and size of data being accessed, which results in load crossing a single cache line." + }, + { + "ArchStdEvent": "ST_ALIGN_LAT", + "PublicDescription": "Counts the number of memory write access in a cycle that incurred additional latency, due to the alignment of the address and size of data being accessed incurred additional latency." + } +] diff --git a/cmd/metrics/resources/component/neoverse-v3/metrics.json b/cmd/metrics/resources/component/neoverse-v3/metrics.json new file mode 100644 index 00000000..11b25691 --- /dev/null +++ b/cmd/metrics/resources/component/neoverse-v3/metrics.json @@ -0,0 +1,149 @@ +[ + { + "MetricName": "backend_stalled_cycles", + "MetricExpr": "STALL_BACKEND / CPU_CYCLES * 100", + "BriefDescription": "This metric is the percentage of cycles that were stalled due to resource constraints in the backend unit of the processor.", + "MetricGroup": "Cycle_Accounting", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "branch_misprediction_ratio", + "MetricExpr": "BR_MIS_PRED_RETIRED / BR_RETIRED", + "BriefDescription": "This metric measures the ratio of branches mispredicted to the total number of branches architecturally executed. This gives an indication of the effectiveness of the branch prediction unit.", + "MetricGroup": "Miss_Ratio;Branch_Effectiveness", + "ScaleUnit": "100percent of branches" + }, + { + "MetricName": "branch_mpki", + "MetricExpr": "BR_MIS_PRED_RETIRED / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of branch mispredictions per thousand instructions executed.", + "MetricGroup": "MPKI;Branch_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "dtlb_mpki", + "MetricExpr": "DTLB_WALK / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of data TLB Walks per thousand instructions executed.", + "MetricGroup": "MPKI;DTLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "dtlb_walk_ratio", + "MetricExpr": "DTLB_WALK / L1D_TLB", + "BriefDescription": "This metric measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication of the effectiveness of the data TLB accesses.", + "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "frontend_stalled_cycles", + "MetricExpr": "STALL_FRONTEND / CPU_CYCLES * 100", + "BriefDescription": "This metric is the percentage of cycles that were stalled due to resource constraints in the frontend unit of the processor.", + "MetricGroup": "Cycle_Accounting", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "ipc", + "MetricExpr": "INST_RETIRED / CPU_CYCLES", + "BriefDescription": "This metric measures the number of instructions retired per cycle.", + "MetricGroup": "General", + "ScaleUnit": "1per cycle" + }, + { + "MetricName": "itlb_mpki", + "MetricExpr": "ITLB_WALK / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of instruction TLB Walks per thousand instructions executed.", + "MetricGroup": "MPKI;ITLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "itlb_walk_ratio", + "MetricExpr": "ITLB_WALK / L1I_TLB", + "BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication of the effectiveness of the instruction TLB accesses.", + "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "l1d_cache_miss_ratio", + "MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE", + "BriefDescription": "This metric measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives an indication of the effectiveness of the level 1 data cache.", + "MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness", + "ScaleUnit": "100percent of cache accesses" + }, + { + "MetricName": "l1d_cache_mpki", + "MetricExpr": "L1D_CACHE_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 1 data cache accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;L1D_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l1d_tlb_miss_ratio", + "MetricExpr": "L1D_TLB_REFILL / L1D_TLB", + "BriefDescription": "This metric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This gives an indication of the effectiveness of the level 1 data TLB.", + "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "l1d_tlb_mpki", + "MetricExpr": "L1D_TLB_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 1 data TLB accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;DTLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l1i_cache_miss_ratio", + "MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE", + "BriefDescription": "This metric measures the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesses. This gives an indication of the effectiveness of the level 1 instruction cache.", + "MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness", + "ScaleUnit": "100percent of cache accesses" + }, + { + "MetricName": "l1i_cache_mpki", + "MetricExpr": "L1I_CACHE_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;L1I_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l1i_tlb_miss_ratio", + "MetricExpr": "L1I_TLB_REFILL / L1I_TLB", + "BriefDescription": "This metric measures the ratio of level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. This gives an indication of the effectiveness of the level 1 instruction TLB.", + "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "l1i_tlb_mpki", + "MetricExpr": "L1I_TLB_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;ITLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l2_cache_miss_ratio", + "MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE", + "BriefDescription": "This metric measures the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives an indication of the effectiveness of the level 2 cache, which is a unified cache that stores both data and instruction. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.", + "MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness", + "ScaleUnit": "100percent of cache accesses" + }, + { + "MetricName": "l2_cache_mpki", + "MetricExpr": "L2D_CACHE_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 2 unified cache accesses missed per thousand instructions executed. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.", + "MetricGroup": "MPKI;L2_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l2_tlb_miss_ratio", + "MetricExpr": "L2D_TLB_REFILL / L2D_TLB", + "BriefDescription": "This metric measures the ratio of level 2 unified TLB accesses missed to the total number of level 2 unified TLB accesses. This gives an indication of the effectiveness of the level 2 TLB.", + "MetricGroup": "Miss_Ratio;ITLB_Effectiveness;DTLB_Effectiveness", + "ScaleUnit": "100percent of TLB accesses" + }, + { + "MetricName": "l2_tlb_mpki", + "MetricExpr": "L2D_TLB_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 2 unified TLB accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;ITLB_Effectiveness;DTLB_Effectiveness", + "ScaleUnit": "1MPKI" + } +] diff --git a/cmd/metrics/resources/component/neoverse-v3/retired.json b/cmd/metrics/resources/component/neoverse-v3/retired.json new file mode 100644 index 00000000..44bdbaf1 --- /dev/null +++ b/cmd/metrics/resources/component/neoverse-v3/retired.json @@ -0,0 +1,26 @@ +[ + { + "ArchStdEvent": "INST_RETIRED", + "PublicDescription": "Counts instructions that have been architecturally executed." + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED", + "PublicDescription": "Counts architecturally executed writes to the CONTEXTIDR_EL1 register, which usually contain the kernel PID and can be output with hardware trace." + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED", + "PublicDescription": "Counts architectural writes to TTBR0/1_EL1. If virtualization host extensions are enabled (by setting the HCR_EL2.E2H bit to 1), then accesses to TTBR0/1_EL1 that are redirected to TTBR0/1_EL2, or accesses to TTBR0/1_EL12, are counted. TTBRn registers are typically updated when the kernel is swapping user-space threads or applications." + }, + { + "ArchStdEvent": "BR_RETIRED", + "PublicDescription": "Counts architecturally executed branches, whether the branch is taken or not. Instructions that explicitly write to the PC are also counted. Note that exception generating instructions, exception return instructions and context synchronization instructions are not counted." + }, + { + "ArchStdEvent": "BR_MIS_PRED_RETIRED", + "PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a pipeline flush." + }, + { + "ArchStdEvent": "OP_RETIRED", + "PublicDescription": "Counts micro-operations that are architecturally executed. This is a count of number of micro-operations retired from the commit queue in a single cycle." + } +] diff --git a/cmd/metrics/resources/component/neoverse-v3/spec_operation.json b/cmd/metrics/resources/component/neoverse-v3/spec_operation.json new file mode 100644 index 00000000..d7795a3b --- /dev/null +++ b/cmd/metrics/resources/component/neoverse-v3/spec_operation.json @@ -0,0 +1,18 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED", + "PublicDescription": "Counts branches which are speculatively executed and mispredicted." + }, + { + "ArchStdEvent": "BR_PRED", + "PublicDescription": "Counts all speculatively executed branches." + }, + { + "ArchStdEvent": "INST_SPEC", + "PublicDescription": "Counts operations that have been speculatively executed." + }, + { + "ArchStdEvent": "OP_SPEC", + "PublicDescription": "Counts micro-operations speculatively executed. This is the count of the number of micro-operations dispatched in a cycle." + } +] diff --git a/cmd/metrics/resources/component/neoverse-v3/stall.json b/cmd/metrics/resources/component/neoverse-v3/stall.json new file mode 100644 index 00000000..0fa82c65 --- /dev/null +++ b/cmd/metrics/resources/component/neoverse-v3/stall.json @@ -0,0 +1,18 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND", + "PublicDescription": "Counts cycles when frontend could not send any micro-operations to the rename stage because of frontend resource stalls caused by fetch memory latency or branch prediction flow stalls. STALL_FRONTEND_SLOTS counts SLOTS during the cycle when this event counts." + }, + { + "ArchStdEvent": "STALL_BACKEND", + "PublicDescription": "Counts cycles whenever the rename unit is unable to send any micro-operations to the backend of the pipeline because of backend resource constraints. Backend resource constraints can include issue stage fullness, execution stage fullness, or other internal pipeline resource fullness. All the backend slots were empty during the cycle when this event counts." + }, + { + "ArchStdEvent": "STALL", + "PublicDescription": "Counts cycles when no operations are sent to the rename unit from the frontend or from the rename unit to the backend for any reason (either frontend or backend stall). This event is the sum of STALL_FRONTEND and STALL_BACKEND" + }, + { + "ArchStdEvent": "STALL_BACKEND_MEM", + "PublicDescription": "Counts cycles when the backend is stalled because there is a pending demand load request in progress in the last level core cache." + } +] diff --git a/cmd/metrics/resources/component/neoverse-v3/tlb.json b/cmd/metrics/resources/component/neoverse-v3/tlb.json new file mode 100644 index 00000000..37f07027 --- /dev/null +++ b/cmd/metrics/resources/component/neoverse-v3/tlb.json @@ -0,0 +1,34 @@ +[ + { + "ArchStdEvent": "L1I_TLB_REFILL", + "PublicDescription": "Counts level 1 instruction TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB." + }, + { + "ArchStdEvent": "L1D_TLB_REFILL", + "PublicDescription": "Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an AT(address translation) instruction." + }, + { + "ArchStdEvent": "L1D_TLB", + "PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operation. Note that load or store instructions can be broken up into multiple memory operations. This event does not count TLB maintenance operations." + }, + { + "ArchStdEvent": "L1I_TLB", + "PublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses in the TLB. This event counts both demand accesses and prefetch or preload generated accesses." + }, + { + "ArchStdEvent": "L2D_TLB_REFILL", + "PublicDescription": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch, except for those caused by TLB maintenance operations and hardware prefetches." + }, + { + "ArchStdEvent": "L2D_TLB", + "PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operations." + }, + { + "ArchStdEvent": "DTLB_WALK", + "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardware prefetchers, and that this event does not count walks triggered by TLB maintenance operations." + }, + { + "ArchStdEvent": "ITLB_WALK", + "PublicDescription": "Counts number of instruction translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event does not count walks triggered by TLB maintenance operations." + } +] diff --git a/internal/cpus/cpus.go b/internal/cpus/cpus.go index 0ce48437..c6b48a3b 100644 --- a/internal/cpus/cpus.go +++ b/internal/cpus/cpus.go @@ -69,6 +69,7 @@ const ( UarchGraviton2 = "Graviton2" UarchGraviton3 = "Graviton3" UarchGraviton4 = "Graviton4" + UarchGraviton5 = "Graviton5" UarchAxion = "Axion" UarchAltraFamily = "Altra Family" UarchAmpereOneAC03 = "AmpereOne AC03" @@ -154,6 +155,7 @@ var cpuCharacteristicsMap = map[string]CPUCharacteristics{ UarchGraviton2: {MicroArchitecture: UarchGraviton2, MemoryChannelCount: 8, LogicalThreadCount: 1}, // AWS Graviton 2 ([m|c|r]6g) Neoverse-N1 UarchGraviton3: {MicroArchitecture: UarchGraviton3, MemoryChannelCount: 8, LogicalThreadCount: 1}, // AWS Graviton 3 ([m|c|r]7g) Neoverse-V1 UarchGraviton4: {MicroArchitecture: UarchGraviton4, MemoryChannelCount: 12, LogicalThreadCount: 1}, // AWS Graviton 4 ([m|c|r]8g) Neoverse-V2 + UarchGraviton5: {MicroArchitecture: UarchGraviton5, MemoryChannelCount: 16, LogicalThreadCount: 1}, // AWS Graviton 5 ([m|c|r]8g) Neoverse-V3 UarchAxion: {MicroArchitecture: UarchAxion, MemoryChannelCount: 12, LogicalThreadCount: 1}, // GCP Axion (c4a) Neoverse-V2 UarchAltraFamily: {MicroArchitecture: UarchAltraFamily, MemoryChannelCount: 8, LogicalThreadCount: 1}, // Ampere Altra UarchAmpereOneAC03: {MicroArchitecture: UarchAmpereOneAC03, MemoryChannelCount: 8, LogicalThreadCount: 1}, // AmpereOne AC03 @@ -209,6 +211,7 @@ var cpuIdentifiersARM = []struct { {CPUIdentifierARM{Implementer: "0x41", Part: "0xd0c", DmidecodePart: "AWS Graviton2"}, UarchGraviton2}, // AWS Graviton 2 ([m|c|r]6g) Neoverse-N1 {CPUIdentifierARM{Implementer: "0x41", Part: "0xd40", DmidecodePart: "AWS Graviton3"}, UarchGraviton3}, // AWS Graviton 3 ([m|c|r]7g) Neoverse-V1 {CPUIdentifierARM{Implementer: "0x41", Part: "0xd4f", DmidecodePart: "AWS Graviton4"}, UarchGraviton4}, // AWS Graviton 4 ([m|c|r]8g) Neoverse-V2 + {CPUIdentifierARM{Implementer: "0x41", Part: "0xd84", DmidecodePart: "AWS Graviton5"}, UarchGraviton5}, // AWS Graviton 5 ([m|c|r]8g) Neoverse-V3 {CPUIdentifierARM{Implementer: "0x41", Part: "0xd4f", DmidecodePart: "Not Specified"}, UarchAxion}, // GCP Axion (c4a) Neoverse-V2 {CPUIdentifierARM{Implementer: "0x41", Part: "0xd0c", DmidecodePart: "Not Specified"}, UarchAltraFamily}, // Ampere Altra {CPUIdentifierARM{Implementer: "0xc0", Part: "0xac3", DmidecodePart: ""}, UarchAmpereOneAC03}, // AmpereOne AC03