Missing PCH PCIe power and clock gating options in ADL-N IOT FSP

[miczyg1]

Certain board designs do not route all CLKREQ signals to PCIe ports and even hardwire them to be pulled up to Vcc (meaning CLKREQ permanently inactive). For such designs, it is required to unset PchPcieClockGating and PchPciePowerGating to avoid the issue described in this patch: https://review.coreboot.org/c/coreboot/+/76687

Currently ADL-N IOT FSP MR5 is missing these options and getting a properly working firmware solution is not possible without having own sources of FSP to modify it.

Could Intel please add those options to the ADL-N FSP?

[miczyg1]

I can see those were added in MR6: 0a9eafc

Thank you so much. Will test ASAP and close the issue if it works.