diff --git a/mkapp/hal/goggle2/HDZGOGGLE_VA.bin b/mkapp/hal/goggle2/HDZGOGGLE_VA.bin
index d258aa55f..09ad4d678 100644
Binary files a/mkapp/hal/goggle2/HDZGOGGLE_VA.bin and b/mkapp/hal/goggle2/HDZGOGGLE_VA.bin differ
diff --git a/mkapp/hal/goggle2/version b/mkapp/hal/goggle2/version
index 1e0e8846e..c47226d3b 100644
--- a/mkapp/hal/goggle2/version
+++ b/mkapp/hal/goggle2/version
@@ -1 +1 @@
-77-191
+77-198
diff --git a/src/core/app_state.c b/src/core/app_state.c
index 0ae60443f..063a1acba 100644
--- a/src/core/app_state.c
+++ b/src/core/app_state.c
@@ -112,11 +112,7 @@ void app_switch_to_hdmi_in() {
     Set_Contrast(g_setting.image.contrast);
 #endif
 
-#if defined HDZGOGGLE2
-    system_exec("aww 0x0300b084 0x0001555");
-#endif
-
-  rtc6715.init(0, 0);
+    rtc6715.init(0, 0);
 
     Source_HDMI_in();
     IT66121_close();
@@ -158,10 +154,6 @@ void app_switch_to_hdzero(bool is_default) {
     Set_Contrast(g_setting.image.contrast);
 #endif
 
-#if defined HDZGOGGLE2
-    system_exec("aww 0x0300b084 0x0001555");
-#endif
-
     rtc6715.init(0, 0);
 
     if (is_default) {
diff --git a/src/core/main.c b/src/core/main.c
index c042ff4be..01b4ae304 100644
--- a/src/core/main.c
+++ b/src/core/main.c
@@ -160,6 +160,9 @@ int main(int argc, char *argv[]) {
     settings_init();
     settings_load();
     language_init();
+#ifdef HDZGOGGLE2
+    vclk_phase_init();
+#endif
     pclk_phase_init();
 
     // 2. Initialize communications.
diff --git a/src/core/self_test.c b/src/core/self_test.c
index f8a3e90de..94381200b 100644
--- a/src/core/self_test.c
+++ b/src/core/self_test.c
@@ -29,8 +29,6 @@ void self_test() {
 #ifdef HDZGOGGLE2
     system_exec("dispw -s vdpo 1080p50");
     system_exec("aww 0x0300b340 0x00000008");
-    system_exec("aww 0x0300b084 0x00002aaa"); // Set vdpo clock driver strength to level 2. Refer datasheet 12.7.5.11
-
 #endif
 
     if (!g_setting.storage.selftest)
diff --git a/src/driver/hardware-goggle2.c b/src/driver/hardware-goggle2.c
index 9a80ed116..1dda8993c 100755
--- a/src/driver/hardware-goggle2.c
+++ b/src/driver/hardware-goggle2.c
@@ -40,14 +40,14 @@ pthread_mutex_t hardware_mutex;
 
 uint32_t vclk_phase_default[VIDEO_SOURCE_NUM] = {
     // 0x??,  0x8e,  0x??, 0x??
-    0x0000000c, // VIDEO_SOURCE_VERSION
+    0x0000000e, // VIDEO_SOURCE_VERSION
     0x00200000, // VIDEO_SOURCE_MENU_UI
     0x00010000, // VIDEO_SOURCE_HDZERO_IN_720P60_50
     0x00200000, // VIDEO_SOURCE_HDZERO_IN_720P90
     0x00000000, // VIDEO_SOURCE_HDZERO_IN_1080P30
     0x00010000, // VIDEO_SOURCE_AV_IN
-    0x00200000, // VIDEO_SOURCE_HDMI_IN_1080P50
-    0x00200000, // VIDEO_SOURCE_HDMI_IN_1080P60
+    0x00000000, // VIDEO_SOURCE_HDMI_IN_1080P50
+    0x00000000, // VIDEO_SOURCE_HDMI_IN_1080P60
     0x00000000, // VIDEO_SOURCE_HDMI_IN_1080POTHER
     0x00000000, // VIDEO_SOURCE_HDMI_IN_720P50
     0x00000000, // VIDEO_SOURCE_HDMI_IN_720P60
@@ -64,7 +64,7 @@ bit[5:4] hdmi out
 bit[6]   oled
 */
 uint32_t pclk_phase_default[VIDEO_SOURCE_NUM] = {
-    0x00000003,
+    0x00000004,
     0x00000000, // VIDEO_SOURCE_MENU_UI
     0x00000000, // VIDEO_SOURCE_HDZERO_IN_720P60_50
     0x00000000, // VIDEO_SOURCE_HDZERO_IN_720P90
@@ -75,7 +75,7 @@ uint32_t pclk_phase_default[VIDEO_SOURCE_NUM] = {
     0x00000001, // VIDEO_SOURCE_HDMI_IN_1080POTHER
     0x00000000, // VIDEO_SOURCE_HDMI_IN_720P50
     0x00000000, // VIDEO_SOURCE_HDMI_IN_720P60
-    0x00000000, // VIDEO_SOURCE_HDMI_IN_720P100
+    0x00000001, // VIDEO_SOURCE_HDMI_IN_720P100
     0x00000000, // VIDEO_SOURCE_TP2825_EX, DO NOT USE
 };
 
@@ -483,11 +483,13 @@ void pclk_phase_set(video_source_t source) {
     LOGI("video_source:%d", source);
     LOGI("pclk_phase_set %d", pclk_phase[source]);
     // bit[0] hdmi in
-    if (source == VIDEO_SOURCE_HDMI_IN_1080P50 || source == VIDEO_SOURCE_HDMI_IN_1080P60 || source == VIDEO_SOURCE_HDMI_IN_1080POTHER) {
-        IT66021_Set_Pclk((pclk_phase[source] >> 0) & 1, 0);
-    } else {
-        IT66021_Set_Pclk((pclk_phase[source] >> 0) & 1, 0);
-    }
+    // IT66021_Set_Pclk((pclk_phase[source] >> 0) & 1, 0);
+    IT66021_Mask_WR(0, 0x0f, 0x03, 0x00);
+    if ((pclk_phase[source] >> 0) & 1)
+        I2C_L_Write(ADDR_IT66021, 0x50, 0xb3);
+    else
+        I2C_L_Write(ADDR_IT66021, 0x50, 0xa1);
+
     // bit[1] analog in
     TP2825_Set_Pclk((pclk_phase[source] >> 1) & 1);
 
@@ -655,7 +657,7 @@ void Display_1080P24_t(int mode) {
     vclk_phase_set(VIDEO_SOURCE_HDZERO_IN_1080P30, 0);
     pclk_phase_set(VIDEO_SOURCE_HDZERO_IN_1080P30);
 
-    I2C_Write(ADDR_FPGA, 0x80, 0x84);
+    I2C_Write(ADDR_FPGA, 0x80, 0x04);
     // I2C_Write(ADDR_FPGA, 0x84, 0x00); // close OSD
 
     DM5680_SetFPS(mode);
diff --git a/src/driver/hardware.h b/src/driver/hardware.h
index b232a713c..40c9e234b 100644
--- a/src/driver/hardware.h
+++ b/src/driver/hardware.h
@@ -114,6 +114,7 @@ int HDMI_in_detect();
 int Get_VideoLatancy_status(); // ret: 0=unlocked, 1=locked
 int Get_HAN_status();          // ret: 0=error; 1=ok
 
+void vclk_phase_init();
 void pclk_phase_init();
 
 extern uint32_t vclk_phase[VIDEO_SOURCE_NUM];
diff --git a/src/driver/it66021.h b/src/driver/it66021.h
index 98ce4797f..97d51afcc 100644
--- a/src/driver/it66021.h
+++ b/src/driver/it66021.h
@@ -3,6 +3,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
+#include <stdint.h>
 
 void IT66021_srst();
 void IT66021_close();
@@ -15,6 +16,7 @@ int IT66021_Get_PCLKFREQ();
 void IT66021_edid();
 
 void IT66021_Set_Pclk(int inv, int dly);
+void IT66021_Mask_WR(uint8_t is_ring, uint8_t addr, uint8_t mask, uint8_t wdat);
 
 #ifdef __cplusplus
 }