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Copy pathgpu.config
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65 lines (65 loc) · 1.51 KB
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block_sim_mode:0
sm_num:68
mem_num:44
gpm_num:1
num_warp_schedulers_per_SM:4
num_inst_dispatch_units_per_warp:1
shared_mem_size:65536
l1_hit_latency:32
tlb_hit_l2_hit_latency:220
tlb_miss_l2_write_hit_latency:1000
tlb_miss_l2_miss_latency:1000
tlb_hit_l2_miss_latency:427
kernel_launch_cycles:300
block_launch_cycles:80
##pipeline_units
INT_units:64
SP_units:64
DP_units:2
SFU_units:16
TC_units:8
LDS_units:16
BRA_units:4
TEX_units:4
##compute_capability
warp_size:32
max_block_size:1024
smem_allocation_size:256
max_registers_per_SM:65536
max_registers_per_block:65536
max_registers_per_thread:255
register_allocation_size:256
max_active_blocks_per_SM:32
max_active_threads_per_SM:1024
##l1_cache_config
l1_cache_n_banks:4
l1_cache_n_sets:1
l1_cache_line_size:128
l1_cache_m_assoc:256
l1_cache_m_replacement_policy:LRU
l1_cache_m_write_policy:LOCAL_WB_GLOBAL_WT
l1_cache_m_alloc_policy:STREAMING
l1_cache_m_write_alloc_policy:NO_WRITE_ALLOCATE
l1_cache_m_set_index_function:LINEAR_SET_FUNCTION
l1_cache_mshr_type:ASSOC
l1_m_mshr_entries:256
l1_m_mshr_max_merge:8
##l2_cache_config
l2_cache_sub_partitions:44
l2_cache_n_sets:64
l2_cache_line_size:128
l2_cache_m_assoc:16
l2_cache_m_replacement_policy:LRU
l2_cache_m_write_policy:WRITE_BACK
l2_cache_m_alloc_policy:ON_MISS
l2_cache_m_write_alloc_policy:LAZY_FETCH_ON_READ
l2_cache_m_set_index_function:HASH_IPOLY_FUNCTION
l2_cache_mshr_type:ASSOC
l2_m_mshr_entries:192
l2_m_mshr_max_merge:4
##crossbar_config
crossbar_bank:16
crossbar_latency:6
crossbar_buffer_size:64
crossbar_subnets:2
####