+Shortcut
+
+
- | IC Vendors | Intel, Qualcomm, Nvidia, Samsung, AMD,IBM, Marvell |
+ IC Vendors |
+ NVIDIA, Intel, Gaudi, AMD, Qualcomm, Samsung, MediaTek, Marvell, Broadcom |
- | Tech Giants & HPC Vendors | Google, Amazon_AWS, Microsoft, Apple, Alibaba Group, Tencent Cloud, Baidu, Fujitsu, Nokia, Facebook, Tesla |
+ Tech Giants & HPC |
+ Google, AWS, Microsoft, Apple, OpenAI, Anthropic, Alibaba, Baidu, Tencent, Meta, Tesla |
- | IP Vendors | ARM, Synopsys, Imagination, CEVA, Cadence, VeriSilicon |
+ IP Vendors |
+ Arm, Synopsys, Imagination, CEVA, Cadence, VeriSilicon |
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- | Startups |
- Cerebras, Graphcore, Tenstorrent, Blaize, Koniku, Adapteva, Mythic, BrainChip, Leepmind, Groq, Kneron, Esperanto Technologies, Gyrfalcon Technology, SambaNova Systems, GreenWaves Technology, Lightelligence, Lightmatter, Hailo,Tachyum,AlphaICs,Syntiant, aiCTX, Flex Logix, Preferred Network, Cornami, Anaflash, Optaylsys, Eta Compute, Achronix, Areanna AI, Neuroblade, Luminous Computing, Efinix, AISTORM, SiMa.ai,Untether AI, GrAI Matter Lab, Rain Neuromorphics, Applied Brain Research, XMOS, DinoPlusAI, Furiosa AI, Perceive, SimpleMachines, Neureality, Analog Inference, Quadric, EdgeQ, Innatera Nanosystems, Ceremorphic, Aspinity, TeraMem, d-Matrix |
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+ | Startups |
+ Cerebras, Graphcore, Tenstorrent, Etched, Groq, SambaNova, Mythic, Hailo, FuriosaAI, Kinara, SiMa, d-Matrix, Blaize, … |
+
+
+ | China AI Accelerators |
+ Huawei Ascend, Cambricon, Biren, Moore Threads, MetaX, Hygon, Iluvatar, Enflame, Horizon, Black Sesame |
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-GPU
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-NVIDIA Teams With Microsoft to Build Massive Cloud AI Computer
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- Tens of Thousands of NVIDIA GPUs, NVIDIA Quantum-2 InfiniBand and Full Stack of NVIDIA AI Software Coming to Azure; NVIDIA, Microsoft and Global Enterprises to Use Platform for Rapid, Cost-Effective AI Development and Deployment
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-NVIDIA Hopper Architecture In-Depth
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- Today during the 2022 NVIDIA GTC Keynote address, NVIDIA CEO Jensen Huang introduced the new NVIDIA H100 Tensor Core GPU based on the new NVIDIA Hopper GPU architecture. This post gives you a look inside the new H100 GPU and describes important new features of NVIDIA Hopper architecture GPUs.
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-NVIDIA Unveils Grace: A High-Performance Arm Server CPU For Use In Big AI Systems
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- Kicking off another busy Spring GPU Technology Conference for NVIDIA, this morning the graphics and accelerator designer is announcing that they are going to once again design their own Arm-based CPU/SoC. Dubbed Grace – after Grace Hopper, the computer programming pioneer and US Navy rear admiral – the CPU is NVIDIA’s latest stab at more fully vertically integrating their hardware stack by being able to offer a high-performance CPU alongside their regular GPU wares. According to NVIDIA, the chip is being designed specifically for large-scale neural network workloads, and is expected to become available in NVIDIA products in 2023.
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-Mobileye EyeQ
-> Mobileye is currently developing its fifth generation SoC, the EyeQ®5, to act as the vision central computer performing sensor fusion for Fully Autonomous Driving (Level 5) vehicles that will hit the road in 2020. To meet power consumption and performance targets, EyeQ® SoCs are designed in most advanced VLSI process technology nodes – down to 7nm FinFET in the 5th generation.
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-Loihi
-Intel Advances Neuromorphic with Loihi 2, New Lava Software Framework and New Partners
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- Second-generation research chip uses pre-production Intel 4 process, grows to 1 million neurons. Intel adds open software framework to accelerate developer innovation and path to commercialization.
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-Habana
-Intel’s Habana Labs Launches Second-Generation AI Processors for Training and Inferencing
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- Today at Intel Vision, Intel announced that Habana Labs, its data center team focused on AI deep learning processor technologies, launched its second-generation deep learning processors for training and inference: Habana® Gaudi®2 and Habana® Greco™. These new processors address an industry gap by providing customers with high-performance, high-efficiency deep learning compute choices for both training workloads and inference deployments in the data center while lowering the AI barrier to entry for companies of all sizes.
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-Habana Gaudi debuts in the Amazon EC2 cloud
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- The primary motivation to create this new training instance class was presented by Andy Jassy in the 2020 re:Invent: “To provide our end-customers with up to 40% better price-performance than the current generation of GPU-based instances.”
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+NVIDIA — GPU / AI accelerator lineage
+NVIDIA turned GPUs into the default AI training/inference substrate via CUDA (2007) and successive datacenter architectures. From Pascal/Volta Tensor Cores through Ampere and Hopper, the stack evolved into rack-scale Grace+Blackwell systems; Rubin extends that AI-factory model into 2026.
-Qualcomm Ups The Snapgragon AI Game
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- The leader in premium mobile SoCs has applied AI across the entire platform.
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+CUDA foundation (pre–Tensor Core)
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+- Tesla arch (2006) + CUDA (2007) — unified shaders / GPGPU; GPU becomes a general accelerator.
+- Fermi (2010) — caches, ECC, stronger HPC path.
+- Kepler (2012) — Hyper-Q / dynamic parallelism; datacenter Tesla K-series.
+- Maxwell (2014) — major perf/W redesign.
+- Pascal (2016) — P100 — HBM2 + NVLink 1.0; first widely adopted datacenter GPU for deep learning at scale.
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-Qualcomm Cloud AI 100
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- The Qualcomm Cloud AI 100, designed for AI inference acceleration, addresses unique requirements in the cloud, including power efficiency, scale, process node advancements, and signal processing—facilitating the ability of datacenters to run inference on the edge cloud faster and more efficiently. Qualcomm Cloud AI 100 is designed to be a leading solution for datacenters who increasingly rely on infrastructure at the edge-cloud.
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+Tensor Core era
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+- Volta (2017) — V100 — first Tensor Cores (FP16 mixed precision); DGX / early large-model workhorse.
+- Turing (2018) — T4 — inference-efficient datacenter SKUs; consumer RTX adds RT + Tensor Cores.
+- Ampere (2020) — A100 — TF32 / BF16, structured sparsity, MIG; A100 40/80GB HBM2e.
+- Ada Lovelace (2022) — L40 / L4 — inference / visual datacenter SKUs alongside Hopper.
+- Hopper (2022) — H100 / H200 — Transformer Engine, FP8, NVLink 4; H200 expands HBM3e for LLM train/serve.
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-Samsung Brings On-device AI Processing for Premium Mobile Devices with Exynos 9 Series 9820 Processor
-> Fourth-generation custom core and 2.0Gbps LTE Advanced Pro modem enables enriched mobile experiences including AR and VR applications
+Platform / rack-scale era (2024–2026)
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+- Blackwell (2024) — B200 / GB200 NVL72 — multi-die GPU, FP4/FP6 datapaths, NVLink 5; Grace+Blackwell superchips and NVL72 racks.
+- Rubin (CES/GTC 2026) — Vera CPU + Rubin GPU + NVLink 6 Switch + ConnectX-9 / BlueField-4 / Spectrum-6 for agentic / MoE; partner availability targeted H2 2026. NVIDIA also described integrating Groq-class LPU technology into the AI-factory stack.
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+Latest
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+- Vera Rubin opens agentic AI frontier — GTC Mar 2026 — seven chips in full production (Vera CPU, Rubin GPU, NVLink 6, ConnectX-9, BlueField-4, Spectrum-6, Groq LPU); NVL72 on track for H2 2026 partner systems.
+- Vera Rubin POD / rack-scale systems — Mar 2026 — POD-scale co-design across five rack systems; CEO later reiterated “giant amounts” of Vera Rubin production incoming for H2 2026.
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+Hopper in-depth · Hopper · Blackwell
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-Samsung resently unveiled “The new Exynos 9810 brings premium features with a 2.9GHz custom CPU, an industry-first 6CA LTE modem and deep learning processing capabilities”.
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+Intel / Habana Gaudi
+Intel’s AI accelerator path consolidated around Habana Labs after the 2019 acquisition. Gaudi (training) and Goya (inference) established Ethernet-centric scale-out as an alternative to proprietary GPU fabrics; Gaudi 2 broadened LLM training, and Gaudi 3 (2024) targets enterprise generative AI with OEM and cloud availability. Intel also folds AI into Xeon AMX and Arc/Flex GPUs, but Gaudi remains the dedicated datacenter accelerator brand.
+Latest
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+- Gaudi 3 on IBM Cloud — Intel Vision 2025 — IBM Cloud is the first CSP with Gaudi 3 in production (Frankfurt, Washington D.C., Dallas) for enterprise GenAI price/performance.
+- Dell AI Factory with Gaudi 3 — 2025 — Dell AI platform / AI Factory ships validated Gaudi 3 systems for scalable enterprise GenAI with open Ethernet networking.
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-The soon to be released AMD Instinct™ MI Series Accelerators
-> AMD Instinct™ accelerators are engineered from the ground up for this new era of data center computing, supercharging HPC and AI workloads to propel new discoveries. The AMD Instinct™ family of accelerators can deliver industry leading performance for the data center at any scale from single server solutions up to the world’s largest supercomputers.1 With new innovations in AMD CDNA™ 2 architecture, AMD Infinity Fabric™ technology and packaging technology, the latest AMD Instinct™ accelerators are designed to power discoveries at exascale, enabling scientists to tackle our most pressing challenges.
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-Meet the IBM Artificial Intelligence Unit
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- It’s our first complete system-on-chip designed to run and train deep learning models faster and more efficiently than a general-purpose CPU.
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-IBM Telum Processor: the next-gen microprocessor for IBM Z and IBM LinuxONE
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- The 7 nm microprocessor is engineered to meet the demands our clients face for gaining AI-based insights from their data without compromising response time for high volume transactional workloads.
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-TrueNorth is IBM's Neuromorphic CMOS ASIC developed in conjunction with the DARPA SyNAPSE program.
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- It is a manycore processor network on a chip design, with 4096 cores, each one simulating 256 programmable silicon "neurons" for a total of just over a million neurons. In turn, each neuron has 256 programmable "synapses" that convey the signals between them. Hence, the total number of programmable synapses is just over 268 million (228). In terms of basic building blocks, its transistor count is 5.4 billion. Since memory, computation, and communication are handled in each of the 4096 neurosynaptic cores, TrueNorth circumvents the von-Neumann-architecture bottlenecks and is very energy-efficient, consuming 70 milliwatts, about 1/10,000th the power density of conventional microprocessors. Wikipedia
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-AI Hardware Center
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- "The IBM Research AI Hardware Center is a global research hub headquartered in Albany, New York. The center is focused on enabling next-generation chips and systems that support the tremendous processing power and unprecedented speed that AI requires to realize its full potential.
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-Data Processing Units
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- Built on seven generations of the industry’s first, most scalable and widely adopted data infrastructure processors, Marvell’s OCTEON™, OCTEON™ Fusion and ARMADA® platforms are optimized for wireless infrastructure, wireline carrier networks, enterprise and cloud data centers.
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-II. Tech Giants & HPC Vendors
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-Google Tensor: Everything you need to know about the Pixel 6 chip
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- Google has taken the wraps off its latest Pixel smartphones and, among the changes, the one with the biggest long-term impact is the switch to in-house silicon for the search giant.
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-Google Launches TPU v4 AI Chips
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- Google CEO Sundar Pichai spoke for only one minute and 42 seconds about the company’s latest TPU v4 Tensor Processing Units during his keynote at the Google I/O virtual conference this week, but it may have been the most important and awaited news from the event.
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-Cloud TPU
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- Machine learning has produced business and research breakthroughs ranging from network security to medical diagnoses. We built the Tensor Processing Unit (TPU) in order to make it possible for anyone to achieve similar breakthroughs. Cloud TPU is the custom-designed machine learning ASIC that powers Google products like Translate, Photos, Search, Assistant, and Gmail. Here’s how you can put the TPU and machine learning to work accelerating your company’s success, especially at scale.
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-Edge TPU
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- AI is pervasive today, from consumer to enterprise applications. With the explosive growth of connected devices, combined with a demand for privacy/confidentiality, low latency, and bandwidth constraints, AI models trained in the cloud increasingly need to be run at the edge. Edge TPU is Google’s purpose-built ASIC designed to run AI at the edge. It delivers high performance in a small physical and power footprint, enabling the deployment of high-accuracy AI at the edge.
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-Other references are:
-Google TPU3 看点
-Google TPU 揭密
-Google的神经网络处理器专利
-脉动阵列 - 因Google TPU获得新生
-Should We All Embrace Systolic Arrays?
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-AWS Trainium
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- AWS Trainium is the second custom machine learning (ML) chip designed by AWS that provides the best price performance for training deep learning models in the cloud. Trainium offers the highest performance with the most teraflops (TFLOPS) of compute power for the fastest ML training in Amazon EC2 and enables a broader set of ML applications. The Trainium chip is specifically optimized for deep learning training workloads for applications including image classification, semantic search, translation, voice recognition, natural language processing and recommendation engines.
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-AWS Inferentia. High performance machine learning inference chip, custom designed by AWS.
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- AWS Inferentia provides high throughput, low latency inference performance at an extremely low cost. Each chip provides hundreds of TOPS (tera operations per second) of inference throughput to allow complex models to make fast predictions. For even more performance, multiple AWS Inferentia chips can be used together to drive thousands of TOPS of throughput. AWS Inferentia will be available for use with Amazon SageMaker, Amazon EC2, and Amazon Elastic Inference.
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-Alibaba’s New AI Chip Can Process Nearly 80K Images Per Second
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- At the Alibaba Cloud (Aliyun) Apsara Conference 2019, Pingtouge unveiled its first AI dedicated processor for cloud-based large-scale AI inferencing. The Hanguang 800 is the first semiconductor product in Alibaba’s 20-year history.
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-Tencent reveals three data center chips - for AI, video transcoding, and networking
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- The company claims that the Zixiao AI chip is twice as good as comparable competing products, video transcoding chip Canghai was 30 percent better, and SmartNIC Xuanling was apparently four times as good. It did not provide external benchmarks or specific product details.
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-Baidu says 2nd-gen Kunlun AI chips enter mass production
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- Chinese tech giant Baidu said on Wednesday it had begun mass-producing second-generation Kunlun artificial intelligence (AI) chips, as it races to become a key player in the chip industry which Beijing is trying to strengthen.
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- This DLU that Fujitsu is creating is done from scratch, and it is not based on either the Sparc or ARM instruction set and, in fact, it has its own instruction set and a new data format specifically for deep learning, which were created from scratch.
- Japanese computing giant Fujitsu. Which knows a thing or two about making a very efficient and highly scalable system for HPC workloads, as evidenced by the K supercomputer, does not believe that the HPC and AI architectures will converge. Rather, the company is banking on the fact that these architectures will diverge and will require very specialized functions.
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- Nokia has developed the ReefShark chipsets for its 5G network solutions. AI is implemented in the ReefShark design for radio and embedded in the baseband to use augmented deep learning to trigger smart, rapid actions by the autonomous, cognitive network, enhancing network optimization and increasing business opportunities.
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-Facebook developing machine learning chip - The Information
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- Facebook Inc (FB.O) is developing a machine learning chip to handle tasks such as content recommendation to users, The Information reported on Thursday, citing two people familiar with the project.
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-Tesla’s Biggest News At AI Day Was The Dojo Supercomputer, Not The Optimus Robot
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- Elon Musk played AI Day to the crowd with the focus on the Optimus humanoid robot. But while this could have a huge impact on our lives and society if it does enter mass production at the price Musk suggested ($20,000), another part of the presentation will have more immediate effects. That was the status report on the Dojo supercomputer. It could really change the world much more quickly than a bipedal bot.
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-Tesla Dojo – Unique Packaging and Chip Design Allow An Order Magnitude Advantage Over Competing AI Hardware
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- Tesla hosted their AI Day and revealed the innerworkings of their software and hardware infrastructure. Part of this reveal was the previously teased Dojo AI training chip. Tesla claims their D1 Dojo chip has a GPU level compute, CPU level flexibility, with networking switch IO.
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-III. Traditional IP Vendors
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-NPU ETHOS-N78
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- Specifically designed for inference at the edge, the ML processor gives an industry-leading performance of 4.6 TOPs, with a stunning efficiency of 3 TOPs/W for mobile devices and smart IP cameras.
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-ARM Details "Project Trillium" Machine Learning Processor Architecture
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- Arm’s second-generation, highly scalable and efficient NPU, the Ethos-N78 enables new immersive applications with a 2.5x increase in single-core performance now scalable from 1 to 10 TOP/s and beyond through many-core technologies. It provides flexibility to optimize the ML capability with 90+ configurations.
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-Synopsys Introduces Industry's Highest Performance Neural Processor IP
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- New DesignWare ARC NPX6 NPU IP Delivers Up to 3,500 TOPS Performance for Automotive, Consumer and Data Center Chip Designs
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-AI Processors
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- Whether you want smartness residing in the palm of your hand, consumer products or industrial robots, or enabled by powerful servers in the cloud, we can help you achieve your vision. We enable the smartness in your products with our PowerVR Neural Network Accelerators (NNA) and GPUs. Our NC-SDK enables seamless deployment of AI acceleration on either our hardware IP either in isolation or combined. Our NNA provides maximum efficiency with a scalable architecture which enables a wide range of smart edge and end point devices from low performance IoT to high performance RoboTaxi.
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-Deep learning for the real-time embedded world
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- One solution lies in supplying a dedicated low power AI processor for Deep Learning at the edge, combined with a deep neural network (DNN) graph compiler
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-Tensilica AI Platform
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-Vivante® NPU IP
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- VeriSilicon's Neural Network Processor (NPU) IP is a highly scalable, programmable computer vision and artificial intelligence processor that supports AI operations upgrades for endpoints, edge devices, and cloud devices. Designed to meet a variety of chip sizes and power budgets, the Vivante NPU IP is a cost-effective, high-quality neural network acceleration engine solution.
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-Cerebras Unveils Andromeda, a 13.5 Million Core AI Supercomputer that Delivers Near-Perfect Linear Scaling for Large Language Models
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- Delivering more than 1 Exaflop of AI compute and 120 Petaflops of dense compute, Andromeda is one of the largest AI supercomputers ever built, and is dead simple to use
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-Cerebras Sets Record for Largest AI Models Ever Trained on Single Device
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- We are announcing the largest models ever trained on a single device. Using the Cerebras Software Platform (CSoft), our customers can easily train state-of-the-art GPT language models (such as GPT-3[i] and GPT-J[ii]) with up to 20 billion parameters on a single CS-2 system. Running on a single CS-2, these models take minutes to set up and users can quickly move between models with just a few keystrokes. With clusters of GPUs, this takes months of engineering work.
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-Cerebras Completes Series F Funding, Another $250M for $4B Valuation
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- The new Series F funding round nets the company another $250m in capital, bringing the total raised through venture capital up to $720 million.
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-Cerebras Unveils Wafer Scale Engine Two (WSE2): 2.6 Trillion Transistors, 100% Yield
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- Two years ago Cerebras unveiled a revolution in silicon design: a processor as big as your head, using as much area on a 12-inch wafer as a rectangular design would allow, built on 16nm, focused on both AI as well as HPC workloads. Today the company is launching its second generation product, built on TSMC 7nm, with more than double the cores and more than double of everything.
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-The Cerebras CS-1 computes deep learning AI problems by being bigger, bigger, and bigger than any other chip
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- Today, the company announced the launch of its end-user compute product, the Cerebras CS-1, and also announced its first customer of Argonne National Laboratory.
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-Graphcore Supercharges IPU with Wafer-on-Wafer
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- Graphcore unveiled its third-generation intelligence processing unit (IPU), the first processor to be built using 3D wafer-on-wafer (WoW) technology.
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-MK2 PERFORMANCE BENCHMARKS
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-Graphcore, the AI chipmaker, raises another $150M at a $1.95B valuation
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- Graphcore, the Bristol-based startup that designs processors specifically for artificial intelligence applications, announced it has raised another $150 million in funding for R&D and to continue bringing on new customers. It’s valuation is now $1.95 billion.
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-解密又一个xPU：Graphcore的IPU give some analysis on its IPU architecture.
-Graphcore AI芯片：更多分析 More analysis.
-深度剖析AI芯片初创公司Graphcore的IPU In-depth analysis after more information was disclosed.
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-Tenstorrent Raises over $200 million at $1 billion Valuation to Create Programmable, High Performance AI Computers
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- TORONTO, May 20, 2021 /PRNewswire/ - Tenstorrent, a hardware start-up developing next generation computers, announced today that it has raised over $200 million in a recent funding round that values the company at $1 billion. The round was led by Fidelity Management and Research Company and includes additional investments from Eclipse Ventures, Epic CG and Moore Capital.
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-An Interview with Tenstorrent: CEO Ljubisa Bajic and CTO Jim Keller
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-Automotive AI Startup Blaize Closes $71 Million Funding Round
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- Blaize, formerly ThinCI, has closed a Series D round of funding at $71 million. New investor Franklin Templeton and existing investor Temasek led the round, along with participation from Denso and other new and existing investors. This round brings Blaize’s total funding to around $155 million total.
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- Founded in 2014, Newark, California startup Koniku has taken in $1.65 million in funding so far to become “the world’s first neurocomputation company“. The idea is that since the brain is the most powerful computer ever devised, why not reverse engineer it? Simple, right? Koniku is actually integrating biological neurons onto chips and has made enough progress that they claim to have AstraZeneca as a customer. Boeing has also signed on with a letter of intent to use the technology in chemical-detecting drones.
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-Adapteva has taken in $5.1 million in funding from investors that include mobile giant Ericsson. The paper "Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip" describes the design of Adapteva's 1024-core processor chip in 16nm FinFet technology.
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-The Era of Analog Compute has Arrived!
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- ResNet-50 in our prototype analog AI processor. Production release will support 900-1000 fps and INT8 accuracy at 3W.
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-Mythic launches analog AI processor that consumes 10 times less power
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- Analog AI processor company Mythic launched its M1076 Analog Matrix Processor today to provide low-power AI processing.
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-BrainChip launches neuromorphic process for AI at the edge
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- BrainChip today announced the commercialization of its Akida neural networking processor. Aimed at a variety of edge and internet of things (IoT) applications, BrainChip claims to be the first commercial producer of neuromorphic AI chips, which could deliver benefits in ultra-low power and performance over conventional approaches.
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-AI Processor Chipmaker Deep Vision Raises $35 Million in Series B Funding
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- Tiger Global Leads Series B Financing, Enabling Deep Vision to Expand Video Analytics and Natural Language Processing Capabilities in Edge Computing Applications
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-Groq Demonstrates Fast LLMs on 4-Year-Old Silicon
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- MOUNTAIN VIEW, CALIF. — Groq has repositioned its first-generation AI inference chip as a language processing unit (LPU), and demonstrated Meta’s Llama-2 70-billion–parameter large language model (LLM) running inference at 240 tokens per second per user. Groq CEO Jonathan Ross told EE Times that the company had Llama-2 up and running on the company’s 10-rack (64-chip) cloud-based dev system in “a couple of days.” This system is based on the company’s first gen AI silicon, released four years ago.
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-AI Chip Startup Groq, Founded By Ex-Googlers, Raises $300 Million To Power Autonomous Vehicles And Data Centers
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- Jonathan Ross left Google to launch next-generation semiconductor startup Groq in 2016. Today, the Mountain View, California-based firm said that it had raised $300 million led by Tiger Global Management and billionaire investor Dan Sundheim’s D1 Capital as it officially launched into public view.
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-Kneron to Accelerate Edge AI Development with more than 10 Million USD Series A Financing
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-According to this article, "Gyrfalcon offers Automotive AI Chip Technology"
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- Gyrfalcon Technology Inc. (GTI), has been promoting matrix-based application specific chips for all forms of AI since offering their production versions of AI accelerator chips in September 2017. Through the licensing of its proprietary technology, the company is confident it can help automakers bring highly competitive AI chips to production for use in vehicles within 18 months, along with significant gains in AI performance, improvements in power dissipation and cost advantages.
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-SambaNova unveils new AI chip to power full-stack AI platform
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- Today Palo-Alto-based SambaNova Systems unveiled a new AI chip, the SN40L, which will power its full-stack large language model (LLM) platform, the SambaNova Suite, that helps enterprises go from chip to model — building and deploying customized generative AI models.
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-SambaNova raises $676M at a $5.1B valuation to double down on cloud-based AI software for enterprises
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- SambaNova — a startup building AI hardware and integrated systems that run on it that only officially came out of three years in stealth last December — is announcing a huge round of funding today to take its business out into the world. The company has closed on $676 million in financing, a Series D that co-founder and CEO Rodrigo Liang has confirmed values the company at $5.1 billion.
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-Introducing SambaNova Systems DataScale: A New Era of Computing
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- SambaNova has been working closely with many organizations the past few months and has established a new state of the art in NLP. This advancement in NLP deep learning is illustrated by a GPU-crushing, world record performance result achieved on SambaNova Systems’ Dataflow-optimized system.
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-A New State of the Art in NLP: Beyond GPUs
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- SambaNova has been working closely with many organizations the past few months and has established a new state of the art in NLP. This advancement in NLP deep learning is illustrated by a GPU-crushing, world record performance result achieved on SambaNova Systems’ Dataflow-optimized system.
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-GreenWaves Shows Off Advanced Audio Demos
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- The Gap9 processor, a successor to Gap8 which targets computer vision in IoT devices, is an ultra-low power neural network processor suitable for battery-powered devices. GreenWaves’ vice president of marketing Martin Croome told EE Times Europe that the company decided to focus Gap9 on the hearables market after receiving traction from this sector for Gap8.
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-Optical Chip Solves Hardest Math Problems Faster than GPUs
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- Optical computing startup Lightelligence has demonstrated a silicon photonics accelerator running the Ising problem more than 100 times faster than a typical GPU setup.
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-Lightmatter Raises More Funding for Photonic AI Chip
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- ightmatter, the MIT spinout building AI accelerators with a silicon photonics computing engine, announced a Series B funding round, raising an additional $80 million. The company’s technology is based on proprietary silicon photonics technology which manipulates coherent light inside a chip to perform calculations very quickly while using very little power
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-‘Unicorn’ AI Chipmaker Hailo Raises $136 Million
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- Israeli AI chip startup Hailo has raised $136 million in a Series C funding round, bringing the company’s total to $224 million. The company has also reportedly reached “unicorn” status.
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-Tachyum Launches Prodigy Universal Processor
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- May 11, 2021 — Tachyum today launched the world’s first universal processor, Prodigy, which unifies the functionality of a CPU, GPU and TPU in a single processor, creating a homogeneous architecture, while delivering massive performance improvements at a cost many times less than competing products
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-AlphaICs Begins Sampling Its Deep Learning Co-Processor
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- AlphaICs, a startup developing edge AI and learning silicon aimed at smart vision applications, is sampling its deep learning co-processor, Gluon, that also comes with a software development kit.
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-Syntiant: Analog Deep Learning Chips
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- Startup Syntiant Corp. is an Irvine, Calif. semiconductor company led by former top Broadcom engineers with experience in both innovative design and in producing chips designed to be produced in the billions, according to company CEO Kurt Busch.
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-Baidu Backs Neuromorphic IC Developer
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- MUNICH — Swiss startup aiCTX has closed a $1.5 million pre-A funding round from Baidu Ventures to develop commercial applications for its low-power neuromorphic computing and processor designs and enable what it calls “neuromorphic intelligence.” It is targeting low-power edge-computing embedded sensory processing systems.
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-Flex Logix has two paths to making a lot of money challenging Nvidia in AI
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- The programmable chip company scores $55 million in venture backing, bringing its total haul to $82 million
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-Preferred Networks develops a custom deep learning processor MN-Core for use in MN-3, a new large-scale cluster, in spring 2020
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- Dec. 12, 2018, Tokyo Japan – Preferred Networks, Inc. (“PFN”, Head Office: Tokyo, President & CEO: Toru Nishikawa) announces that it is developing MN-Core (TM), a processor dedicated to deep learning and will exhibit this independently developed hardware for deep learning, including the MN-Core chip, board, and server, at the SEMICON Japan 2018, held at Tokyo Big Site.
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-AI Startup Cornami reveals details of neural net chip
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- Stealth startup Cornami on Thursday revealed some details of its novel approach to chip design to run neural networks. CTO Paul Masters says the chip will finally realize the best aspects of a technology first seen in the 1970s.
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-AI chip startup offers new edge computing solution
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- Anaflash Inc. (San Jose, CA) is a startup company that has developed a test chip to demonstrate analog neurocomputing taking place inside logic-compatible embedded flash memory.
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-Optalysys launches world’s first commercial optical processing system, the FT:X 2000
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- Optalysys develops Optical Co-processing technology which enables new levels of processing capability delivered with a vastly reduced energy consumption compared with conventional computers. Its first coprocessor is based on an established diffractive optical approach that uses the photons of low-power laser light instead of conventional electricity and its electrons. This inherently parallel technology is highly scalable and is the new paradigm of computing.
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-Low-Power AI Startup Eta Compute Delivers First Commercial Chips
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- The firm pivoted away from riskier spiking neural networks using a new power management scheme
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-Eta Compute Debuts Spiking Neural Network Chip for Edge AI
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- Chip can learn on its own and inference at 100-microwatt scale, says company at Arm TechCon.
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-Achronix Rolls 7-nm FPGAs for AI
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- Achronix is back in the game of providing full-fledged FPGAs with a new high-end 7-nm family, joining the Gold Rush of silicon to accelerate deep learning. It aims to leverage novel design of its AI block, a new on-chip network, and use of GDDR6 memory to provide similar performance at a lower cost than larger rivals Intel and Xilinx.
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-Startup Runs AI in Novel SRAM
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- Areanna is the latest example of an explosion of new architectures spawned by the rise of deep learning. The debut of a whole new approach to computing has fired imaginations of engineers around the industry hoping to be the next Hewlett and Packard.
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-NeuroBlade Preps Inference Chip
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- Add NeuroBlade to the dozens of startups working on AI silicon. The Israeli company just closed a $23 million Series A, led by the founder of Check Point Software and with participation from Intel Capital.
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-Bill Gates just backed a chip startup that uses light to turbocharge AI
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- Luminous Computing has developed an optical microchip that runs AI models much faster than other semiconductors while using less power.
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-Chip startup Efinix hopes to bootstrap AI efforts in IoT
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- Six-year-old startup Efinix has created an intriguing twist on the FPGA technology dominated by Intel and Xiliinx; the company hopes its energy-efficient chips will bootstrap the market for embedded AI in the Internet of Things.
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-AIStorm raises $13.2 million for AI edge computing chips
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- David Schie, a former senior executive at Maxim, Micrel, and Semtech, thinks both markets are ripe for disruption. He — along with WSI, Toshiba, and Arm veterans Robert Barker, Andreas Sibrai, and Cesar Matias — in 2011 cofounded AIStorm, a San Jose-based artificial intelligence (AI) startup that develops chipsets that can directly process data from wearables, handsets, automotive devices, smart speakers, and other internet of things (IoT) devices.
-
+
+AMD — Instinct AI GPUs
+AMD’s datacenter AI story runs through the Instinct line on CDNA architecture (distinct from RDNA gaming GPUs), with ROCm as the software stack. MI100/MI200 established HBM-heavy training SKUs; MI300A/X (CDNA 3, 2023) brought chiplet APU/GPU designs into large LLM clusters. MI350 (CDNA 4, 2025) pushes HBM3E capacity and low-precision datatypes; MI400 / Helios rack systems headline the 2026 roadmap alongside deep hyperscaler partnerships.
+
+- MI100 / MI200 (CDNA 1–2) — early Instinct training accelerators; MI250X widely used in HPC+AI.
+- MI300A / MI300X (2023) — CDNA 3 chiplets; MI300X became a primary non-NVIDIA LLM training/inference GPU.
+- MI350X / MI355X (2025) — CDNA 4, up to 288GB HBM3E, MXFP6/MXFP4 paths.
+- MI400 / Helios (roadmap 2026) — rack-scale systems and custom SKUs for hyperscalers.
+
+Latest
+
+- AMD–Meta 6GW Instinct partnership — Feb 2026 — up to 6GW multi-generation Instinct GPUs; custom MI450-class on Helios with ROCm; first-GW shipments targeted H2 2026.
+- Helios / MI400 series on track — 2026 — AMD says Helios racks and MI400/MI455X UALink systems remain on track for H2 2026 engineering/low-volume production alongside MI350 volume deployments.
+
+
+
+Qualcomm — Hexagon NPU & Dragonfly data-center AI
+Qualcomm’s AI silicon now spans mobile Hexagon NPUs in Snapdragon SoCs and a full data-center Dragonfly portfolio for agentic inference. Hexagon evolved from DSP blocks into fused scalar/vector/tensor NPUs for on-device GenAI; Cloud AI 100 was an earlier inference SKU. In Oct 2025 Qualcomm launched rack-scale Dragonfly AI200/AI250 inference accelerators, then at Investor Day Jun 2026 added AI300 with High Bandwidth Compute (HBC), the Dragonfly C1000 server CPU (Meta multi-generation agreement), and a multi-year data-center revenue push.
+Latest
+
+- Dragonfly AI300 / data-center roadmap — Jun 24, 2026 Investor Day — Dragonfly AI300 (3rd-gen rack inference with HBC Gen 2; sampling ~2028) joins AI200/AI250; Dragonfly C1000 CPU (250+ Oryon cores) with multi-generation Meta server deal; HBC near-memory compute for token efficiency.
+- Dragonfly AI200 / AI250 launch — Oct 2025 — Hexagon-based rack-scale inference accelerators: AI200 (~768GB LPDDR/card, commercial ~2026) and AI250 (HBC Gen 1 near-memory, ~2027); Humain among early large deploy partners.
+
-
+
+
+Samsung — Exynos NPU
+Samsung integrates NPUs into Exynos mobile SoCs and builds HBM that underpins datacenter AI GPUs. Exynos NPUs scaled with each flagship for vision and on-device GenAI; Exynos 2500 (3nm GAA) was followed by Exynos 2600 — Samsung’s first 2nm GAA mobile SoC — powering Galaxy S26 with substantially higher generative-AI NPU performance and AI graphics features (ENSS).
+Latest
+
+- Exynos 2600 — First 2nm GAA mobile SoC; Samsung cites ~113% generative-AI NPU gains vs. prior gen for larger on-device models; ships in Galaxy S26 / S26+.
+- ENSS AI graphics on Exynos 2600 — Apr 2026 — Exynos Neural Super Sampling (ENSS) commercialized for AI upscaling/frame generation to cut GPU load on flagship gaming/graphics.
+
-
+
+
+MediaTek — Dimensity NPU
+MediaTek’s Dimensity flagship line pairs Arm CPUs with successive in-house NPUs for Android on-device AI. The NPU roadmap (through 8th-gen NPU 890 on Dimensity 9400) emphasizes generative and agentic workloads—LoRA adaptation, diffusion video, and MoE LLMs—alongside the Dimensity Agentic AI Engine software path.
+Latest
+
+- Dimensity 9500 — NPU 990 — Sep 2025 — 9th-gen NPU 990 with Generative AI Engine 2.0 (vendor: ~2× compute, 4K image gen, 128K-token LLM path) plus Super Efficient CIM NPU for always-on AI.
+
-
+
+
+Marvell — custom AI ASICs & DPUs
+Marvell supplies DPUs (OCTEON / ARMADA) and, increasingly, co-designed custom AI accelerators for cloud providers. Alongside Broadcom’s XPU franchise, Marvell is widely reported as a design partner on AWS Trainium/Inferentia-class and Microsoft Maia-class silicon—making it a key “picks and shovels” vendor in the custom-ASIC wave.
+Latest
+
+- Expanding custom silicon opportunity — Jul 2025 — Custom AI Investor Event: ~18 active custom projects (hyperscaler XPUs + attach) with TAM for custom XPUs growing into the tens of billions by 2028.
+- Hyperscaler AI ASIC programs — 2025–2026 — widely reported design partner on AWS Trainium-class and Microsoft Maia-class accelerators, plus AI optics/DPU attach silicon.
+
-SiMa.ai Raises $30 Million in Series A Investment Round Led by Dell Technologies Capital
-
- SAN JOSE, Calif.--(BUSINESS WIRE)--SiMa.ai, the company enabling high performance machine learning to go green, today announced its Machine Learning SoC (MLSoC) platform – the industry’s first unified solution to support traditional compute with high performance, lowest power, safe and secure machine learning inference. Delivering the highest frames per second per watt, SiMa.ai’s MLSoC is the first machine learning platform to break the 1000 FPS/W barrier for ResNet-501. In customer engagements, the company has demonstrated 10-30x improvement in FPS/W through its automated software flow across a wide range of embedded edge applications, over today’s competing solutions. The platform will provide machine learning solutions that range from 50 TOPs@5W to 200 TOPs@20W, delivering an industry first of 10 TOPs/W for high performance inference.
-
+
+
+Broadcom — custom XPUs
+Broadcom co-designs customer-specific AI accelerators (XPUs) and pairs them with Tomahawk/Jericho Ethernet switching. The model began with Google TPU generations and now spans Meta MTIA, OpenAI custom silicon, and other frontier/cloud programs—positioning Broadcom as the primary ASIC implementation partner opposite merchant GPUs.
+Latest
+
+- OpenAI Jalapeño with Broadcom — Jun 2026 — OpenAI’s first custom LLM inference ASIC co-developed with Broadcom (Tomahawk networking); initial deployments targeted end of 2026 within multi-GW platform.
+- Meta MTIA partnership extended — Apr 2026 — XPU platform continues as co-design backbone for multi-generation MTIA and Ethernet AI fabric.
+
-SiMa.ai™ Introduces MLSoC™ – First Machine Learning Platform to Break 1000 FPS/W Barrier with 10-30x Improvement over Alternative Solutions
-
- SiMa.ai, the company enabling high performance machine learning to go green, today announced its Machine Learning SoC (MLSoC) platform – the industry’s first unified solution to support traditional compute with high performance, lowest power, safe and secure machine learning inference. Delivering the highest frames per second per watt, SiMa.ai’s MLSoC is the first machine learning platform to break the 1000 FPS/W barrier for ResNet-501. In customer engagements, the company has demonstrated 10-30x improvement in FPS/W through its automated software flow across a wide range of embedded edge applications, over today’s competing solutions. The platform will provide machine learning solutions that range from 50 TOPs@5W to 200 TOPs@20W, delivering an industry first of 10 TOPs/W for high performance inference.
-
+II. Tech Giants & HPC Vendors
+
+
+Google — TPU lineage
+Google invented the modern custom-AI-ASIC pattern with TPU v1 (2015) for production inference, then opened Cloud TPU for external training. Each generation scaled systolic MXUs, HBM, and pod interconnect; v4/v5 pods trained many Google foundation models, while Trillium (v6e) and Ironwood (v7) address GenAI train/serve economics. Edge TPU (Coral) and Pixel Tensor are related but separate product lines.
-
+Early generations
+
+- TPU v1 (2015) — inference-only systolic MXU (INT8) in Google production services.
+- TPU v2 (2017) — training + inference, bfloat16, HBM, first multi-chip pods.
+- TPU v3 (2018) — higher compute, liquid cooling at pod scale.
+- TPU v4 (2021) — denser pods, 3D torus + optical circuit switches.
+
-
+Split SKUs & GenAI scale-up
+
+- TPU v5e (2023) — cost-efficient training/inference at volume.
+- TPU v5p (2023) — high-end large-pod training.
+- Trillium / TPU v6e (2024) — larger MXUs; Google cites ~4.7× peak compute/chip vs. v5e.
+- Ironwood / TPU v7 (2025) — inference-leaning generation with FP8-class paths and very large pods.
+
-
+Related Google silicon
+
+- Edge TPU — Coral edge inference ASIC.
+- Google Tensor (Pixel) — mobile SoC ML blocks (separate from Cloud TPU).
+
+Latest
+
+- Ironwood (TPU7x) GA — Mar 31, 2026 — TPU7x (Ironwood family) generally available for large-scale training and inference (LLMs, MoEs, diffusion); up to 9,216-chip pods.
+- Ironwood for the age of inference — 2025–2026 — 7th-gen TPU purpose-built for high-volume low-latency inference/serving; Google cites large per-chip gains vs. prior gen.
+
+10 years of TPU · v6e docs · Cloud TPU · Edge TPU
+
+
+
+Amazon AWS — Trainium & Inferentia
+AWS builds first-party AI silicon for EC2: Inferentia for inference and Trainium for training, compiled via the Neuron SDK. Inferentia1/2 lowered LLM serving cost on Inf1/Inf2; Trainium1 and Trainium2 (Trn1/Trn2) plus UltraServers with NeuronLink scale-up target foundation-model training and large inference inside AWS regions—often co-designed with partners such as Marvell/Annapurna.
+Latest
+
+- EC2 Trn3 UltraServers (Trainium3) — Dec 2025 re:Invent — Trainium3 (first 3nm AWS AI chip) UltraServers GA; AWS cites up to ~4.4× compute and ~4× energy efficiency vs. Trn2 UltraServers.
+- Trainium3 UltraServers details — Up to 144 Trainium3 chips / ~362 FP8 PFLOPs per UltraServer; Anthropic and Bedrock among early Trainium users; Trainium4 on the roadmap.
+
-Untether AI nabs $125M for AI acceleration chips
-
- Untether AI, a startup developing custom-built chips for AI inferencing workloads, today announced it has raised $125 million from Tracker Capital Management and Intel Capital. The round, which was oversubscribed and included participation from Canada Pension Plan Investment Board and Radical Ventures, will be used to support customer expansion.
-
+
+
+Microsoft — Azure Maia
+Microsoft entered custom AI silicon with Azure Maia (accelerator) and Cobalt (Arm CPU) to optimize Azure OpenAI / Copilot economics. Maia 100 (5nm, advanced packaging) is co-designed for Azure AI cloud workloads with a PyTorch/ONNX Runtime software path; subsequent Maia generations are expected to deepen rack-level integration with Azure networking and cooling.
+Latest
+
+- Maia 200 inference accelerator — Jan 2026 — TSMC 3nm inference ASIC with 216GB HBM3e; Microsoft cites ~30% better perf/$ vs. prior fleet hardware and FP4/FP8 leadership claims vs. other custom silicon.
+- Maia 200 Azure rollout — Deploying in US Central (then US West 3) for Superintelligence / Foundry / Copilot workloads; Maia SDK preview with PyTorch and Triton.
+
+
+
+OpenAI — custom Intelligence Processors
+Long dependent on NVIDIA GPUs (and Azure capacity), OpenAI moved into custom inference silicon to cut serving cost and diversify supply. Jalapeño—co-developed with Broadcom—is the first “Intelligence Processor,” optimized for LLM inference rather than general training, as the opening move in a multi-generation, multi-gigawatt Broadcom collaboration.
+Latest
+
+- Jalapeño LLM inference chip — Jun 2026 — first custom inference-optimized ASIC with Broadcom; initial deployments targeted by end of 2026 within a multi-generation platform.
+
-
+
+
+Anthropic — multi-hardware compute
+Anthropic does not tape out a merchant chip brand; it co-designs capacity across AWS Trainium (Project Rainier), Google TPUs (Broadcom-implemented), and NVIDIA GPUs. The strategy is deliberate multi-sourcing for Claude training and serving at gigawatt scale, with long-term TPU commitments expanding through 2027+.
+Latest
+
-
+
+
+Apple — Neural Engine & Apple silicon AI
+Apple’s on-device AI runs on the Neural Engine and, increasingly, GPU Neural Accelerators inside Apple silicon—not discrete datacenter GPUs. From A11’s first Neural Engine through M1–M4, Apple scaled unified-memory ML performance for privacy-preserving inference; M5 (2025) and M5 Pro/Max (2026) explicitly target Apple Intelligence and local LLM/creative AI workflows.
+Latest
+
+- Apple M5 — Oct 2025 — Neural Accelerators in each GPU core and a faster 16-core Neural Engine for on-device Apple Intelligence.
+- M5 Pro and M5 Max — Mar 2026 — Fusion Architecture scales GPU AI compute and unified memory (up to 128GB / ~614GB/s on M5 Max) for local LLM and pro creative AI.
+
-
+
+
+Alibaba — T-Head PPU
+Alibaba’s T-Head unit designs cloud AI accelerators under the Zhenwu / PPU family for Alibaba Cloud and external customers as a domestic GPU-class alternative. After Zhenwu 810E-class SKUs, Zhenwu M890 (2026) raises HBM capacity and chip-to-chip bandwidth for agentic train/infer, paired with Panjiu AL128 servers, ICN Switch networking, and the SAIL software stack.
+Latest
+
+- Zhenwu M890 AI chip — May 2026 Cloud Summit — M890 triples prior-gen performance claims with 144GB HBM3 and 800GB/s chip-to-chip bandwidth; FP32→FP4; powers Panjiu AL128 with ICN Switch 1.0.
+- T-Head scale shipments — 2026 — T-Head cites 560,000+ Zhenwu AI chips shipped and 400+ external customers; further V900 (2027) / J900 (2028) roadmap messaging.
+
-GrAI Matter Labs Reveals NeuronFlow Technology and Announces GrAIFlow SDK
+
+
+Baidu — Kunlunxin
+Baidu’s Kunlunxin (昆仑芯) GPUs underpin ERNIE and Baidu Cloud AI services. From earlier Kunlun generations through P800-class training/inference cards, Baidu has iterated a full stack (hardware + software) as a China-domestic alternative for large-model workloads.
+Latest
+
+- Kunlunxin trains key ERNIE 5.1 version — Baidu Create 2026 — P800 completed large-scale validation with multiple 10k-card clusters since 2025; fully domestic Kunlunxin cluster trained a key ERNIE 5.1 version (97% effective training rate claimed).
+- Tianchi 256-card supernode — May 2026 — Tianchi 256-card Kunlunxin supernode lit up, June launch messaging; +25% throughput / +50% inference efficiency claims vs. prior gen, HPN5.0 networking.
+
-
- GrAI Matter Labs (aka GML), a neuromorphic computing pioneer today revealed NeuronFlow – a new programmable processor technology – and announced an early access program to its GrAIFlow software development kit.
-
+
+
+Tencent Cloud — Zixiao / custom AI
+Tencent deploys proprietary Zixiao-class and partner AI accelerators across Tencent Cloud for recommendation, multimodal, and LLM train/infer inside its China footprint—part of a broader mix that also includes merchant GPUs where available.
+Latest
+
+- Tencent Cloud AI accelerators — 2025–2026 — proprietary Zixiao-class and partner AI accelerators deployed for recommendation, multimodal, and LLM train/infer inside Tencent Cloud.
+
-
+
+
+Meta — MTIA
+Meta’s MTIA (Meta Training and Inference Accelerator) is an in-house family for ranking, recommendation, and increasingly generative workloads at hyperscale. Built with Broadcom as implementation partner, MTIA has moved to a rapid multi-generation chiplet cadence (MTIA 300–500 class messaging) aimed at Meta’s production AI fleet rather than merchant sale.
+Latest
+
+- MTIA Iris production September 2026 — Jul 2026 reporting — next-gen MTIA chip (Iris / v3) cleared testing and targets September production with Broadcom design + TSMC 3nm; part of ~6-month cadence through 2027.
+- Four MTIA chips in two years — Multi-generation MTIA roadmap (300–500 class) with modular chiplets; continues alongside AMD Instinct and NVIDIA GPU capacity.
+
-
+
+
+Tesla — HW / AI inference & Dojo
+Tesla designs FSD/AI inference SoCs for vehicles (HW3 → HW4/AI4 → AI5) and pursued Dojo training tiles for internal vision-model training. The vertical stack ties cars, Optimus, and data-center inference together; AI5 is the next major SoC step after AI4, with Dojo3 still on the longer training roadmap.
+Latest
+
+- Tesla AI5 taped out — Apr 2026 — AI5 inference/training SoC taped out; AI6/Dojo3 mentioned as in progress; broad vehicle deployment still gated (reports: mid–late 2027+).
+
-
+III. Traditional IP Vendors
+
+
+Arm — Ethos NPU IP
+Arm licenses Ethos NPU IP alongside Cortex CPUs for edge and IoT SoCs. The Ethos-U micro-NPU line (U55 → U65 → U85) scales MAC arrays and adds transformer operators while keeping the Vela/Ethos toolchain path; larger Ethos-N products address higher-TOPS vision/GenAI in Cortex-A systems.
+Latest
+
+- Ethos-U85 micro-NPU — Third-gen Ethos-U (to ~4 TOPS @ 1 GHz) with native transformer ops for edge/IoT GenAI; Corstone-320 reference and Vela toolchain.
+- Arm C1 / SME2 in flagship SoCs — 2025 — Arm Lumex CSS (C1 cores + SME2) ships in MediaTek Dimensity 9500-class SoCs, accelerating on-CPU ML alongside NPUs.
+
-Rain Neuromorphics on Crunchbase
-
- We build artificial intelligence processors, inspired by the brain. Our mission is to enable brain-scale intelligence.
-
+
+
+Synopsys — ARC NPX NPU IP
+Synopsys DesignWare ARC NPX provides licensable neural processor IP for SoC integrators across automotive, consumer, and infrastructure. The family emphasizes scalable TOPS, functional-safety options, and toolchain continuity for DNN/transformer graphs.
+Latest
+
+- ARC NPX NPU IP — 2025–2026 — DesignWare ARC NPX neural processor IP for automotive/consumer/infrastructure SoCs; multi-TOPS configs and transformer-ready toolchain updates.
+
-
+
+
+Imagination — NNA IP
+Imagination’s PowerVR Neural Network Accelerators (NNA) and GPU+NNA combinations target edge and automotive SoCs. IMG Continuum software maps CNN and transformer-class networks onto the NNA datapaths for licensees.
+Latest
+
+- Imagination AI / NNA IP — 2025–2026 — PowerVR Neural Network Accelerators and GPU+NNA combinations for edge and automotive SoCs with Continuum software for transformer-class nets.
+
-
+
+
+CEVA — NeuPro / edge AI IP
+CEVA licenses low-power AI processor IP and DSP/NPU hybrids for real-time embedded, automotive, and IoT inference. NeuPro-class offerings and the CEVA DNN compiler add transformer-capable paths for on-device GenAI and vision.
+Latest
+
+- CEVA edge AI / NeuPro IP — 2025–2026 — low-power NeuPro-class AI processor IP and DNN graph compiler for real-time embedded, automotive, and IoT inference including transformers.
+
-
+
+
+Cadence — Tensilica AI IP
+Cadence Tensilica offers configurable NPU and AI DSP IP for on-device and automotive SoCs. The NeuroWeave toolchain maps modern DNN and transformer graphs onto Tensilica datapaths used widely in vision, audio, and edge GenAI chips.
+Latest
+
+- Tensilica AI Platform — 2025–2026 — Tensilica NPU/AI DSP IP with NeuroWeave toolchain updates for modern DNN and transformer workloads in edge/auto SoCs.
+
-Applied Brain Research on Crunchbase
-
- ABR makes the world's most advanced neuromoprhic compiler, runtime and libraries for the emerging space of neuromorphic computing.
-
+
+
+VeriSilicon — VIP NPU IP
+VeriSilicon provides VIP/Acuity NPU IP plus turnkey ASIC design services, especially strong in China edge and vision SoCs. The IP covers CNN through on-device GenAI use cases for consumer, automotive, and IoT customers.
+Latest
+
+- VIP / NPU IP & design services — 2025–2026 — Acuity/VIP NPU IP plus turnkey ASIC design services widely used in China and global edge SoCs for vision and on-device GenAI.
+
-
+
+
+
+
+Cerebras — wafer-scale engine
+Cerebras builds wafer-scale AI processors (WSE) that place an enormous on-wafer SRAM/compute fabric into CS systems, avoiding many multi-GPU communication bottlenecks. WSE-1/2 established the approach; WSE-3 (2024, 5nm) powers CS-3 for foundation-model training and high-throughput inference with cloud and on-prem deployments.
+Latest
+
+- Cerebras IPO (CBRS) — May 2026 — blockbuster Nasdaq debut after filing; WSE-3 / CS-3 wafer-scale systems power Training and Inference Cloud services.
+- OpenAI multi-year capacity deal — 2025–2026 — OpenAI commits to large inference capacity (filings cite 750MW committed, option to 2GW) plus $1B infrastructure loan / warrants.
+
-
+
+
+Graphcore — IPU
+Graphcore pioneered Intelligence Processing Units (IPU) with fine-grained MIMD parallelism and large on-chip memory (Colossus Mk1/Mk2, Bow). After competing in the pre-LLM and early-LLM era, SoftBank acquired Graphcore (2024) as a wholly owned subsidiary to fund next-generation AI compute while keeping the Graphcore brand.
+Latest
+
+- SoftBank $457M funding into Graphcore — May 2026 — SoftBank funnels ~$457M into Graphcore (wholly owned since Jul 2024) to fund next-gen AI silicon and SoftBank AI infra plans.
+- Izanagi / SoftBank AI stack — 2025–2026 — next-gen accelerator work (Izanagi messaging) pairs Graphcore IPU heritage with SoftBank/Ampere Arm CPU stack for hyperscale deployment targets.
+
-
+
+
+Tenstorrent — Wormhole / Blackhole
+Tenstorrent (Jim Keller–led) builds Tensix-based AI processors as scalable chiplet meshes with an open software stack (TT-Metalium). Wormhole-generation cards are shipping into developer and rack deployments; Blackhole is the next architecture step toward higher-density train/infer systems.
+Latest
+
+- Galaxy Blackhole general availability — Apr 28, 2026 — 6U air-cooled Galaxy with 32 Blackhole chips shipping (vendor: 23 PFLOPS Block FP8, Ethernet scale-out); from ~$110k per server.
+- TT-Deploy production shipping — May 2026 — TT-Deploy: volume shipping, multi-Galaxy superclusters, open TT-Metalium stack, and third-party validated serving benchmarks.
+
-XMOS adapts Xcore into AIoT ‘crossover processor’
-
- EE Times exclusive! The new chip targets AI-powered voice interfaces in IoT devices — “the most important AI workload at the endpoint.”
-
+
+
+Etched — transformer ASICs
+Etched builds ASICs purpose-built for Transformer inference (Sohu) rather than general-purpose GPU programmability—betting that specialization wins tokens/sec and energy efficiency for LLM serving. TSMC-manufactured silicon and “frontier inference cluster” messaging mark a fast rise from 2024 Series A through 2026 scale-up.
+Latest
+
+- Etched hits $5B valuation — Jun 2026 — ~$800M raised to date (incl. $500M at $5B valuation) and ~$1B in booked system orders for transformer-specialized ASICs.
+
-XMOS unveils Xcore.ai, a powerful chip designed for AI processing at the edge
-
- The latest xcore.ai is a crossover chip designed to deliver high-performance AI, digital signal processing, control, and input/output in a single device with prices from $1.
-
+
+
+Groq — LPU
+Groq’s Language Processing Unit (LPU) uses a deterministic, compiler-scheduled architecture for ultra-low-latency LLM token generation. After building a cloud inference service on LPU racks, Groq’s technology was licensed by NVIDIA (late 2025), with key talent joining NVIDIA; GTC 2026 described LPU-class engines inside the Vera Rubin AI factory for efficient decode alongside Rubin GPUs.
+Latest
+
+- NVIDIA Vera Rubin includes Groq LPU — Late 2025 NVIDIA licensed Groq LPU tech; GTC 2026 — LPU-class engines integrated into Vera Rubin for low-latency / high-efficiency token generation.
+
-
+
+
+SambaNova — RDU
+SambaNova’s Reconfigurable Dataflow Unit (RDU) maps full model graphs onto a dataflow fabric for enterprise and agentic inference. SN40L established the GenAI-era platform; SN50 (5th gen) scales compute and network bandwidth for large agentic deployments with SambaNova’s full-stack software.
+Latest
+
+- SN50 RDU, Intel collab, $350M+ Series E — Feb 2026 — SN50 targets agentic inference (vendor: ~5× compute / ~4× network vs. SN40L); SoftBank early deploy; H2 2026 shipping; Intel heterogeneous-inference collaboration.
+
-
+
+
+Mythic — analog compute-in-memory
+Mythic builds Analog Processing Units (APUs) that use flash-based compute-in-memory for energy-efficient inference at the edge and in data centers. After years of analog AI development, 2025–2026 funding and the Videantis acquisition add digital processor IP for a hybrid analog/digital platform aimed at robotics, automotive, and defense.
+Latest
+
+- $125M Series D — Dec 2025 — oversubscribed DCVC-led round (Honda, Lockheed Martin among strategics) to scale APUs and chiplet next-gen products.
+- Acquires Videantis — May 2026 — Videantis digital processor IP + software joins Mythic analog CIM for a hybrid efficiency-focused platform.
+
-
+
+
+Hailo — edge AI accelerators
+Hailo designs high-efficiency edge AI accelerators for vision and, with Hailo-10, on-device generative AI. Hailo-8 established the structure-sparsity / efficient-NPU brand in smart cameras and industrial vision; Hailo-10H adds LLM/VLM-class GenAI at low watts with automotive qualification paths.
+Latest
+
+- Hailo-10H GA for edge GenAI — Jul 2025 — second-gen Hailo-10H for on-device LLM/VLM/GenAI (~40 TOPS INT4, ~2.5W typical); AEC-Q100 Grade 2 with 2026 SOP targeting.
+
-
- We design and produce AI processors and the software to run them in data centers. Our unique approach optimizes for inference with the focus on performance, power efficiency, and ease of use; and at the same time our approach enables cost-effective training.
-
+
+
+FuriosaAI — RNGD / TCP
+Korea-based FuriosaAI builds Tensor Contraction Processor (TCP) accelerators for datacenter inference. After earlier Warboy edge/vision chips, RNGD (TSMC 5nm) targets LLM and agentic serving in air-cooled multi-card servers, with a Broadcom collaboration to scale into multi-die Ethernet/PCIe platforms.
+Latest
+
+- RNGD mass production — Jan 2026 — RNGD (~180W PCIe) volume shipment for LLM/agentic inference; NXT RNGD servers pack multiple cards into ~3kW-class air-cooled systems.
+- Broadcom inference partnership — May 2026 — evolve TCP into a scale-up multi-die inference platform with Broadcom Ethernet/PCIe switching.
+
-
+
+
+Kinara (ex–Deep Vision)
+Kinara (formerly Deep Vision) builds Ara/Prisma-class edge NPUs for vision and on-device GenAI inference. The company rebranded and scaled edge AI SKUs before NXP announced an acquisition (2025) to fold Kinara into NXP’s industrial and automotive edge AI portfolio.
+Latest
+
+- NXP to acquire Kinara — Feb 2025 — NXP acquisition of Kinara for edge AI NPUs used in vision and on-device GenAI; expands NXP industrial/automotive AI.
+
-
+
+
+SiMa.ai — Modalix MLSoC
+SiMa.ai builds MLSoC platforms for edge / Physical AI—robots, industrial, automotive, and vision—combining CPU, ML accelerator, and software (Palette / LLiMa) for CNN through Transformer/LLM workloads at low power. Modalix is the second-generation production platform after the first MLSoC.
+Latest
+
-
+
+
+d-Matrix — Corsair
+d-Matrix builds digital compute-in-memory accelerators (Corsair) for low-latency, high-efficiency datacenter LLM inference—contrasting analog CIM approaches with a digital datapath while still attacking the memory-wall bottleneck that dominates decode.
+Latest
+
+- Corsair enters full production — Jun 2026 — Corsair digital in-memory inference platform in volume production (TSMC N6); shipping to priority hyperscalers, neoclouds, and frontier labs.
+- Series C / $2B valuation — Nov 2025 — $275M Series C (incl. Microsoft M12) at ~$2B valuation to scale Corsair rack-scale inference.
+
-
- We build high-performance AI inference coprocessors that can be seamlessly integrated into various computing platforms including data centers, servers, desktops, automobiles and robots.
-
+
+
+Blaize — Graph Streaming Processor
+Blaize’s Graph Streaming Processor (GSP) targets graph-native edge AI for vision and GenAI in industrial and smart-city deployments. After years as a private edge-AI vendor, Blaize listed via SPAC (Nasdaq: BZAI) in 2025 to scale product and go-to-market.
+Latest
+
+- Blaize AI edge platforms — 2025 — listed via SPAC; GSP architecture for edge AI vision / GenAI in industrial and smart-city deployments.
+
-
+
+
+SynSense (ex–aiCTX)
+SynSense (formerly aiCTX) builds neuromorphic and event-based sensing+compute chips (Speck, Xylo) for ultra-low-power always-on perception. Collaborations such as with iniVation extend event-camera + neuromorphic pipelines for edge AI.
+Latest
+
+- SynSense neuromorphic products — 2025–2026 — Speck/Xylo-class neuromorphic chips and event-based vision+compute offerings (incl. prior iniVation collaboration) for always-on edge sensing.
+
-
+
+
+Sagence AI (ex–Analog Inference)
+Sagence AI (rebranded from Analog Inference in Nov 2024) develops analog compute-in-memory accelerators aimed at energy-efficient LLM and vision inference for datacenter and edge deployments—part of the broader analog-AI cohort seeking orders-of-magnitude efficiency vs. digital GPUs on inference.
+Latest
+
+- Sagence AI analog CIM — 2025–2026 — continues analog compute-in-memory accelerators (ex–Analog Inference) aimed at energy-efficient datacenter/edge LLM and vision inference.
+
-
+V. China AI Accelerator Vendors
+Domestic training/inference accelerators have become central under export-control and procurement policies. Coverage below highlights widely reported product lines; treat performance claims as vendor-/press-reported unless independently benchmarked.
+
+
+
+
+
Huawei Ascend / HiSilicon
+Huawei’s Ascend line (HiSilicon) is China’s most widely deployed domestic training/inference accelerator family. Ascend 910 established the high-end; 910B/910C scaled under export controls into Atlas servers and SuperPoD / CloudMatrix supernodes. Ascend 950-class (950DT training / 950PR inference messaging) and Atlas 950 SuperPoD push UnifiedBus optical scale-up to thousands of NPUs as a single logical node, with Cann/MindSpore as the software stack.
+Latest
+
+- Atlas 950 SuperPoD at MWC 2026 — Mar 2026 — global debut of Atlas 950 SuperPoD on UnifiedBus; scales from 64 NPUs/cabinet toward up to 8,192 Ascend 950-class NPUs for large-model train/infer.
+- Atlas 950 SuperPoD at WAIC 2026 — Jul 2026 — first public hardware demonstration planned at WAIC Shanghai; single-cabinet 64-card base with global unified memory addressing for trillion-parameter models.
+
-
- Corerain provides ultra-high performance AI acceleration chips and the world's first streaming engine-based AI development platform.
-
+
+
+Cambricon (寒武纪)
+Cambricon is China’s leading pure-play AI-chip vendor, spanning edge IP/SoCs and cloud MLU / Siyuan accelerators. After an early edge-IP era, the company refocused on cloud training/inference cards for Chinese internet and intelligent-computing customers, with aggressive 2026 volume plans.
+Latest
+
+- Siyuan 690 mass production — 2026 — next-gen Siyuan/MLU 690 cloud accelerators in mass production/delivery (reports: dual-die, ~196GB HBM3, >700 TFLOPS FP16-class); Q1 profit surged on domestic cloud demand.
+- 500,000 AI chips target for 2026 — Aggressive 2026 volume plans for Siyuan 590/690-class accelerators serving Chinese internet/cloud customers as a leading pure-play domestic AI-chip vendor.
+
-
+
+
+Biren Technology (壁仞)
+Biren builds high-performance GPGPU / AI accelerators (BR100 class) positioned as domestic alternatives for training and inference. After years of product development under export-control pressure, Biren listed in Hong Kong in early 2026, raising capital to scale production and software.
+Latest
+
+- Hong Kong listing debut — Jan 2026 — listed 6082.HK, raising ~HK$5.58B; BR100-class accelerators as high-performance domestic alternatives.
+
-
+
+
+Moore Threads (摩尔线程)
+Moore Threads develops full-function GPUs for graphics and AI (MTT S-series) with the MUSA software stack. The company completed a large STAR Market IPO in late 2025 amid China’s domestic GPU push, targeting intelligent-computing centers and PC/GPU markets.
+Latest
+
+- Shanghai trading debut — Dec 2025 — ~$1.1B STAR Market IPO; MTT S4000/S5000-class AI cards and MUSA stack in the domestic GPU wave.
+
-
+
+
+MetaX (沐曦)
+MetaX (沐曦) ships C-series GPUs for training and inference with the MXMACA software stack for AI clusters and intelligent-computing centers. After listing on STAR in Dec 2025, the company reported strong revenue growth into 2026 as domestic GPU demand rose.
+Latest
+
+- MetaX doubles revenue — C500 mass production; C600 domestic-process follow-on; STAR 688802.SH (listed Dec 2025) with MXMACA for AI clusters.
+
-Perceive emerges from stealth with Ergo edge AI chip
-
- On-device computing solutions startup Perceive emerged from stealth today with its first product: the Ergo edge processor for AI inference. CEO Steve Teig claims the chip, which is designed for consumer devices like security cameras, connected appliances, and mobile phones, delivers “breakthrough” accuracy and performance in its class.
-
+
+
+Hygon (海光) DCU
+Hygon’s Deep Computing Unit (DCU) accelerators are GPGPU-class chips widely used in China for large-model training and inference, paired with the DTK software stack. Hygon also ships x86 CPUs; the DCU line is the AI-relevant product for intelligent-computing centers.
+Latest
+
+- DeepSeek-V4 Day-0 adaptation — 2025–2026 — DCU + DTK widely used for LLM train/infer; same-day DeepSeek model adaptations reported with Ascend and Cambricon.
+
-
+
+
+Iluvatar CoreX (天数智芯)
+Iluvatar CoreX (天数智芯) designs general-purpose GPUs for AI training and inference (BI-V series) with a multi-generation architecture roadmap. Hong Kong-listed, the company publicly frames Tianshu / Tianxuan / Tianji / Tianquan messaging against NVIDIA Hopper→Blackwell→Rubin class platforms.
+Latest
+
+- Roadmap vs. NVIDIA Rubin — Jan 2026 — multi-generation GPU roadmap; BI-V150-class products already in AI train/infer deployments.
+
-
+
+
+Enflame (燧原)
+Enflame (燧原) builds CloudBlazer / iGCU accelerators for domestic training and inference in intelligent-computing centers. The TopsRider software stack targets LLM workloads alongside hardware refreshes through 2024–2026.
+Latest
+
+- CloudBlazer / iGCU accelerators — 2025–2026 — domestic train/infer GPUs deployed in China intelligent-computing centers with TopsRider software updates for LLM workloads.
+
-
+
+
+Horizon Robotics (地平线)
+Horizon Robotics (地平线) is a leading China automotive AI SoC vendor. Journey-series chips (through Journey 6 with BPU Nash) power L2+ assisted driving in many passenger vehicles, with increasing Transformer support for BEV/occupancy and end-to-end driving models.
+Latest
+
+- Journey 6 / BPU Nash — 2025–2026 — Journey 6 automotive AI SoCs with BPU Nash and stronger Transformer support widely designed into China passenger vehicles for L2+ ADAS.
+
-SimpleMachines, Inc. Debuts First-of-its-Kind High Performance Chip
-
- As traditional chip makers struggle to embrace the challenges presented by the rapidly evolving AI software landscape, a San Jose startup has announced it has working silicon and a whole new future-proof chip paradigm to address these issues.
+
+
+Black Sesame Technologies (黑芝麻智能)
+Black Sesame Technologies (黑芝麻智能) designs automotive-grade ADAS/AD SoCs (Huashan family). Hong Kong-listed in 2024, the company focuses on safety-certified L2+/L3 platforms; A1000-family chips are reported in mass-production vehicles, with A2000 extending toward higher-performance and cross-domain AI.
+Latest
+
+- Huashan A1000 / A2000 path — 2025–2026 — A1000-family chips reported in mass-production L2+/L3 vehicles; A2000 messaging extends toward higher-performance and cross-domain AI inference.
+
-The SimpleMachines, Inc. (SMI) team – which includes leading research scientists and industry heavyweights formerly of Qualcomm, Intel and Sun Microsystems – has created a first-of-its-kind easily programmable, high-performance chip that will accelerate a wide variety of AI and machine-learning applications.
-
-
+
-
AI Chip Compilers
+
-NeuReality unveiled NR1-P, A novel AI-centric inference platform
-
- NeuReality has unveiled NR1-P, a novel AI-centric inference platform. NeuReality has already started demonstrating its AI-centric platform to customers and partners. NeuReality has redefined today’s outdated AI system architecture by developing an AI-centric inference platform based on a new type of System-on-Chip (SoC).
-
+
-NeuReality raises $8M for its novel AI inferencing platform
-
- NeuReality, an Israeli AI hardware startup that is working on a novel approach to improving AI inferencing platforms by doing away with the current CPU-centric model, is coming out of stealth today and announcing an $8 million seed round.
-
-
-
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+AI Chip Benchmarks
+
-
-
Analog inference startup raises $10.6 million
-
- The company is backed by Khosla Ventures and is developing its first generation of products for AI computing at the edge. The company raised $4.5 million shortly after its formation in March 2018, so the latest tranche brings the total raised to-date to $15.1 million
-
+
-
-
+1.
MLPerf (MLCommons) — industry-standard training, inference, HPC, and client benchmarks.
+
Latest results (2026):
+
Inference v6.0 ·
+
Training v6.0 ·
+
Results visualizer
+2.
DAWNBench (historical end-to-end ImageNet benchmark)
+3.
Fathom — reference workloads for modern deep learning methods
+4.
AI-Benchmark — mobile / edge AI scores
+5.
EEMBC MLMark
+6.
AIIA DNN Benchmark
-
-
Quadric Announces Unified Silicon and Software Platform Optimized for On-Device AI
-
- BURLINGAME, Calif., June 22, 2021 — Quadric (quadric.io), an innovator in high-performance edge processing, has introduced a unified silicon and software platform that unlocks the power of on-device AI.
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-
-
EdgeQ reveals more details behind its next-gen 5G/AI chip
-
- 5G is the current revolution in wireless technology, and every chip company old and new is trying to burrow their way into this ultra-competitive — but extremely lucrative — market. One of the most interesting new players in the space is EdgeQ, a startup with a strong technical pedigree via Qualcomm that we covered last year after it raised a nearly $40 million Series A.
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+
-Innatera Unveils Neuromorphic AI Chip to Accelerate Spiking Networks
-
- Innatera, the Dutch startup making neuromorphic AI accelerators for spiking neural networks, has produced its first chips, gauged their performance, and revealed details of their architecture.
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-Redpine Founder Launches AI Processor Startup
-
- Ceremorphic, an AI chip startup emerging from stealth mode this week, is readying a heterogeneous AI processor aimed at model training in data centers, automotive, high-performance computing, robotics and other emerging applications.
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-Aspinity Analog ML Chip Allows Battery-Powered “Always On”
-
- Machine learning (ML) is all about massive amounts of processing, DSP, etc., right? Maybe not, according to the team at Aspinity. The company continues to push ahead on the analog front. The latest member of the company’s analogML family, the AML100, operates completely in the analog domain. As a result, it can reduce always-on system power by 95% (for the record, we had to walk through this a couple of times before I believed them).
-
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-TetraMem enjoyed an exciting public debut of our analog in-memory compute technology at the Linley Spring 2022 Processor Conference.
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-Exclusive: AI chip startup d-Matrix raises $110 million with backing from Microsoft
-
- Sept 6 (Reuters) - Silicon Valley-based artificial intelligence chip startup d-Matrix has raised $110 million from investors that include Microsoft Corp (MSFT.O) at a time when many chip companies are struggling to raise cash.
-
-
-D-Matrix AI chip promises efficient transformer processing
-
- The startup combines digital in-memory compute and chiplet implementations for data-center-grade inference.
-
-
-
-
-
-
-AI Chip Compilers
-
-
-1. pytorch/glow
-2. TVM:End to End Deep Learning Compiler Stack
-3. Google Tensorflow XLA
-4. Nvidia TensorRT
-5. PlaidML
-6. nGraph
-7. MIT Tiramisu compiler
-8. ONNC (Open Neural Network Compiler)
-9. MLIR: Multi-Level Intermediate Representation
-10. The Tensor Algebra Compiler (taco)
-11. Tensor Comprehensions
-12. PolyMage Labs
-13. OctoML
-14. Modular AI
-
-
-
-
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-AI Chip Benchmarks
-
-
-
-1. DAWNBench:An End-to-End Deep Learning Benchmark and Competition Image Classification (ImageNet)
-2. Fathom:Reference workloads for modern deep learning methods
-3. MLPerf:A broad ML benchmark suite for measuring performance of ML software frameworks, ML hardware accelerators, and ML cloud platforms.
-You can find latest MLPerf results: training 2.1, HPC 2.0, inference tiny 1.0 here..
-You can find MLPerf inference results v2.1 here..
-You can find MLPerf training results v1.0 here..
-
-4. AI Matrix
-5. AI-Benchmark
-6. AIIABenchmark
-7. EEMBC MLMark Benchmark
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-
-
-Reference
-
-
-
-
-
-1. FPGAs and AI processors: DNN and CNN for all
-2. 12 AI Hardware Startups Building New AI Chips
-3. Tutorial on Hardware Architectures for Deep Neural Networks
-4. Neural Network Accelerator Comparison
-5. "White Paper on AI Chip Technologies 2018". You can download it from here, or Google drive.
-5. "What We Talk About When We Talk About AI Chip". #1, #2, #3, #4
-6. AI Chip Paper List
-7. TPU vs GPU vs Cerebras vs Graphcore: A Fair Comparison between ML Hardware
+
+
+Reference
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+
+
+
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+
