diff --git a/cores/arduino/Arduino.h b/cores/arduino/Arduino.h index 175dcf705..160a94cf7 100644 --- a/cores/arduino/Arduino.h +++ b/cores/arduino/Arduino.h @@ -46,6 +46,7 @@ extern "C"{ // Include Atmel headers #include "sam.h" +#include "same5x_compat_shim.h" #include "wiring_constants.h" #define clockCyclesPerMicrosecond() ( SystemCoreClock / 1000000L ) diff --git a/cores/arduino/Reset.cpp b/cores/arduino/Reset.cpp index 9bde4a8c0..77bc3f75c 100644 --- a/cores/arduino/Reset.cpp +++ b/cores/arduino/Reset.cpp @@ -33,7 +33,7 @@ extern const uint32_t __text_start__; #else -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) #define APP_START 0x00004004 #else #define APP_START 0x00002004 @@ -42,7 +42,7 @@ extern const uint32_t __text_start__; #endif static inline bool nvmReady(void) { -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) return NVMCTRL->STATUS.reg & NVMCTRL_STATUS_READY; #else return NVMCTRL->INTFLAG.reg & NVMCTRL_INTFLAG_READY; @@ -54,7 +54,7 @@ static void banzai() { // Disable all interrupts __disable_irq(); -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) //THESE MUST MATCH THE BOOTLOADER #define DOUBLE_TAP_MAGIC 0xf01669efUL #define BOOT_DOUBLE_TAP_ADDRESS (HSRAM_ADDR + HSRAM_SIZE - 4) diff --git a/cores/arduino/SERCOM.cpp b/cores/arduino/SERCOM.cpp index f945a847f..0cf1366a7 100644 --- a/cores/arduino/SERCOM.cpp +++ b/cores/arduino/SERCOM.cpp @@ -47,7 +47,7 @@ SERCOM::SERCOM(Sercom* s) #elif SERCOM_SPI_FREQ_REF == 100000000 // 100 MHz clock = GCLK2 clockSource = SERCOM_CLOCK_SOURCE_100M; #endif -#endif // end __SAMD51__ +#endif // end SAMD51/SAME5x } /* ========================= diff --git a/cores/arduino/SERCOM.h b/cores/arduino/SERCOM.h index 35c90f1c4..9ec62ddfe 100644 --- a/cores/arduino/SERCOM.h +++ b/cores/arduino/SERCOM.h @@ -20,6 +20,7 @@ #define _SERCOM_CLASS_ #include "sam.h" +#include "same5x_compat_shim.h" // SAMD51 has configurable MAX_SPI, else use peripheral clock default. // Update: changing MAX_SPI via compiler flags is DEPRECATED, because diff --git a/cores/arduino/Tone.cpp b/cores/arduino/Tone.cpp index b47a1a278..076a38ce0 100644 --- a/cores/arduino/Tone.cpp +++ b/cores/arduino/Tone.cpp @@ -30,7 +30,7 @@ volatile int64_t toggleCount; volatile bool toneIsActive = false; volatile bool firstTimeRunning = false; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) #define TONE_TC TC0 #define TONE_TC_IRQn TC0_IRQn #define TONE_TC_GCLK_ID TC0_GCLK_ID @@ -86,7 +86,7 @@ void tone (uint32_t outputPin, uint32_t frequency, uint32_t duration) NVIC_SetPriority(TONE_TC_IRQn, 5); -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) GCLK->PCHCTRL[TONE_TC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); #else // Enable GCLK for TC4 and TC5 (timer counter input clock) @@ -150,7 +150,7 @@ void tone (uint32_t outputPin, uint32_t frequency, uint32_t duration) uint16_t tmpReg = 0; tmpReg |= TC_CTRLA_MODE_COUNT16; // Set Timer counter Mode to 16 bits -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) TONE_TC->COUNT16.WAVE.reg = TC_WAVE_WAVEGEN_MFRQ; // Set TONE_TC mode as match frequency #else tmpReg |= TC_CTRLA_WAVEGEN_MFRQ; // Set TONE_TC mode as match frequency diff --git a/cores/arduino/USB/SAMD21_USBDevice.h b/cores/arduino/USB/SAMD21_USBDevice.h index 00da069db..babfdc9a8 100644 --- a/cores/arduino/USB/SAMD21_USBDevice.h +++ b/cores/arduino/USB/SAMD21_USBDevice.h @@ -42,13 +42,13 @@ class USBDevice_SAMD21G18x { // Enable inline void enable() { usb.CTRLA.bit.ENABLE = 1; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) while( usb.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE ); //wait for sync #endif } inline void disable() { usb.CTRLA.bit.ENABLE = 0; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) while( usb.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE ); //wait for sync #endif } diff --git a/cores/arduino/USB/USBCore.cpp b/cores/arduino/USB/USBCore.cpp index 83a3e5d32..fe168561f 100644 --- a/cores/arduino/USB/USBCore.cpp +++ b/cores/arduino/USB/USBCore.cpp @@ -246,7 +246,7 @@ bool USBDeviceClass::sendDescriptor(USBSetup &setup) } else if (setup.wValueL == ISERIAL) { #ifdef PLUGGABLE_USB_ENABLED -#ifdef __SAMD51__ +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) #define SERIAL_NUMBER_WORD_0 *(volatile uint32_t*)(0x008061FC) #define SERIAL_NUMBER_WORD_1 *(volatile uint32_t*)(0x00806010) #define SERIAL_NUMBER_WORD_2 *(volatile uint32_t*)(0x00806014) @@ -333,7 +333,7 @@ void USBDeviceClass::init() #endif /* Enable USB clock */ -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) MCLK->APBBMASK.reg |= MCLK_APBBMASK_USB; MCLK->AHBMASK.reg |= MCLK_AHBMASK_USB; @@ -377,7 +377,7 @@ void USBDeviceClass::init() usbd.setFullSpeed(); // Configure interrupts -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) /* Attach to the USB host */ NVIC_SetPriority(USB_0_IRQn, 0UL); NVIC_SetPriority(USB_1_IRQn, 0UL); diff --git a/cores/arduino/USB/samd21_host.c b/cores/arduino/USB/samd21_host.c index 7d59f9c45..8f1d46cc2 100644 --- a/cores/arduino/USB/samd21_host.c +++ b/cores/arduino/USB/samd21_host.c @@ -28,6 +28,7 @@ #include "USB_host.h" #include "samd21_host.h" #include "sam.h" +#include "same5x_compat_shim.h" #include "wiring_digital.h" #include "wiring_private.h" @@ -68,7 +69,7 @@ void UHD_Init(void) USB_SetHandler(&UHD_Handler); /* Enable USB clock */ -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) MCLK->APBBMASK.reg |= MCLK_APBBMASK_USB; #else PM->APBBMASK.reg |= PM_APBBMASK_USB; @@ -89,7 +90,7 @@ void UHD_Init(void) * Put Generic Clock Generator 0 as source for Generic Clock Multiplexer 6 (USB reference) */ -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) GCLK->PCHCTRL[USB_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK1_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); #else GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(6) | // Generic Clock Multiplexer 6 @@ -116,7 +117,7 @@ void UHD_Init(void) /* Load Pad Calibration */ -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) pad_transn = (*((uint32_t *)(NVMCTRL_SW0) // Non-Volatile Memory Controller #else pad_transn = (*((uint32_t *)(NVMCTRL_OTP4) // Non-Volatile Memory Controller @@ -133,7 +134,7 @@ void UHD_Init(void) USB->HOST.PADCAL.bit.TRANSN = pad_transn; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) pad_transp = (*((uint32_t *)(NVMCTRL_SW0) #else pad_transp = (*((uint32_t *)(NVMCTRL_OTP4) @@ -149,7 +150,7 @@ void UHD_Init(void) USB->HOST.PADCAL.bit.TRANSP = pad_transp; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) pad_trim = (*((uint32_t *)(NVMCTRL_SW0) #else pad_trim = (*((uint32_t *)(NVMCTRL_OTP4) @@ -189,7 +190,7 @@ void UHD_Init(void) USB->HOST.CTRLB.bit.VBUSOK = 1; // Configure interrupts -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) NVIC_SetPriority((IRQn_Type)USB_0_IRQn, 0UL); NVIC_SetPriority((IRQn_Type)USB_1_IRQn, 0UL); NVIC_SetPriority((IRQn_Type)USB_2_IRQn, 0UL); diff --git a/cores/arduino/WInterrupts.c b/cores/arduino/WInterrupts.c index 85b744673..536b42dc4 100644 --- a/cores/arduino/WInterrupts.c +++ b/cores/arduino/WInterrupts.c @@ -34,7 +34,7 @@ static void __initialize() memset(ISRcallback, 0, sizeof(ISRcallback)); nints = 0; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) ///EIC MCLK is enabled by default for (uint32_t i = 0; i <= 15; i++) // EIC_0_IRQn = 12 ... EIC_15_IRQn = 27 { @@ -63,7 +63,7 @@ static void __initialize() */ // Enable EIC -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) EIC->CTRLA.bit.ENABLE = 1; while (EIC->SYNCBUSY.bit.ENABLE == 1) { } #else @@ -95,7 +95,7 @@ void attachInterrupt(uint32_t pin, voidFuncPtr callback, uint32_t mode) } uint32_t inMask = (1UL << in); // Enable wakeup capability on pin in case being used during sleep - #if defined(__SAMD51__) + #if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) //I believe this is done automatically #else EIC->WAKEUP.reg |= (1 << in); @@ -164,7 +164,7 @@ void attachInterrupt(uint32_t pin, voidFuncPtr callback, uint32_t mode) pos = in << 2; } - #if defined (__SAMD51__) + #if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) EIC->CTRLA.bit.ENABLE = 0; while (EIC->SYNCBUSY.bit.ENABLE == 1) { } #endif @@ -197,7 +197,7 @@ void attachInterrupt(uint32_t pin, voidFuncPtr callback, uint32_t mode) EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << in); } - #if defined (__SAMD51__) + #if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) EIC->CTRLA.bit.ENABLE = 1; while (EIC->SYNCBUSY.bit.ENABLE == 1) { } #endif @@ -221,7 +221,7 @@ void detachInterrupt(uint32_t pin) EIC->INTENCLR.reg = EIC_INTENCLR_EXTINT(1 << in); // Disable wakeup capability on pin during sleep -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) //I believe this is done automatically #else // Disable wakeup capability on pin during sleep @@ -249,7 +249,7 @@ void detachInterrupt(uint32_t pin) /* * External Interrupt Controller NVIC Interrupt Handler */ -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) void InterruptHandler(uint32_t unused_i) { (void)unused_i; diff --git a/cores/arduino/WVariant.h b/cores/arduino/WVariant.h index cb7202d84..aaaae3971 100644 --- a/cores/arduino/WVariant.h +++ b/cores/arduino/WVariant.h @@ -39,13 +39,13 @@ typedef enum _EAnalogChannel ADC_Channel5=5, ADC_Channel6=6, ADC_Channel7=7, -#if defined __SAMD21J18A__ || defined(__SAMD51__) +#if defined __SAMD21J18A__ || defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) ADC_Channel8=8, ADC_Channel9=9, #endif // __SAMD21J18A__ ADC_Channel10=10, ADC_Channel11=11, -#if defined __SAMD21J18A__ || defined(__SAMD51__) +#if defined __SAMD21J18A__ || defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) ADC_Channel12=12, ADC_Channel13=13, ADC_Channel14=14, @@ -61,7 +61,14 @@ typedef enum _EAnalogChannel ADC_Channel_PTAT=0x1C, } EAnalogChannel ; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) + +#ifndef TC_INST_NUM + #define TC_INST_NUM 8 +#endif +#ifndef TCC_INST_NUM + #define TCC_INST_NUM 5 +#endif #if defined(__SAMD51G19A__) || defined(__SAME51G19A__) @@ -307,7 +314,7 @@ typedef enum _EPioType PIO_SERCOM_ALT, /* The pin is controlled by the associated signal of peripheral D. */ PIO_TIMER, /* The pin is controlled by the associated signal of peripheral E. */ PIO_TIMER_ALT, /* The pin is controlled by the associated signal of peripheral F. */ -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) PIO_TCC_PDEC, /* The pin is controlled by the associated signal of peripheral G. */ PIO_COM, /* The pin is controlled by the associated signal of peripheral H. */ PIO_SDHC, /* The pin is controlled by the associated signal of peripheral I. */ @@ -341,7 +348,7 @@ typedef enum _EPioType #define PIN_ATTR_EXTINT (1UL<<6) #define PIN_ATTR_ANALOG_ALT (1UL<<7) -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) // these correspond to the mux table #define PIN_ATTR_PWM_E (1UL<<3) #define PIN_ATTR_PWM_F (1UL<<8) diff --git a/cores/arduino/avr/io.h b/cores/arduino/avr/io.h index 5c395fd26..0fb218abc 100644 --- a/cores/arduino/avr/io.h +++ b/cores/arduino/avr/io.h @@ -25,7 +25,7 @@ #ifndef _IO_H_ #define _IO_H_ -#ifdef __SAMD51__ +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) #define RAMSTART (HSRAM_ADDR) #define RAMSIZE (HSRAM_SIZE) #else diff --git a/cores/arduino/cortex_handlers.c b/cores/arduino/cortex_handlers.c index 953d1a6e1..179976a87 100644 --- a/cores/arduino/cortex_handlers.c +++ b/cores/arduino/cortex_handlers.c @@ -18,6 +18,7 @@ */ #include +#include "same5x_compat_shim.h" #include #include @@ -25,6 +26,7 @@ extern void svcHook(void); extern void pendSVHook(void); extern int sysTickHook(void); +extern void SystemInit(void); /* Default empty handler */ void Dummy_Handler(void) @@ -35,7 +37,7 @@ void Dummy_Handler(void) for (;;) { } } -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) /* Cortex-M4 processor handlers */ void Reset_Handler ( void ); @@ -486,7 +488,7 @@ void Reset_Handler(void) *pDest = 0; } -#if defined(__FPU_USED) && defined(__SAMD51__) +#if defined(__FPU_USED) && (defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__)) /* Enable FPU */ SCB->CPACR |= (0xFu << 20); __DSB(); @@ -513,7 +515,7 @@ void SysTick_Handler(void) static void (*usb_isr)(void) = NULL; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) void USB_0_Handler(void) { if (usb_isr) diff --git a/cores/arduino/delay.c b/cores/arduino/delay.c index 773ce39e9..7530230af 100644 --- a/cores/arduino/delay.c +++ b/cores/arduino/delay.c @@ -61,7 +61,7 @@ unsigned long micros( void ) // a runtime multiplication and shift, saving a few cycles } -#ifdef __SAMD51__ +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) /* * On SAMD51, use the (32bit) cycle count maintained by the DWT unit, * and count exact number of cycles elapsed, rather than guessing how diff --git a/cores/arduino/delay.h b/cores/arduino/delay.h index 3d3a6d195..644ac0230 100644 --- a/cores/arduino/delay.h +++ b/cores/arduino/delay.h @@ -61,7 +61,7 @@ extern void delay( unsigned long dwMs ) ; * * \param dwUs the number of microseconds to pause (uint32_t) */ -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) extern void delayMicroseconds( unsigned int ); #else static __inline__ void delayMicroseconds( unsigned int ) __attribute__((always_inline, unused)) ; diff --git a/cores/arduino/pulse.c b/cores/arduino/pulse.c index 6ead704dd..c921120f3 100644 --- a/cores/arduino/pulse.c +++ b/cores/arduino/pulse.c @@ -34,7 +34,7 @@ uint32_t pulseIn(uint32_t pin, uint32_t state, uint32_t timeout) uint32_t bit = 1 << p.ulPin; uint32_t stateMask = state ? bit : 0; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) /* * The SAMD51 is fast enough to use really obvious code (similar to * what was used to produce pulse_asm.S, but using micros() for timing. @@ -80,4 +80,3 @@ uint32_t pulseIn(uint32_t pin, uint32_t state, uint32_t timeout) return 0; #endif // SAMD51 } - diff --git a/cores/arduino/same5x_compat_shim.h b/cores/arduino/same5x_compat_shim.h new file mode 100644 index 000000000..af3f5bd39 --- /dev/null +++ b/cores/arduino/same5x_compat_shim.h @@ -0,0 +1,254 @@ +#pragma once + +#if defined(__GNUC__) +#pragma GCC system_header +#endif + +#if defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) + +#include "sam.h" + +#ifndef _Ul +#define _Ul(x) x##U +#endif + +#ifndef SIMIO_SAME5X_COMPAT_ROREG8 +#define SIMIO_SAME5X_COMPAT_ROREG8 1 +typedef volatile const uint8_t RoReg8; +#endif + +#if !defined(NVMCTRL_SW0) && defined(SW0_ADDR) +#define NVMCTRL_SW0 SW0_ADDR +#elif !defined(NVMCTRL_SW0) && defined(SW0_FUSES_BASE_ADDRESS) +#define NVMCTRL_SW0 SW0_FUSES_BASE_ADDRESS +#endif + +#if !defined(NVMCTRL_TEMP_LOG) && defined(TEMP_LOG_ADDR) +#define NVMCTRL_TEMP_LOG TEMP_LOG_ADDR +#elif !defined(NVMCTRL_TEMP_LOG) && defined(TEMP_LOG_FUSES_BASE_ADDRESS) +#define NVMCTRL_TEMP_LOG TEMP_LOG_FUSES_BASE_ADDRESS +#endif + +#if defined(__has_include) +#if __has_include("samd51/include/component/sercom.h") +#include "samd51/include/component/sercom.h" +#include "samd51/include/component/usb.h" +#include "samd51/include/component/port.h" +#include "samd51/include/component/gclk.h" +#include "samd51/include/component/mclk.h" +#include "samd51/include/component/tc.h" +#include "samd51/include/component/tcc.h" +#include "samd51/include/component/nvmctrl.h" +#include "samd51/include/component/dmac.h" +#include "samd51/include/component/eic.h" +#include "samd51/include/component/osc32kctrl.h" +#include "samd51/include/component/oscctrl.h" +#include "samd51/include/component/adc.h" +#include "samd51/include/component/dac.h" +#include "samd51/include/component/supc.h" +#include "samd51/include/component/ac.h" +#include "samd51/include/component/cmcc.h" +#else +#error "SAME5x compatibility shim requires CMSIS-Atmel SAMD51 component headers on the include path." +#endif +#else +#include "samd51/include/component/sercom.h" +#include "samd51/include/component/usb.h" +#include "samd51/include/component/port.h" +#include "samd51/include/component/gclk.h" +#include "samd51/include/component/mclk.h" +#include "samd51/include/component/tc.h" +#include "samd51/include/component/tcc.h" +#include "samd51/include/component/nvmctrl.h" +#include "samd51/include/component/dmac.h" +#include "samd51/include/component/eic.h" +#include "samd51/include/component/osc32kctrl.h" +#include "samd51/include/component/oscctrl.h" +#include "samd51/include/component/adc.h" +#include "samd51/include/component/dac.h" +#include "samd51/include/component/supc.h" +#include "samd51/include/component/ac.h" +#include "samd51/include/component/cmcc.h" +#endif + +#if !defined(GCLK) && defined(GCLK_REGS) +#define GCLK ((Gclk *)GCLK_REGS) +#endif +#if !defined(MCLK) && defined(MCLK_REGS) +#define MCLK ((Mclk *)MCLK_REGS) +#endif +#if !defined(PORT) && defined(PORT_REGS) +#define PORT ((Port *)PORT_REGS) +#endif +#if !defined(USB) && defined(USB_REGS) +#define USB ((Usb *)USB_REGS) +#endif +#if !defined(EIC) && defined(EIC_REGS) +#define EIC ((Eic *)EIC_REGS) +#endif +#if !defined(DMAC) && defined(DMAC_REGS) +#define DMAC ((Dmac *)DMAC_REGS) +#endif +#if !defined(NVMCTRL) && defined(NVMCTRL_REGS) +#define NVMCTRL ((Nvmctrl *)NVMCTRL_REGS) +#endif +#if !defined(OSC32KCTRL) && defined(OSC32KCTRL_REGS) +#define OSC32KCTRL ((Osc32kctrl *)OSC32KCTRL_REGS) +#endif +#if !defined(OSCCTRL) && defined(OSCCTRL_REGS) +#define OSCCTRL ((Oscctrl *)OSCCTRL_REGS) +#endif +#if !defined(ADC0) && defined(ADC0_REGS) +#define ADC0 ((Adc *)ADC0_REGS) +#endif +#if !defined(ADC1) && defined(ADC1_REGS) +#define ADC1 ((Adc *)ADC1_REGS) +#endif +#if !defined(DAC) && defined(DAC_REGS) +#define DAC ((Dac *)DAC_REGS) +#endif +#if !defined(SUPC) && defined(SUPC_REGS) +#define SUPC ((Supc *)SUPC_REGS) +#endif +#if !defined(AC) && defined(AC_REGS) +#define AC ((Ac *)AC_REGS) +#endif +#if !defined(CMCC) && defined(CMCC_REGS) +#define CMCC ((Cmcc *)CMCC_REGS) +#endif + +#if !defined(SERCOM0) && defined(SERCOM0_REGS) +#define SERCOM0 ((Sercom *)SERCOM0_REGS) +#endif +#if !defined(SERCOM1) && defined(SERCOM1_REGS) +#define SERCOM1 ((Sercom *)SERCOM1_REGS) +#endif +#if !defined(SERCOM2) && defined(SERCOM2_REGS) +#define SERCOM2 ((Sercom *)SERCOM2_REGS) +#endif +#if !defined(SERCOM3) && defined(SERCOM3_REGS) +#define SERCOM3 ((Sercom *)SERCOM3_REGS) +#endif +#if !defined(SERCOM4) && defined(SERCOM4_REGS) +#define SERCOM4 ((Sercom *)SERCOM4_REGS) +#endif +#if !defined(SERCOM5) && defined(SERCOM5_REGS) +#define SERCOM5 ((Sercom *)SERCOM5_REGS) +#endif +#if !defined(SERCOM6) && defined(SERCOM6_REGS) +#define SERCOM6 ((Sercom *)SERCOM6_REGS) +#endif +#if !defined(SERCOM7) && defined(SERCOM7_REGS) +#define SERCOM7 ((Sercom *)SERCOM7_REGS) +#endif + +#if !defined(TC0) && defined(TC0_REGS) +#define TC0 ((Tc *)TC0_REGS) +#endif +#if !defined(TC1) && defined(TC1_REGS) +#define TC1 ((Tc *)TC1_REGS) +#endif +#if !defined(TC2) && defined(TC2_REGS) +#define TC2 ((Tc *)TC2_REGS) +#endif +#if !defined(TC3) && defined(TC3_REGS) +#define TC3 ((Tc *)TC3_REGS) +#endif +#if !defined(TC4) && defined(TC4_REGS) +#define TC4 ((Tc *)TC4_REGS) +#endif +#if !defined(TC5) && defined(TC5_REGS) +#define TC5 ((Tc *)TC5_REGS) +#endif +#if !defined(TC6) && defined(TC6_REGS) +#define TC6 ((Tc *)TC6_REGS) +#endif +#if !defined(TC7) && defined(TC7_REGS) +#define TC7 ((Tc *)TC7_REGS) +#endif + +#if !defined(TCC0) && defined(TCC0_REGS) +#define TCC0 ((Tcc *)TCC0_REGS) +#endif +#if !defined(TCC1) && defined(TCC1_REGS) +#define TCC1 ((Tcc *)TCC1_REGS) +#endif +#if !defined(TCC2) && defined(TCC2_REGS) +#define TCC2 ((Tcc *)TCC2_REGS) +#endif +#if !defined(TCC3) && defined(TCC3_REGS) +#define TCC3 ((Tcc *)TCC3_REGS) +#endif +#if !defined(TCC4) && defined(TCC4_REGS) +#define TCC4 ((Tcc *)TCC4_REGS) +#endif + +#ifndef TC_INST_NUM +#define TC_INST_NUM 8 +#endif +#ifndef TCC_INST_NUM +#define TCC_INST_NUM 5 +#endif +#ifndef SERCOM_INST_NUM +#define SERCOM_INST_NUM 8 +#endif + +#ifndef EIC_IRQn +#define EIC_IRQn EIC_EXTINT_0_IRQn +#endif +#ifndef EIC_0_IRQn +#define EIC_0_IRQn EIC_EXTINT_0_IRQn +#endif +#ifndef USB_0_IRQn +#define USB_0_IRQn USB_OTHER_IRQn +#endif +#ifndef USB_1_IRQn +#define USB_1_IRQn USB_SOF_HSOF_IRQn +#endif +#ifndef USB_2_IRQn +#define USB_2_IRQn USB_TRCPT0_IRQn +#endif +#ifndef USB_3_IRQn +#define USB_3_IRQn USB_TRCPT1_IRQn +#endif +#ifndef ADC0_0_IRQn +#define ADC0_0_IRQn ADC0_OTHER_IRQn +#endif +#ifndef ADC0_1_IRQn +#define ADC0_1_IRQn ADC0_RESRDY_IRQn +#endif +#ifndef ADC1_0_IRQn +#define ADC1_0_IRQn ADC1_OTHER_IRQn +#endif +#ifndef ADC1_1_IRQn +#define ADC1_1_IRQn ADC1_RESRDY_IRQn +#endif +#ifndef DMAC_4_IRQn +#define DMAC_4_IRQn DMAC_3_IRQn +#endif +#ifndef SERCOM0_3_IRQn +#define SERCOM0_3_IRQn SERCOM0_2_IRQn +#endif +#ifndef SERCOM1_3_IRQn +#define SERCOM1_3_IRQn SERCOM1_2_IRQn +#endif +#ifndef SERCOM2_3_IRQn +#define SERCOM2_3_IRQn SERCOM2_2_IRQn +#endif +#ifndef SERCOM3_3_IRQn +#define SERCOM3_3_IRQn SERCOM3_2_IRQn +#endif +#ifndef SERCOM4_3_IRQn +#define SERCOM4_3_IRQn SERCOM4_2_IRQn +#endif +#ifndef SERCOM5_3_IRQn +#define SERCOM5_3_IRQn SERCOM5_2_IRQn +#endif +#ifndef SERCOM6_3_IRQn +#define SERCOM6_3_IRQn SERCOM6_2_IRQn +#endif +#ifndef SERCOM7_3_IRQn +#define SERCOM7_3_IRQn SERCOM7_2_IRQn +#endif + +#endif diff --git a/cores/arduino/startup.c b/cores/arduino/startup.c index 676844091..e68b8ac59 100644 --- a/cores/arduino/startup.c +++ b/cores/arduino/startup.c @@ -18,6 +18,7 @@ */ #include "sam.h" +#include "same5x_compat_shim.h" #include "variant.h" #include @@ -25,7 +26,7 @@ // Constants for Clock generators #define GENERIC_CLOCK_GENERATOR_MAIN (0u) -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) #define GENERIC_CLOCK_GENERATOR_XOSC32K (3u) #define GENERIC_CLOCK_GENERATOR_48M (1u) #define GENERIC_CLOCK_GENERATOR_48M_SYNC GCLK_SYNCBUSY_GENCTRL1 @@ -55,7 +56,7 @@ void SystemInit( void ) { //***************** SAMD51 ************************// -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) NVMCTRL->CTRLA.reg |= NVMCTRL_CTRLA_RWS(0); #ifndef CRYSTALLESS diff --git a/cores/arduino/wiring.c b/cores/arduino/wiring.c index ad6c7982d..328a4e83d 100644 --- a/cores/arduino/wiring.c +++ b/cores/arduino/wiring.c @@ -24,7 +24,7 @@ extern "C" { #endif -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) uint32_t SystemCoreClock=F_CPU; #else /* @@ -77,7 +77,7 @@ void init( void ) // // Clock EIC for I/O interrupts // PM->APBAMASK.reg |= PM_APBAMASK_EIC ; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) MCLK->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0 | MCLK_APBAMASK_SERCOM1 | MCLK_APBAMASK_TC0 | MCLK_APBAMASK_TC1; MCLK->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2 | MCLK_APBBMASK_SERCOM3 | MCLK_APBBMASK_TCC0 | MCLK_APBBMASK_TCC1 | MCLK_APBBMASK_TC3 | MCLK_APBBMASK_TC2; @@ -114,7 +114,7 @@ void init( void ) // Initialize Analog Controller // Setting clock -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) //set to 1/(1/(48000000/32) * 6) = 250000 SPS GCLK->PCHCTRL[ADC0_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK1_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); //use clock generator 1 (48Mhz) GCLK->PCHCTRL[ADC1_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK1_Val | (1 << GCLK_PCHCTRL_CHEN_Pos); //use clock generator 1 (48Mhz) diff --git a/cores/arduino/wiring_analog.c b/cores/arduino/wiring_analog.c index 40f5a6424..af7fd769a 100644 --- a/cores/arduino/wiring_analog.c +++ b/cores/arduino/wiring_analog.c @@ -27,7 +27,7 @@ extern "C" { static int _readResolution = 10; static int _ADCResolution = 10; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) static int _writeResolution = 12; static int _dacResolution = 12; #else @@ -36,7 +36,7 @@ static int _writeResolution = 8; #endif -#if !defined(__SAMD51__) +#if !(defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__)) // Wait for synchronization of registers between the clock domains static __inline__ void syncADC() __attribute__((always_inline, unused)); static void syncADC() { @@ -73,7 +73,7 @@ static bool dacEnabled[2]; void analogReadResolution(int res) { _readResolution = res; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) if (res > 10) { ADC0->CTRLB.bit.RESSEL = ADC_CTRLB_RESSEL_12BIT_Val; @@ -133,7 +133,7 @@ static inline uint32_t mapResolution(uint32_t value, uint32_t from, uint32_t to) */ void analogReference(eAnalogReference mode) { -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) while(ADC0->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL); //wait for sync while(ADC1->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL); //wait for sync @@ -279,7 +279,7 @@ uint32_t analogRead(uint32_t pin) //ATSAMR, for example, doesn't have a DAC #ifdef DAC - #if defined(__SAMD51__) + #if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) if (pin == PIN_DAC0 || pin == PIN_DAC1) { // Disable DAC, if analogWrite(A0,dval) used previously the DAC is enabled uint8_t channel = (pin == PIN_DAC0 ? 0 : 1); @@ -309,7 +309,7 @@ uint32_t analogRead(uint32_t pin) #endif -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) Adc *adc; if(g_APinDescription[pin].ulPinAttribute & PIN_ATTR_ANALOG) adc = ADC0; else if(g_APinDescription[pin].ulPinAttribute & PIN_ATTR_ANALOG_ALT) adc = ADC1; @@ -412,13 +412,13 @@ void analogWrite(uint32_t pin, uint32_t value) if ((attr & PIN_ATTR_ANALOG) == PIN_ATTR_ANALOG) { // DAC handling code -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) if (pin == PIN_DAC0 || pin == PIN_DAC1) { // 2 DACs on A0 (PA02) and A1 (PA05) #else if (pin == PIN_DAC0) { // Only 1 DAC on A0 (PA02) #endif -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) value = mapResolution(value, _writeResolution, _dacResolution); @@ -480,13 +480,13 @@ void analogWrite(uint32_t pin, uint32_t value) syncDAC(); DAC->CTRLA.bit.ENABLE = 0x01; // Enable DAC syncDAC(); -#endif // __SAMD51__ +#endif // SAMD51/SAME5x return; } } #endif // DAC -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) if(attr & (PIN_ATTR_PWM_E|PIN_ATTR_PWM_F|PIN_ATTR_PWM_G)){ uint32_t tcNum = GetTCNumber(pinDesc.ulPWMChannel); diff --git a/cores/arduino/wiring_private.c b/cores/arduino/wiring_private.c index 954f854af..6be6d76a7 100644 --- a/cores/arduino/wiring_private.c +++ b/cores/arduino/wiring_private.c @@ -68,7 +68,7 @@ int pinPeripheral( uint32_t ulPin, EPioType ulPeripheral ) case PIO_TIMER: case PIO_TIMER_ALT: case PIO_EXTINT: -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) case PIO_TCC_PDEC: case PIO_COM: case PIO_SDHC: @@ -127,4 +127,3 @@ int pinPeripheral( uint32_t ulPin, EPioType ulPeripheral ) return 0l ; } - diff --git a/libraries/I2S/src/I2S.cpp b/libraries/I2S/src/I2S.cpp index 00837e202..f636582f6 100644 --- a/libraries/I2S/src/I2S.cpp +++ b/libraries/I2S/src/I2S.cpp @@ -21,7 +21,7 @@ #include "utility/DMA.h" -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) #include "utility/SAMD51_I2SDevice.h" @@ -115,7 +115,7 @@ int I2SClass::begin(int mode, long sampleRate, int bitsPerSample, bool driveCloc if (_beginCount == 0) { // enable the I2S interface -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) MCLK->APBDMASK.reg |= MCLK_APBDMASK_I2S; #else PM->APBCMASK.reg |= PM_APBCMASK_I2S; @@ -197,7 +197,7 @@ void I2SClass::end() i2sd.disable(); // disable the I2S interface -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) MCLK->APBDMASK.reg &= ~(MCLK_APBDMASK_I2S); #else PM->APBCMASK.reg &= ~PM_APBCMASK_I2S; diff --git a/libraries/I2S/src/utility/DMA.cpp b/libraries/I2S/src/utility/DMA.cpp index 45b166650..953e097df 100644 --- a/libraries/I2S/src/utility/DMA.cpp +++ b/libraries/I2S/src/utility/DMA.cpp @@ -40,7 +40,7 @@ void DMAClass::begin() { if (_beginCount == 0) { -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) MCLK->AHBMASK.bit.DMAC_ = 1; #else // enable the DMA interface @@ -62,7 +62,7 @@ void DMAClass::begin() DMAC->CTRL.bit.LVLEN3 = 1; DMAC->CTRL.bit.DMAENABLE = 1; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) NVIC_DisableIRQ(DMAC_0_IRQn); NVIC_ClearPendingIRQ(DMAC_0_IRQn); NVIC_EnableIRQ(DMAC_0_IRQn); @@ -102,7 +102,7 @@ void DMAClass::end() if (_beginCount == 0) { // disable the interrupt -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) NVIC_DisableIRQ(DMAC_0_IRQn); NVIC_DisableIRQ(DMAC_1_IRQn); NVIC_DisableIRQ(DMAC_2_IRQn); @@ -116,7 +116,7 @@ void DMAClass::end() DMAC->CTRL.bit.DMAENABLE = 0; // disable the DMA interface -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) MCLK->AHBMASK.bit.DMAC_ = 0; #else // enable the DMA interface @@ -140,7 +140,7 @@ int DMAClass::allocateChannel() memset((void*)&_descriptors[i], 0x00, sizeof(_descriptors[i])); // select the channel and reset it -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) DMAC->Channel[i].CHCTRLA.bit.ENABLE = 0; DMAC->Channel[i].CHCTRLA.bit.SWRST = 1; #else @@ -160,7 +160,7 @@ int DMAClass::allocateChannel() void DMAClass::freeChannel(int channel) { // select the channel and disable it -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) DMAC->Channel[channel].CHCTRLA.bit.ENABLE = 0; #else DMAC->CHID.bit.ID = channel; @@ -173,7 +173,7 @@ void DMAClass::freeChannel(int channel) void DMAClass::setPriorityLevel(int channel, int level) { // select the channel and set priority level -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) DMAC->Channel[channel].CHPRILVL.reg = level; #else @@ -184,7 +184,7 @@ void DMAClass::setPriorityLevel(int channel, int level) void DMAClass::setTriggerSource(int channel, int source) { -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) DMAC->Channel[channel].CHCTRLA.bit.TRIGSRC = source; DMAC->Channel[channel].CHCTRLA.bit.TRIGACT = DMAC_CHCTRLA_TRIGACT_BLOCK_Val; #else @@ -242,7 +242,7 @@ int DMAClass::transfer(int channel, void* src, void* dst, uint16_t size) } -#if !defined(__SAMD51__) +#if !(defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__)) // select the channel DMAC->CHID.bit.ID = channel; #endif @@ -289,7 +289,7 @@ int DMAClass::transfer(int channel, void* src, void* dst, uint16_t size) // validate the descriptor _descriptors[channel].BTCTRL.bit.VALID = 1; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) DMAC->Channel[channel].CHINTENSET.bit.TERR = 1; DMAC->Channel[channel].CHINTENSET.bit.TCMPL = 1; DMAC->Channel[channel].CHCTRLA.bit.ENABLE = 1; @@ -327,14 +327,14 @@ void DMAClass::onService() { // get the channel and select it int channel = DMAC->INTPEND.bit.ID; -#if !defined(__SAMD51__) +#if !(defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__)) DMAC->CHID.bit.ID = channel; #endif // invalidate the channel _descriptors[channel].BTCTRL.bit.VALID = 0; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) if (DMAC->Channel[channel].CHINTFLAG.bit.TERR) { // clear the error interrupt and call the error callback if there is one DMAC->Channel[channel].CHINTFLAG.bit.TERR = 1; @@ -374,7 +374,7 @@ void DMAClass::onService() } extern "C" { -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) static void _dmac_handler(void) { DMA.onService(); diff --git a/libraries/I2S/src/utility/DMA.h b/libraries/I2S/src/utility/DMA.h index 4368eeae1..71c9aab6a 100644 --- a/libraries/I2S/src/utility/DMA.h +++ b/libraries/I2S/src/utility/DMA.h @@ -17,7 +17,7 @@ */ #pragma once -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) #define NUM_DMA_CHANNELS 4 #else #define NUM_DMA_CHANNELS 1 diff --git a/libraries/SAMD_AnalogCorrection/src/SAMD_AnalogCorrection.cpp b/libraries/SAMD_AnalogCorrection/src/SAMD_AnalogCorrection.cpp index e39ab43e3..d153107b5 100644 --- a/libraries/SAMD_AnalogCorrection/src/SAMD_AnalogCorrection.cpp +++ b/libraries/SAMD_AnalogCorrection/src/SAMD_AnalogCorrection.cpp @@ -27,7 +27,7 @@ void analogReadCorrection (int offset, uint16_t gain) { Adc *adc; -#if defined (__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) adc = ADC0; #else adc = ADC; @@ -39,10 +39,9 @@ adc = ADC; // Enable digital correction logic adc->CTRLB.bit.CORREN = 1; -#if defined (__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) while(adc->SYNCBUSY.bit.OFFSETCORR || adc->SYNCBUSY.bit.GAINCORR); #else while(adc->STATUS.bit.SYNCBUSY); #endif } - diff --git a/libraries/SPI/SPI.cpp b/libraries/SPI/SPI.cpp index 0393752d7..62e6c321f 100644 --- a/libraries/SPI/SPI.cpp +++ b/libraries/SPI/SPI.cpp @@ -278,7 +278,7 @@ void SPIClass::dmaAllocate(void) { // aren't large and there's usually only a handful to a dozen, so this // isn't an excessive burden in exchange for big non-blocking transfers. uint32_t maxWriteBytes = FLASH_SIZE; // Writes can't exceed all of flash -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) uint32_t maxReadBytes = HSRAM_SIZE; // Reads can't exceed all of RAM #else uint32_t maxReadBytes = HMCRAMC0_SIZE; @@ -521,11 +521,11 @@ int SPIClass::getDMAC_ID_RX(void) { return (idx >= 0) ? sercomData[idx].dmac_id_rx : -1; } -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) // Set the SPI device's SERCOM clock CORE and SLOW clock sources. // SercomClockSource values are an enumeration in SERCOM.h. -// This works on SAMD51 only. On SAMD21, a dummy function is declared +// This works on SAMD51/SAME5x only. On SAMD21, a dummy function is declared // in SPI.h which compiles to nothing, so user code doesn't need to check // and conditionally compile lines for different architectures. void SPIClass::setClockSource(SercomClockSource clk) { @@ -534,7 +534,7 @@ void SPIClass::setClockSource(SercomClockSource clk) { _p_sercom->setClockSource(idx, clk, false); // false = set slow clock } -#endif // end __SAMD51__ +#endif // end SAMD51/SAME5x #if SPI_INTERFACES_COUNT > 0 /* In case new variant doesn't define these macros, diff --git a/libraries/SPI/SPI.h b/libraries/SPI/SPI.h index 7c719f695..fd05c538a 100644 --- a/libraries/SPI/SPI.h +++ b/libraries/SPI/SPI.h @@ -38,7 +38,7 @@ #define SPI_MODE2 0x03 #define SPI_MODE3 0x01 -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) // SAMD51 has configurable MAX_SPI, else use peripheral clock default. // Update: changing MAX_SPI via compiler flags is DEPRECATED, because // this affects ALL SPI peripherals including some that should NOT be @@ -80,7 +80,7 @@ class SPISettings { } void init_AlwaysInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) __attribute__((__always_inline__)) { -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) this->clockFreq = clock; // Clipping handled in SERCOM.cpp #else this->clockFreq = clock >= MAX_SPI ? MAX_SPI : clock; @@ -144,14 +144,14 @@ class SPIClass { int getDMAC_ID_TX(void); int getDMAC_ID_RX(void); uint8_t getSercomIndex(void) { return _p_sercom->getSercomIndex(); }; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) // SERCOM clock source override is available only on SAMD51. void setClockSource(SercomClockSource clk); #else // On SAMD21, this compiles to nothing, so user code doesn't need to // check and conditionally compile lines for different architectures. void setClockSource(SercomClockSource clk) { (void)clk; }; -#endif // end __SAMD51__ +#endif // end SAMD51/SAME5x private: void config(SPISettings settings); diff --git a/libraries/Servo/src/samd/Servo.cpp b/libraries/Servo/src/samd/Servo.cpp index ba07e70a7..75d86e83b 100644 --- a/libraries/Servo/src/samd/Servo.cpp +++ b/libraries/Servo/src/samd/Servo.cpp @@ -26,7 +26,7 @@ #include #endif -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) // Different prescalers depending on FCPU (avoid overflowing 16-bit counter) #if(F_CPU > 200000000) #define usToTicks(_us) ((clockCyclesPerMicrosecond() * _us) / 128) @@ -78,7 +78,7 @@ void Servo_Handler(timer16_Sequence_t timer, Tc *tc, uint8_t channel, uint8_t in { if (currentServoIndex[timer] < 0) { tc->COUNT16.COUNT.reg = (uint16_t) 0; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) while(tc->COUNT16.SYNCBUSY.bit.COUNT); #else WAIT_TC16_REGS_SYNC(tc) @@ -98,7 +98,7 @@ void Servo_Handler(timer16_Sequence_t timer, Tc *tc, uint8_t channel, uint8_t in } // Get the counter value -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) // Note from datasheet: Prior to any read access, this register must be synchronized by user by writing the according TC // Command value to the Control B Set register (CTRLBSET.CMD=READSYNC) while (tc->COUNT16.SYNCBUSY.bit.CTRLB); @@ -106,14 +106,14 @@ void Servo_Handler(timer16_Sequence_t timer, Tc *tc, uint8_t channel, uint8_t in while (tc->COUNT16.SYNCBUSY.bit.CTRLB); #endif uint16_t tcCounterValue = tc->COUNT16.COUNT.reg; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) while(tc->COUNT16.SYNCBUSY.bit.COUNT); #else WAIT_TC16_REGS_SYNC(tc) #endif tc->COUNT16.CC[channel].reg = (uint16_t) (tcCounterValue + SERVO(timer, currentServoIndex[timer]).ticks); -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) if(channel == 0) { while(tc->COUNT16.SYNCBUSY.bit.CC0); } else if(channel == 1) { @@ -128,7 +128,7 @@ void Servo_Handler(timer16_Sequence_t timer, Tc *tc, uint8_t channel, uint8_t in // Get the counter value uint16_t tcCounterValue = tc->COUNT16.COUNT.reg; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) while(tc->COUNT16.SYNCBUSY.bit.COUNT); #else WAIT_TC16_REGS_SYNC(tc) @@ -140,7 +140,7 @@ void Servo_Handler(timer16_Sequence_t timer, Tc *tc, uint8_t channel, uint8_t in else { tc->COUNT16.CC[channel].reg = (uint16_t) (tcCounterValue + 4UL); // at least REFRESH_INTERVAL has elapsed } -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) if(channel == 0) { while(tc->COUNT16.SYNCBUSY.bit.CC0); } else if(channel == 1) { @@ -161,7 +161,7 @@ static inline void resetTC (Tc* TCx) { // Disable TCx TCx->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) while(TCx->COUNT16.SYNCBUSY.bit.ENABLE); #else WAIT_TC16_REGS_SYNC(TCx) @@ -169,7 +169,7 @@ static inline void resetTC (Tc* TCx) // Reset TCx TCx->COUNT16.CTRLA.reg = TC_CTRLA_SWRST; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) while(TCx->COUNT16.SYNCBUSY.bit.SWRST); #else WAIT_TC16_REGS_SYNC(TCx) @@ -181,7 +181,7 @@ static void _initISR(Tc *tc, uint8_t channel, uint32_t id, IRQn_Type irqn, uint8 { (void)id; // Select GCLK0 as timer/counter input clock source -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) int idx = gcmForTimer; // see datasheet Table 14-9 GCLK->PCHCTRL[idx].bit.GEN = 0; // Select GCLK0 as periph clock source GCLK->PCHCTRL[idx].bit.CHEN = 1; // Enable peripheral @@ -198,7 +198,7 @@ static void _initISR(Tc *tc, uint8_t channel, uint32_t id, IRQn_Type irqn, uint8 // Set timer counter mode to 16 bits tc->COUNT16.CTRLA.reg |= TC_CTRLA_MODE_COUNT16; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) // Set timer counter mode as normal PWM tc->COUNT16.WAVE.bit.WAVEGEN = TCC_WAVE_WAVEGEN_NPWM_Val; @@ -220,7 +220,7 @@ static void _initISR(Tc *tc, uint8_t channel, uint32_t id, IRQn_Type irqn, uint8 // Count up tc->COUNT16.CTRLBCLR.bit.DIR = 1; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) while(tc->COUNT16.SYNCBUSY.bit.CTRLB); #else WAIT_TC16_REGS_SYNC(tc) @@ -228,7 +228,7 @@ static void _initISR(Tc *tc, uint8_t channel, uint32_t id, IRQn_Type irqn, uint8 // First interrupt request after 1 ms tc->COUNT16.CC[channel].reg = (uint16_t) usToTicks(1000UL); -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) if(channel == 0) { while(tc->COUNT16.SYNCBUSY.bit.CC0); } else if(channel == 1) { @@ -250,7 +250,7 @@ static void _initISR(Tc *tc, uint8_t channel, uint32_t id, IRQn_Type irqn, uint8 // Enable the timer and start it tc->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) while(tc->COUNT16.SYNCBUSY.bit.ENABLE); #else WAIT_TC16_REGS_SYNC(tc) diff --git a/libraries/Servo/src/samd/ServoTimers.h b/libraries/Servo/src/samd/ServoTimers.h index c4da50694..9257c6898 100644 --- a/libraries/Servo/src/samd/ServoTimers.h +++ b/libraries/Servo/src/samd/ServoTimers.h @@ -37,7 +37,7 @@ //#define _useTimer2 // <- TODO do not activate until the code in Servo.cpp has been changed in order // to manage more than one channel per timer on the SAMD architecture -#if defined(__SAMD51__) +#if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) #if defined (_useTimer1) #define TC_FOR_TIMER1 TC1 #define CHANNEL_FOR_TIMER1 0 diff --git a/libraries/Wire/Wire.cpp b/libraries/Wire/Wire.cpp index da9732c59..ab97cb3a5 100644 --- a/libraries/Wire/Wire.cpp +++ b/libraries/Wire/Wire.cpp @@ -293,12 +293,12 @@ void TwoWire::onService(void) Wire.onService(); } - #if defined(__SAMD51__) + #if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) void WIRE_IT_HANDLER_0(void) { Wire.onService(); } void WIRE_IT_HANDLER_1(void) { Wire.onService(); } void WIRE_IT_HANDLER_2(void) { Wire.onService(); } void WIRE_IT_HANDLER_3(void) { Wire.onService(); } - #endif // __SAMD51__ + #endif // SAMD51/SAME5x #endif #if WIRE_INTERFACES_COUNT > 1 @@ -308,12 +308,12 @@ void TwoWire::onService(void) Wire1.onService(); } - #if defined(__SAMD51__) + #if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) void WIRE1_IT_HANDLER_0(void) { Wire1.onService(); } void WIRE1_IT_HANDLER_1(void) { Wire1.onService(); } void WIRE1_IT_HANDLER_2(void) { Wire1.onService(); } void WIRE1_IT_HANDLER_3(void) { Wire1.onService(); } - #endif // __SAMD51__ + #endif // SAMD51/SAME5x #endif #if WIRE_INTERFACES_COUNT > 2 @@ -323,12 +323,12 @@ void TwoWire::onService(void) Wire2.onService(); } - #if defined(__SAMD51__) + #if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) void WIRE2_IT_HANDLER_0(void) { Wire2.onService(); } void WIRE2_IT_HANDLER_1(void) { Wire2.onService(); } void WIRE2_IT_HANDLER_2(void) { Wire2.onService(); } void WIRE2_IT_HANDLER_3(void) { Wire2.onService(); } - #endif // __SAMD51__ + #endif // SAMD51/SAME5x #endif #if WIRE_INTERFACES_COUNT > 3 @@ -338,12 +338,12 @@ void TwoWire::onService(void) Wire3.onService(); } - #if defined(__SAMD51__) + #if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) void WIRE3_IT_HANDLER_0(void) { Wire3.onService(); } void WIRE3_IT_HANDLER_1(void) { Wire3.onService(); } void WIRE3_IT_HANDLER_2(void) { Wire3.onService(); } void WIRE3_IT_HANDLER_3(void) { Wire3.onService(); } - #endif // __SAMD51__ + #endif // SAMD51/SAME5x #endif #if WIRE_INTERFACES_COUNT > 4 @@ -353,12 +353,12 @@ void TwoWire::onService(void) Wire4.onService(); } - #if defined(__SAMD51__) + #if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) void WIRE4_IT_HANDLER_0(void) { Wire4.onService(); } void WIRE4_IT_HANDLER_1(void) { Wire4.onService(); } void WIRE4_IT_HANDLER_2(void) { Wire4.onService(); } void WIRE4_IT_HANDLER_3(void) { Wire4.onService(); } - #endif // __SAMD51__ + #endif // SAMD51/SAME5x #endif #if WIRE_INTERFACES_COUNT > 5 @@ -368,11 +368,10 @@ void TwoWire::onService(void) Wire5.onService(); } - #if defined(__SAMD51__) + #if defined(__SAMD51__) || defined(__SAME51__) || defined(__SAME53__) || defined(__SAME54__) void WIRE5_IT_HANDLER_0(void) { Wire5.onService(); } void WIRE5_IT_HANDLER_1(void) { Wire5.onService(); } void WIRE5_IT_HANDLER_2(void) { Wire5.onService(); } void WIRE5_IT_HANDLER_3(void) { Wire5.onService(); } - #endif // __SAMD51__ + #endif // SAMD51/SAME5x #endif -