From f3f375d761481c345190ab49d7ed837c0f4ae8e6 Mon Sep 17 00:00:00 2001 From: AmeNote-Michael Date: Wed, 8 Jul 2026 17:21:18 -0600 Subject: [PATCH 1/3] arm64: dts: mt-connect: fix SAI MCLK direction and add SAI2/SAI3 MCLK pinctrl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All SAI MCLK signals are generated by the Dante Clocking Circuit (SI5351B) and flow into the A53 — none are outputs from the SoC. - Remove fsl,sai-mclk-direction-output from sai1 and sai3: these were incorrectly enabling the SAI MCLK output driver (MOE bit in MCR). For SAI1 the MCLK pad (AB18) is NC so it was harmless; for SAI3 (AD6) it was contending with the SI5351B CLK2 output. - Move SAI3_MCLK (AD6) from pinctrl_gpio5/gpio5grp to pinctrl_sai3/sai3grp using SAI3_MCLK function (ALT0) so the 24.576 MHz Dante MCLK signal is properly routed into the SAI3 peripheral rather than a GPIO register. - Add pinctrl_sai2 and enable &sai2 (no sound card, no data lines) so SAI2_TXFS (AD23) and SAI2_TXC (AD22) are claimed as inputs. These pads are tied to the shared Dante BCLK/LRCLK bus along with SAI1 and SAI3. - Remove now-empty pinctrl_gpio5 group and its reference from &gpio5. Co-Authored-By: Claude Sonnet 4.6 --- arch/arm64/boot/dts/freescale/mt-connect.dts | 29 +++++++++++++------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/mt-connect.dts b/arch/arm64/boot/dts/freescale/mt-connect.dts index 49b02c88cba9d..e3c3a8c0bfeae 100644 --- a/arch/arm64/boot/dts/freescale/mt-connect.dts +++ b/arch/arm64/boot/dts/freescale/mt-connect.dts @@ -439,8 +439,6 @@ }; &gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio5>; gpio-line-names = "DPM_HP_DAC_BCLK", "DPM_HP_DAC_SD", "DPM_HP_DAC_MCLK", "", "", "PWM_MEMBRANE", "", "", "", "", "SPI2_SCK", "SPI2_MOSI", "SPI2_MISO", "SPI2_NSS", "", "", "DPM_I2C2_SCL", "DPM_I2C2_SDA", "", "", "DPM_I2C4_SCL", "DPM_I2C4_SDA", "", "", @@ -466,7 +464,6 @@ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; fsl,dataline = <1 0x00 0x01>; /*I2S mode enabled, 0 RX lines, 1 TX lines*/ fsl,txs-rxs; - fsl,sai-mclk-direction-output; status = "okay"; }; @@ -480,7 +477,18 @@ fsl,dataline = <1 0x0F 0x0F>; /*I2S mode enabled, 4 RX lines, 4 TX lines*/ fsl,txs-rxs; fsl,sai-multi-lane; - fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* SAI2 TXFS/TXC share the Dante clock bus with SAI1 and SAI3; no data lines used. */ +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + clocks = <&clk IMX8MM_CLK_SAI2_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&dante_osc_mclk>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + fsl,txs-rxs; status = "okay"; }; @@ -688,12 +696,19 @@ >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x80 /* Dante LRCLK shared bus */ + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x80 /* Dante BCLK shared bus */ + >; + }; pinctrl_sai3: sai3grp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x80 /* DANTE_OSC_SCLK */ MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 /* DPM_HP_DAC_SD */ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x80 /* DPM_HP_DAC_LRCK */ + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x80 /* DANTE_OSC_MCLK input */ >; }; @@ -704,12 +719,6 @@ >; }; - pinctrl_gpio5: gpio5grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x80 /* DANTE_OSC_MCLK */ - >; - }; - pinctrl_typec1: typec1grp { fsl,pins = < MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 From c3540d2eeff85aec2a08cda4ed0839321e6e286e Mon Sep 17 00:00:00 2001 From: AmeNote-Michael Date: Wed, 8 Jul 2026 18:29:44 -0600 Subject: [PATCH 2/3] arm64: dts: mt-connect: add fsl,dataline to sai2 to fix probe crash Without fsl,dataline, fsl_sai_read_dlcfg computes num_cfg=0 and calls devm_kzalloc(0) which returns ZERO_SIZE_PTR (0x10) instead of NULL. The plain !cfg guard passes, and the immediate cfg[0].type = FSL_SAI_DL_DEFAULT write faults at address 0x10. Add fsl,dataline = <1 0x00 0x00> to declare zero RX and TX data lines, giving the allocator a non-zero size. Co-Authored-By: Claude Sonnet 4.6 --- arch/arm64/boot/dts/freescale/mt-connect.dts | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/mt-connect.dts b/arch/arm64/boot/dts/freescale/mt-connect.dts index e3c3a8c0bfeae..e682b4c0920c9 100644 --- a/arch/arm64/boot/dts/freescale/mt-connect.dts +++ b/arch/arm64/boot/dts/freescale/mt-connect.dts @@ -480,7 +480,12 @@ status = "okay"; }; -/* SAI2 TXFS/TXC share the Dante clock bus with SAI1 and SAI3; no data lines used. */ +/* + * SAI2 TXFS/TXC share the Dante clock bus with SAI1 and SAI3; no data lines + * are used. fsl,dataline must be present even with zero lanes — without it + * fsl_sai_read_dlcfg calls devm_kzalloc(0) which returns ZERO_SIZE_PTR and + * immediately crashes on the first cfg[0] write. + */ &sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2>; @@ -488,6 +493,7 @@ <&dante_osc_mclk>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + fsl,dataline = <1 0x00 0x00>; /* no RX or TX data lines */ fsl,txs-rxs; status = "okay"; }; From f0b6626431a7cfd088508b8a234e8154ac70b982 Mon Sep 17 00:00:00 2001 From: Michael Loh <90074657+AmeNote-Michael@users.noreply.github.com> Date: Wed, 8 Jul 2026 22:58:07 -0600 Subject: [PATCH 3/3] Potential fix for pull request finding Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com> --- arch/arm64/boot/dts/freescale/mt-connect.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/mt-connect.dts b/arch/arm64/boot/dts/freescale/mt-connect.dts index e682b4c0920c9..c56236f14e9f2 100644 --- a/arch/arm64/boot/dts/freescale/mt-connect.dts +++ b/arch/arm64/boot/dts/freescale/mt-connect.dts @@ -482,7 +482,7 @@ /* * SAI2 TXFS/TXC share the Dante clock bus with SAI1 and SAI3; no data lines - * are used. fsl,dataline must be present even with zero lanes — without it + * are used. fsl,dataline must be present even with zero lanes -- without it * fsl_sai_read_dlcfg calls devm_kzalloc(0) which returns ZERO_SIZE_PTR and * immediately crashes on the first cfg[0] write. */