From f006492046ce282710e14581030cd8038cbc9fdf Mon Sep 17 00:00:00 2001 From: wanghengZzz Date: Thu, 30 Jul 2026 14:18:00 +0800 Subject: [PATCH 1/2] rtos: Add explanatory comment for portFPU_REG_OFFSET in RISC-V port Explain that the initial (2 * portWORD_SIZE) offset reserves space for the fcsr register and maintains proper memory and ABI stack alignment for both RV32 and RV64 architectures. --- portable/GCC/RISC-V/portContext.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/portable/GCC/RISC-V/portContext.h b/portable/GCC/RISC-V/portContext.h index 0869a82b6ce..eb3bed2fe40 100644 --- a/portable/GCC/RISC-V/portContext.h +++ b/portable/GCC/RISC-V/portContext.h @@ -91,6 +91,13 @@ #define portFPU_REG_SIZE ( __riscv_flen / 8 ) #define portFPU_REG_COUNT 33 /* 32 Floating point registers plus one CSR. */ + + /* + * Reserve space at the beginning of the FPU context block for: + * 1. The FCSR (Floating-Point Control and Status Register). + * 2. Padding to ensure proper memory/stack alignment (8-byte alignment for + * RV32D, and 16-byte stack alignment mandated by the RISC-V ABI for RV64). + */ #define portFPU_REG_OFFSET( regIndex ) ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) ) #define portFPU_CONTEXT_SIZE ( portFPU_REG_SIZE * portFPU_REG_COUNT ) #else From ee4636fa663bd8b20d516b8cc0543ecc68ea1010 Mon Sep 17 00:00:00 2001 From: wanghengZzz Date: Fri, 31 Jul 2026 09:59:58 +0800 Subject: [PATCH 2/2] comment: clarify FPU context offset calculation in RISC-V portContext.h --- portable/GCC/RISC-V/portContext.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/portable/GCC/RISC-V/portContext.h b/portable/GCC/RISC-V/portContext.h index eb3bed2fe40..9da2b45b69e 100644 --- a/portable/GCC/RISC-V/portContext.h +++ b/portable/GCC/RISC-V/portContext.h @@ -94,9 +94,10 @@ /* * Reserve space at the beginning of the FPU context block for: - * 1. The FCSR (Floating-Point Control and Status Register). - * 2. Padding to ensure proper memory/stack alignment (8-byte alignment for - * RV32D, and 16-byte stack alignment mandated by the RISC-V ABI for RV64). + * 1. The FCSR (one portWORD_SIZE slot). + * 2. Padding (one portWORD_SIZE slot) to align the FP registers: + * - RV32: 8-byte boundary for double-precision registers. + * - RV64: 16-byte boundary mandated by the RISC-V ABI. */ #define portFPU_REG_OFFSET( regIndex ) ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) ) #define portFPU_CONTEXT_SIZE ( portFPU_REG_SIZE * portFPU_REG_COUNT )