From e2dfdcbac9f16a22a8b206ceab812eca93bd5afa Mon Sep 17 00:00:00 2001
From: Mausam5055
Date: Mon, 1 Jun 2026 21:23:01 +0530
Subject: [PATCH 01/19] Update README.md
---
README.md | 647 ++++++++++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 599 insertions(+), 48 deletions(-)
diff --git a/README.md b/README.md
index 62b294793..819cd389a 100644
--- a/README.md
+++ b/README.md
@@ -1,61 +1,612 @@
-
-
-
-[](https://www.python.org/dev/peps/pep-0008/)
-
-[](https://esim.readthedocs.io/en/latest/?badge=latest)
-[](https://github.com/fossee/esim/network)
-[](https://github.com/fossee/esim)
-
-
-## eSim
-
-[eSim](https://esim.fossee.in/) is an open source EDA tool for circuit design, simulation, analysis and PCB design, developed by [FOSSEE Team](https://www.fossee.in/) at [IIT Bombay](https://www.iitb.ac.in/).
-It is an integrated tool build using open source softwares such as KiCad, Ngspice and GHDL.
-
-## Releases and Installation
-eSim is released for the following distributions (operating systems):
-* **All Linux distributions** (Fedora, Ubuntu, openSUSE, Arch, etc.) via Flatpak
-* Ubuntu 22.04, 23.04, 24.04 LTS versions (native installer)
-* Microsoft Windows 8, 10 and 11
-
-**For Fedora and other Linux distributions:** Use the Flatpak method for easy installation:
+
+
+
+
+
eSim — Electronic Circuit Simulation
+
+
+ An Open-Source EDA Tool for Circuit Design, Simulation, Analysis & PCB Design
+ Developed by FOSSEE Team at IIT Bombay
+
-## eSim Manual
-To know everything about eSim, how it works and it's feature please download the manual from [here](https://static.fossee.in/esim/manuals/eSim_Manual_2.5.pdf)
+
+
+---
+
+## 📞 Contact & Support
+
+| Channel | Link |
+|:--------|:-----|
+| 📧 **Email** | [contact-esim@fossee.in](mailto:contact-esim@fossee.in) |
+| 🌐 **Website** | [esim.fossee.in](https://esim.fossee.in/) |
+| 💬 **Forum** | [forums.fossee.in](https://forums.fossee.in/) |
+| 📞 **Contact Page** | [esim.fossee.in/contact-us](https://esim.fossee.in/contact-us) |
+| 📄 **User Manual** | [eSim Manual v2.5 (PDF)](https://static.fossee.in/esim/manuals/eSim_Manual_2.5.pdf) |
+| 📚 **Developer Docs** | [esim.readthedocs.io](https://esim.readthedocs.io/en/latest/) |
+
+---
+
+## 🔒 Security
+
+For information on reporting security vulnerabilities, please see [SECURITY.md](SECURITY.md).
+
+---
+
+## 📄 License
+
+eSim is released under the **GNU General Public License v3.0** — see the [LICENSE](LICENSE) file for details.
+
+```
+Copyright (C) FOSSEE, IIT Bombay
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 3 of the License, or
+(at your option) any later version.
+```
-## Contact
-For any queries regarding eSim please write us on at this [email address](mailto:contact-esim@fossee.in).
+---
-Other Contact Details are available [here](https://esim.fossee.in/contact-us).
+
+ Auto-generated via contrib.rocks — shows GitHub avatar for every contributor
+
+
+---
+
+
+ Thank you to every single contributor who has made eSim possible! ❤️
+ This file is maintained alongside the project. If your contribution is missing, please open an issue.
+
+ 📋 View the full Contributors page →
+ Complete list with profiles, commit counts, and contribution tiers for all 149+ contributors
+
---
From 18e2eada77535afc63d1c95ceb8380c8dab2056d Mon Sep 17 00:00:00 2001
From: Mausam5055
Date: Mon, 1 Jun 2026 21:38:20 +0530
Subject: [PATCH 04/19] commit
---
CONTRIBUTING.md | 249 +++++++++++++++++++++++++++++++++
CONTRIBUTION.md | 24 ----
CONTRIBUTORS.md | 364 ------------------------------------------------
3 files changed, 249 insertions(+), 388 deletions(-)
create mode 100644 CONTRIBUTING.md
delete mode 100644 CONTRIBUTION.md
delete mode 100644 CONTRIBUTORS.md
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
new file mode 100644
index 000000000..4dc1f4459
--- /dev/null
+++ b/CONTRIBUTING.md
@@ -0,0 +1,249 @@
+# Contributing to eSim
+
+Thank you for your interest in contributing to **eSim**! 🎉
+Every contribution — whether it's a bug fix, new feature, documentation improvement, or example circuit — helps make eSim better for everyone.
+
+
+
+
+
+
+
+---
+
+## 📋 Table of Contents
+
+- [Getting Started](#-getting-started)
+- [Ways to Contribute](#-ways-to-contribute)
+- [Development Setup](#-development-setup)
+- [Pull Request Workflow](#-pull-request-workflow)
+- [Commit Guidelines](#-commit-guidelines)
+- [Code Style](#-code-style)
+- [Reporting Bugs](#-reporting-bugs)
+- [Requesting Features](#-requesting-features)
+- [Community](#-community)
+
+---
+
+## 🚀 Getting Started
+
+1. **Find an issue** — Browse the [issue tracker](https://github.com/fossee/esim/issues) for bugs or features you'd like to work on
+2. **Claim it** — Comment on the issue with *"I would like to work on this"* so maintainers can assign it to you
+3. **Fork & code** — Follow the [Pull Request Workflow](#-pull-request-workflow) below
+4. **Submit a PR** — Every pull request **must reference an issue**
+
+> **💡 First-time contributor?** Look for issues labeled [`good first issue`](https://github.com/fossee/esim/labels/good%20first%20issue) — these are beginner-friendly tasks curated by maintainers.
+
+---
+
+## 🤝 Ways to Contribute
+
+| Type | Description | Difficulty |
+|:-----|:------------|:----------:|
+| 🐛 **Bug Fixes** | Fix reported issues from the [issue tracker](https://github.com/fossee/esim/issues) | ⭐ – ⭐⭐ |
+| ✨ **New Features** | Implement new functionality or enhance existing modules | ⭐⭐ – ⭐⭐⭐ |
+| 📝 **Documentation** | Improve docs, docstrings, README, or Sphinx docs in `docs/` | ⭐ |
+| 🧪 **Testing** | Add test cases or report bugs with reproducible steps | ⭐ – ⭐⭐ |
+| 🎨 **UI/UX** | Improve the PyQt6 user interface and user experience | ⭐⭐ |
+| 📚 **Examples** | Add new example circuits to the `Examples/` directory | ⭐ |
+| 📦 **Packaging** | Help with Flatpak, Snap, AppImage, or Docker builds | ⭐⭐⭐ |
+| 🌐 **Integration** | Improve KiCad, Ngspice, GHDL, or Makerchip integration | ⭐⭐⭐ |
+
+---
+
+## 🔧 Development Setup
+
+### Prerequisites
+
+| Tool | Version | Purpose |
+|:-----|:--------|:--------|
+| Python | 3.6+ | Core application runtime |
+| PyQt6 | ≥ 6.5.0 | GUI framework |
+| KiCad | Latest | Schematic & PCB editor |
+| Ngspice | 35+ | Circuit simulation engine |
+| Git | Latest | Version control |
+
+### Setup Steps
+
+```bash
+# 1. Fork the repository on GitHub, then clone your fork
+git clone https://github.com//eSim.git
+cd eSim
+
+# 2. Install Python dependencies
+pip install -r requirements.txt
+
+# 3. (Optional) Install additional tools for full functionality
+# See INSTALL file for KiCad, Ngspice, and GHDL setup
+```
+
+---
+
+## 📬 Pull Request Workflow
+
+```mermaid
+flowchart LR
+ A["🍴 Fork"] --> B["🌿 Branch"]
+ B --> C["💻 Code"]
+ C --> D["✅ Commit"]
+ D --> E["⬆️ Push"]
+ E --> F["📬 PR"]
+
+ style A fill:#6c5ce7,color:#fff
+ style B fill:#00b894,color:#fff
+ style C fill:#0984e3,color:#fff
+ style D fill:#fdcb6e,color:#333
+ style E fill:#e17055,color:#fff
+ style F fill:#d63031,color:#fff
+```
+
+### Step-by-Step
+
+**1. Fork & Clone**
+
+```bash
+# Fork via GitHub UI, then:
+git clone https://github.com//eSim.git
+cd eSim
+```
+
+**2. Create a Feature Branch**
+
+```bash
+# Always branch from master — never commit directly to master
+git checkout -b fix/issue-42-rectifier-bug
+```
+
+> **Branch naming convention:**
+> - `fix/issue--short-description` — for bug fixes
+> - `feature/issue--short-description` — for new features
+> - `docs/short-description` — for documentation changes
+
+**3. Make Your Changes**
+
+- Write clean, well-commented code
+- Follow the [Code Style](#-code-style) guidelines
+- Test your changes locally
+
+**4. Commit Your Changes**
+
+```bash
+git add
+git commit -m "Fixes issue #42 - Fix half-wave rectifier simulation error"
+```
+
+> ⚠️ **One commit per pull request.** If you have multiple commits, squash them before submitting.
+
+**5. Push & Open a PR**
+
+```bash
+git push origin fix/issue-42-rectifier-bug
+```
+
+Then open a Pull Request on GitHub targeting the `master` branch.
+
+---
+
+## 📝 Commit Guidelines
+
+### Commit Message Format
+
+```
+Fixes issue # -
+
+
+- What was the problem?
+- What did you change?
+- Why this approach?
+```
+
+### Examples
+
+```
+Fixes issue #42 - Fix AC analysis crash when frequency range is empty
+
+The AC analysis module threw an unhandled exception when the user
+left the frequency range fields blank. Added input validation in
+Analysis.py to show an error dialog instead of crashing.
+```
+
+```
+Fixes issue #87 - Add 4-bit counter example circuit
+
+Added a new example project under Examples/4_bit_counter with
+schematic, netlist, and simulation configuration files.
+```
+
+### Rules
+
+| Rule | Details |
+|:-----|:--------|
+| **Reference an issue** | Every PR must link to an existing GitHub issue |
+| **One commit per PR** | Squash multiple commits before submitting |
+| **Clear subject line** | Format: `Fixes issue #N - Brief description` |
+| **Add a body** | Explain *what* you changed and *why* |
+
+---
+
+## 🎨 Code Style
+
+eSim follows **[PEP 8](https://www.python.org/dev/peps/pep-0008/)** — the Python community's style guide.
+
+| Rule | Details |
+|:-----|:--------|
+| **Style** | PEP 8 compliant |
+| **Indentation** | 4 spaces (no tabs) |
+| **Line length** | Max 79 characters |
+| **Docstrings** | Required for all public functions and classes |
+| **Imports** | Group by stdlib → third-party → local; one per line |
+| **Naming** | `snake_case` for functions/variables, `PascalCase` for classes |
+
+### Linting
+
+```bash
+# Check your code before submitting
+flake8 src/
+```
+
+---
+
+## 🐛 Reporting Bugs
+
+Found a bug? Please [open an issue](https://github.com/fossee/esim/issues/new) with:
+
+1. **Title** — Clear, concise summary of the problem
+2. **Environment** — OS, Python version, eSim version
+3. **Steps to reproduce** — Exact steps to trigger the bug
+4. **Expected behavior** — What should happen
+5. **Actual behavior** — What actually happens
+6. **Screenshots/Logs** — If applicable, attach console output or screenshots
+
+---
+
+## 💡 Requesting Features
+
+Have an idea for a new feature? [Open an issue](https://github.com/fossee/esim/issues/new) with:
+
+1. **Title** — Prefix with `[Feature Request]`
+2. **Problem** — What problem does this solve?
+3. **Proposed solution** — How should it work?
+4. **Alternatives considered** — Any other approaches you thought of?
+5. **Additional context** — Mockups, references, or related issues
+
+---
+
+## 💬 Community
+
+| Channel | Link |
+|:--------|:-----|
+| 📧 **Email** | [contact-esim@fossee.in](mailto:contact-esim@fossee.in) |
+| 💬 **Forum** | [forums.fossee.in](https://forums.fossee.in/) |
+| 🌐 **Website** | [esim.fossee.in](https://esim.fossee.in/) |
+| 📚 **Dev Docs** | [esim.readthedocs.io](https://esim.readthedocs.io/en/latest/) |
+
+---
+
+
+ Thank you for contributing to eSim! ❤️
+ Every contribution, no matter how small, makes a difference.
+
diff --git a/CONTRIBUTION.md b/CONTRIBUTION.md
deleted file mode 100644
index ce6338b78..000000000
--- a/CONTRIBUTION.md
+++ /dev/null
@@ -1,24 +0,0 @@
-## Contribution
-If you want to add any enhancement feature or have found any bug and want to work on it, please open a new issue regarding that and put a message "I would like to work on it." And make sure every pull request should reference to an issue.
-
-#### Points on how to make pull request
-* You need to fork this repository to your account.
-
-* Clone it using ``` git clone https://github.com/FOSSEE/eSim.git ```
-
-* Always create a new branch before making any changes. You can create new branch using ```git branch ```
-
-* Checkout into your new branch using ```git checkout ```
-
-* Make changes to code and once you are done use ```git add ```. Now commit changes with proper message using ```git commit -m "Your message"```.
-
-* After commiting your changes push your changes to your forked repository using ```git push origin ```
-Finally create a pull request from github.
-There should be only one commit per pull request.
-
-
-* Please follow below guidelines for your commit message :
- * Commit message should be like : Fixes issue #[issue_number] - one line message of work you did.
- * After commit message, there should be a commit body where you can mention what you did in short or in detail.
-
-Please follow above method to file pull requests.
diff --git a/CONTRIBUTORS.md b/CONTRIBUTORS.md
deleted file mode 100644
index edc788eb8..000000000
--- a/CONTRIBUTORS.md
+++ /dev/null
@@ -1,364 +0,0 @@
-
-
-
-
-
🏆 eSim Contributors
-
-
- Honoring the people who built eSim — since February 2015
- An open-source EDA tool by FOSSEE at IIT Bombay
-
-
-
-
-
-
-
-
-
----
-
-eSim is built by a vibrant community of **149+ contributors** — students, researchers, engineers, and open-source enthusiasts from around the world. This page recognizes everyone who has contributed code, documentation, bug fixes, and features to the project since its first commit on **February 5, 2015**.
-
----
-
-## 🏛️ Project Leads & Organization
-
-| Role | Name | Affiliation |
-|:-----|:-----|:------------|
-| **Developed by** | [FOSSEE Team](https://www.fossee.in/) | IIT Bombay |
-| **Original Author** | Fahim Khan | eSim / FOSSEE, IIT Bombay |
-| **Lead Maintainer** | Sumanto Kar | FOSSEE, IIT Bombay |
-| **Core Maintainer** | Rahul Paknikar | FOSSEE, IIT Bombay |
-| **Core Maintainer** | Pranav P | FOSSEE, IIT Bombay |
-
----
-
-## 🥇 Core Maintainers
-
-These individuals have made sustained, foundational contributions to eSim's architecture, features, and long-term maintenance.
-
-
- Auto-generated via contrib.rocks — shows GitHub avatar for every contributor
-
-
----
-
-
- Thank you to every single contributor who has made eSim possible! ❤️
- This file is maintained alongside the project. If your contribution is missing, please open an issue.
-
-
-
-
-
-
-
From d6c7cf8902c11f76e72e9c08def28f2742354965 Mon Sep 17 00:00:00 2001
From: Mausam5055
Date: Mon, 1 Jun 2026 21:38:38 +0530
Subject: [PATCH 05/19] Update README.md
---
README.md | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/README.md b/README.md
index 9ef2c689b..25713fe99 100644
--- a/README.md
+++ b/README.md
@@ -523,7 +523,7 @@ flowchart LR
> - Follow [PEP 8](https://www.python.org/dev/peps/pep-0008/) code style
> - Include a commit body describing what you changed and why
-For detailed contribution guidelines, see [CONTRIBUTION.md](CONTRIBUTION.md).
+For detailed contribution guidelines, see [CONTRIBUTING.md](CONTRIBUTING.md).
---
@@ -542,10 +542,7 @@ A huge thank you to all **149+ amazing people** who have contributed to eSim!
-
- 📋 View the full Contributors page →
- Complete list with profiles, commit counts, and contribution tiers for all 149+ contributors
-
### 🥈 Major Contributors (20+ commits)
@@ -255,21 +277,6 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015!
---
-## 📋 Table of Contents
-
-- [Our Contributors](#-our-contributors)
-- [Getting Started](#-getting-started)
-- [Ways to Contribute](#-ways-to-contribute)
-- [Development Setup](#-development-setup)
-- [Pull Request Workflow](#-pull-request-workflow)
-- [Commit Guidelines](#-commit-guidelines)
-- [Code Style](#-code-style)
-- [Reporting Bugs](#-reporting-bugs)
-- [Requesting Features](#-requesting-features)
-- [Community](#-community)
-
----
-
## 🚀 Getting Started
1. **Find an issue** — Browse the [issue tracker](https://github.com/fossee/esim/issues) for bugs or features you'd like to work on
diff --git a/README.md b/README.md
index 38d930d34..adaef1ccc 100644
--- a/README.md
+++ b/README.md
@@ -531,26 +531,33 @@ For detailed contribution guidelines, see [CONTRIBUTING.md](CONTRIBUTING.md).
A huge thank you to all **149+ amazing people** who have contributed to eSim! 🎉
-
### 🌟 Community Contributors
@@ -267,15 +172,108 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015!
-### All Contributors Mosaic
+### 🥉 Active Contributors (10–19 commits)
-
+
---
## 🚀 Getting Started
From 88cfe9c4f5241c02ae9c2d6d9adfdd0030b52bdd Mon Sep 17 00:00:00 2001
From: Mausam5055
Date: Mon, 1 Jun 2026 22:02:40 +0530
Subject: [PATCH 12/19] Update README.md
---
README.md | 235 ++++++++++++++++++++++++++++++------------------------
1 file changed, 133 insertions(+), 102 deletions(-)
diff --git a/README.md b/README.md
index 48dff84fb..13e22e36e 100644
--- a/README.md
+++ b/README.md
@@ -38,7 +38,7 @@
---
-## 📖 About
+## About
**eSim** is a free and open-source EDA (Electronic Design Automation) tool for circuit design, simulation, analysis, and PCB design. It is an integrated tool built using open-source software such as **KiCad**, **Ngspice**, **GHDL**, and **Makerchip**, providing a seamless workflow from schematic capture to simulation results.
@@ -48,130 +48,161 @@ eSim is designed for electronics engineers, students, educators, and hobbyists w
---
-## ✨ Features
+## Features
| Category | Feature | Description |
|:---------|:--------|:------------|
-| 🎨 **Design** | Schematic Capture | Draw circuit schematics using KiCad's schematic editor with eSim's custom symbol libraries |
-| 🔄 **Conversion** | KiCad to Ngspice | Convert KiCad schematics to Ngspice-compatible netlists for simulation |
-| ⚡ **Simulation** | Ngspice Engine | Run DC, AC, Transient, and other SPICE analyses with real-time interactive plots |
-| 📊 **Analysis** | Waveform Plotting | Visualize simulation results with matplotlib-based Python plots and Ngspice native plots |
-| 🔧 **Model Editor** | Device Models | Create and edit SPICE device models (Diodes, BJTs, MOSFETs, JFETs, IGBTs, etc.) |
-| 🧩 **Subcircuits** | Subcircuit Builder | Build, manage, and upload reusable subcircuit blocks |
-| 🖥️ **Mixed-Signal** | NGHDL Integration | Interface VHDL digital models (via GHDL) with analog Ngspice simulations |
-| 🌐 **Verilog** | Makerchip + NgVeri | Use Makerchip IDE for Verilog/TL-Verilog design and convert to Ngspice models |
-| 🏭 **PCB** | Layout Design | Design PCB layouts using KiCad's PCB editor with eSim's footprint libraries |
-| 🔁 **Converters** | Schematic Import | Convert PSpice and LTSpice schematics/libraries to KiCad-compatible formats |
-| 📐 **Modelica** | Ngspice-to-Modelica | Convert Ngspice netlists to Modelica models for OpenModelica simulation |
-| 🏗️ **SKY130 PDK** | SkyWater 130nm | Support for SkyWater SKY130 open-source Process Design Kit |
-| 🔬 **IHP PDK** | IHP OpenPDK | Integration with IHP SG13G2 open-source PDK for SiGe BiCMOS |
+| • **Design** | Schematic Capture | Draw circuit schematics using KiCad's schematic editor with eSim's custom symbol libraries |
+| • **Conversion** | KiCad to Ngspice | Convert KiCad schematics to Ngspice-compatible netlists for simulation |
+| • **Simulation** | Ngspice Engine | Run DC, AC, Transient, and other SPICE analyses with real-time interactive plots |
+| • **Analysis** | Waveform Plotting | Visualize simulation results with matplotlib-based Python plots and Ngspice native plots |
+| • **Model Editor** | Device Models | Create and edit SPICE device models (Diodes, BJTs, MOSFETs, JFETs, IGBTs, etc.) |
+| • **Subcircuits** | Subcircuit Builder | Build, manage, and upload reusable subcircuit blocks |
+| • **Mixed-Signal** | NGHDL Integration | Interface VHDL digital models (via GHDL) with analog Ngspice simulations |
+| • **Verilog** | Makerchip + NgVeri | Use Makerchip IDE for Verilog/TL-Verilog design and convert to Ngspice models |
+| • **PCB** | Layout Design | Design PCB layouts using KiCad's PCB editor with eSim's footprint libraries |
+| • **Converters** | Schematic Import | Convert PSpice and LTSpice schematics/libraries to KiCad-compatible formats |
+| • **Modelica** | Ngspice-to-Modelica | Convert Ngspice netlists to Modelica models for OpenModelica simulation |
+| • **SKY130 PDK** | SkyWater 130nm | Support for SkyWater SKY130 open-source Process Design Kit |
+| • **IHP PDK** | IHP OpenPDK | Integration with IHP SG13G2 open-source PDK for SiGe BiCMOS |
---
-## 🏗️ Architecture
+## Architecture
### High-Level System Architecture
```mermaid
graph TB
- subgraph USER["👤 User Interface Layer"]
- APP["Application.py Main Window (PyQt6)"]
- PE["ProjectExplorer File Browser"]
- DA["DockArea Tabbed Workspace"]
- TE["TimeExplorer Snapshot Manager"]
- CON["Console Log Output"]
+ %% Styling
+ classDef ui fill:#2A3F54,stroke:#1ABB9C,stroke-width:2px,color:#fff
+ classDef core fill:#3E536C,stroke:#3498DB,stroke-width:2px,color:#fff
+ classDef engine fill:#1F2D3D,stroke:#E74C3C,stroke-width:2px,color:#fff
+ classDef data fill:#E9F0F5,stroke:#95A5A6,stroke-width:1px,color:#333
+
+ subgraph UI ["User Interface (PyQt6)"]
+ A[Application Main Window]:::ui
+ PE[Project Explorer]:::ui
+ DA[Dock Area Workspace]:::ui
+ TE[Time Explorer]:::ui
+ CON[Console Widget]:::ui
+
+ A --> PE & DA & TE & CON
end
- subgraph CORE["⚙️ Core Engine Layer"]
- KNG["KiCad-to-Ngspice Converter"]
- SIM["Ngspice Simulation Engine"]
- PLT["Plot Window matplotlib"]
- ME["Model Editor"]
- SC["Subcircuit Manager"]
+ subgraph CORE ["Core Python Modules"]
+ K2N[KiCad-to-Ngspice]:::core
+ SIM[Ngspice Simulator]:::core
+ PLT[Matplotlib Plotter]:::core
+ ME[Model Editor]:::core
+ SC[Subcircuit Builder]:::core
+
+ DA --> K2N & SIM & ME & SC
end
- subgraph INTEGRATION["🔌 Integration Layer"]
- NGHDL["NGHDL GHDL Interface"]
- MKR["Makerchip/NgVeri Verilog Models"]
- MOD["Modelica Converter OpenModelica"]
- CONV["Schematic Converters PSpice / LTSpice"]
+ subgraph INTEGRATION ["Mixed-Signal & External APIs"]
+ NGHDL[NGHDL Interface]:::core
+ MKR[Makerchip/NgVeri]:::core
+ MOD[Modelica Converter]:::core
+ CONV[PSpice/LTSpice Converter]:::core
+
+ DA --> NGHDL & MKR & MOD & CONV
end
- subgraph EXTERNAL["📦 External Tools"]
- KICAD["KiCad Schematic + PCB"]
- NGSPICE["Ngspice SPICE Simulator"]
- GHDL["GHDL VHDL Simulator"]
- VERILATOR["Verilator Verilog Simulator"]
- OMEDIT["OpenModelica Modelica IDE"]
+ subgraph ENGINES ["Simulation & EDA Engines"]
+ KICAD[KiCad Eeschema]:::engine
+ PCB[KiCad Pcbnew]:::engine
+ NGSPICE[Ngspice Backend]:::engine
+ GHDL[GHDL Simulator]:::engine
+ VER[Verilator]:::engine
+ OM[OpenModelica]:::engine
end
- APP --> PE
- APP --> DA
- APP --> TE
- APP --> CON
-
- DA --> KNG
- DA --> SIM
- DA --> ME
- DA --> SC
- DA --> NGHDL
- DA --> MKR
- DA --> MOD
- DA --> CONV
-
- KNG --> KICAD
- SIM --> NGSPICE
- SIM --> PLT
- NGHDL --> GHDL
- MKR --> VERILATOR
- MOD --> OMEDIT
-
- style USER fill:#1a1a2e,stroke:#e94560,color:#fff
- style CORE fill:#16213e,stroke:#0f3460,color:#fff
- style INTEGRATION fill:#0f3460,stroke:#533483,color:#fff
- style EXTERNAL fill:#533483,stroke:#e94560,color:#fff
+ %% Data Flow
+ XML[(Netlist / XML)]:::data
+ RAW[(Raw Data / txt)]:::data
+ VHDL[(VHDL Files)]:::data
+
+ K2N -- Generates --> XML
+ XML -- Consumed by --> NGSPICE
+ SIM -- Triggers --> NGSPICE
+ NGSPICE -- Outputs --> RAW
+ RAW -- Parsed by --> PLT
+
+ NGHDL -- Compiles --> VHDL
+ VHDL -- Simulated by --> GHDL
+ GHDL -- Co-simulates --> NGSPICE
+
+ MKR -- Verilog/TL-V --> VER
+
+ KICAD -- Schematic --> K2N
+ KICAD -- Netlist --> PCB
```
### Simulation Workflow
```mermaid
-flowchart LR
- A["📝 Create/Open Project"] --> B["🎨 Draw Schematic KiCad"]
- B --> C["🔄 Convert KiCad → Ngspice"]
- C --> D["⚙️ Configure Analysis & Parameters"]
- D --> E["▶️ Run Simulation Ngspice"]
- E --> F["📊 Plot & Analyze Results"]
-
- style A fill:#6c5ce7,stroke:#a29bfe,color:#fff
- style B fill:#00b894,stroke:#55efc4,color:#fff
- style C fill:#fdcb6e,stroke:#f9ca24,color:#333
- style D fill:#e17055,stroke:#fab1a0,color:#fff
- style E fill:#0984e3,stroke:#74b9ff,color:#fff
- style F fill:#d63031,stroke:#ff7675,color:#fff
+flowchart TD
+ %% Styling
+ classDef startend fill:#2ECC71,stroke:#27AE60,stroke-width:2px,color:#fff
+ classDef process fill:#3498DB,stroke:#2980B9,stroke-width:2px,color:#fff
+ classDef decision fill:#F1C40F,stroke:#F39C12,stroke-width:2px,color:#333
+ classDef io fill:#9B59B6,stroke:#8E44AD,stroke-width:2px,color:#fff
+
+ START([Start eSim Project]):::startend --> CREATE{New or Existing?}:::decision
+ CREATE -- New --> PROJ[Create Project Structure]:::process
+ CREATE -- Existing --> OPEN[Open Project Workspace]:::process
+
+ PROJ --> SCHEM[Draw Schematic in KiCad]:::process
+ OPEN --> SCHEM
+
+ SCHEM --> CHECK{Mixed Signal?}:::decision
+ CHECK -- Yes --> VHDL[Write VHDL/Verilog Models]:::process
+ VHDL --> GHDL[Compile via NGHDL/NgVeri]:::process
+ GHDL --> SYM[Generate KiCad Symbol]:::process
+ SYM --> SCHEM
+
+ CHECK -- No --> K2N[Run KiCad-to-Ngspice]:::process
+ K2N --> PARSE[Parse XML Netlist]:::process
+ PARSE --> SRC[Configure Sources & Analysis]:::process
+ SRC --> DEV[Configure Device Models]:::process
+
+ DEV --> SPICE[Generate .cir SPICE Netlist]:::io
+ SPICE --> NGSPICE[Execute Ngspice Simulation]:::process
+
+ NGSPICE --> OUT{Simulation Success?}:::decision
+ OUT -- No --> ERR[View Error Log & Debug]:::process
+ ERR --> SCHEM
+
+ OUT -- Yes --> RAW[Generate RAW Output Data]:::io
+ RAW --> PLOT[Extract Data for Plotting]:::process
+ PLOT --> MAT[Render matplotlib Waveforms]:::process
+
+ MAT --> END([Analyze Results]):::startend
```
### Mixed-Signal Simulation Flow (NGHDL)
```mermaid
-flowchart TB
- V["📄 Write VHDL Code"] --> U["⬆️ Upload via NGHDL"]
- U --> G["🔧 GHDL Compiles VHDL to Shared Lib"]
- G --> CM["📦 Create Ngspice Code Model"]
- CM --> KS["🎨 Create KiCad Symbol"]
- KS --> SC["📝 Use in Schematic"]
- SC --> SIM["⚡ Mixed-Signal Simulation"]
-
- style V fill:#a29bfe,stroke:#6c5ce7,color:#fff
- style U fill:#74b9ff,stroke:#0984e3,color:#fff
- style G fill:#55efc4,stroke:#00b894,color:#fff
- style CM fill:#ffeaa7,stroke:#fdcb6e,color:#333
- style KS fill:#fab1a0,stroke:#e17055,color:#fff
- style SIM fill:#fd79a8,stroke:#e84393,color:#fff
+flowchart TD
+ %% Styling
+ classDef input fill:#34495E,stroke:#2C3E50,stroke-width:2px,color:#fff
+ classDef process fill:#16A085,stroke:#1ABC9C,stroke-width:2px,color:#fff
+ classDef output fill:#8E44AD,stroke:#9B59B6,stroke-width:2px,color:#fff
+
+ VHDL([Write VHDL/Verilog Code]):::input --> UPLOAD[Upload via NGHDL/NgVeri UI]:::process
+ UPLOAD --> COMPILE[GHDL/Verilator Compiles Code to Shared Lib]:::process
+ COMPILE --> MODEL[Create Ngspice Code Model .cm]:::process
+ MODEL --> KICAD[Generate KiCad Component Symbol]:::output
+
+ KICAD --> SCHEM([Place Symbol in Schematic]):::input
+ SCHEM --> BRIDGE[ADC/DAC Bridge Insertion]:::process
+ BRIDGE --> SIM[Execute Mixed-Signal Co-Simulation]:::output
```
---
-## 📂 Project Structure
+## Project Structure
### Root Directory
@@ -203,7 +234,7 @@ flowchart TB
```
src/
-├── frontEnd/ # 🖥️ GUI & Main Application
+├── frontEnd/ # GUI & Main Application
│ ├── Application.py # Main window, toolbar setup, menu actions (960 lines)
│ ├── DockArea.py # Tabbed dock workspace for editors/simulators (24K)
│ ├── ProjectExplorer.py # File tree browser for project navigation (20K)
@@ -211,7 +242,7 @@ src/
│ ├── TerminalUi.py # Embedded terminal widget (5K)
│ └── Workspace.py # Workspace selection dialog (6K)
│
-├── kicadtoNgspice/ # 🔄 KiCad-to-Ngspice Conversion Engine
+├── kicadtoNgspice/ # KiCad-to-Ngspice Conversion Engine
│ ├── KicadtoNgspice.py # Main conversion controller & UI (41K)
│ ├── Convert.py # Netlist parsing and SPICE generation (40K)
│ ├── Analysis.py # Analysis type configuration (DC, AC, Transient) (32K)
@@ -223,23 +254,23 @@ src/
│ ├── Model.py # Model file handling (6K)
│ └── TrackWidget.py # UI tracking widget (1K)
│
-├── ngspiceSimulation/ # ⚡ Simulation Engine & Plotting
+├── ngspiceSimulation/ # Simulation Engine & Plotting
│ ├── NgspiceWidget.py # Ngspice process management & execution (16K)
│ ├── plot_window.py # matplotlib-based waveform plotter (66K)
│ ├── plotting_widgets.py # Custom plot controls and widgets (8K)
│ └── data_extraction.py # Simulation data file parser (11K)
│
-├── modelEditor/ # 🔧 SPICE Model Editor
+├── modelEditor/ # SPICE Model Editor
│ └── ModelEditor.py # GUI for creating/editing device models (33K)
│
-├── subcircuit/ # 🧩 Subcircuit Management
+├── subcircuit/ # Subcircuit Management
│ ├── Subcircuit.py # Subcircuit manager main window (3K)
│ ├── newSub.py # Create new subcircuit (3K)
│ ├── openSub.py # Open existing subcircuit (1K)
│ ├── uploadSub.py # Upload subcircuit to library (4K)
│ └── convertSub.py # Subcircuit format conversion (2K)
│
-├── maker/ # 🌐 Makerchip & NgVeri Integration
+├── maker/ # Makerchip & NgVeri Integration
│ ├── Maker.py # Makerchip IDE integration (23K)
│ ├── NgVeri.py # Verilog-to-Ngspice model generator (17K)
│ ├── ModelGeneration.py # Auto model generation pipeline (48K)
@@ -247,7 +278,7 @@ src/
│ ├── makerchip.py # Makerchip cloud IDE connector (3K)
│ └── Appconfig.py # Maker-specific configuration (2K)
│
-├── converter/ # 🔁 Schematic Format Converters
+├── converter/ # Schematic Format Converters
│ ├── pspiceToKicad.py # PSpice schematic importer (5K)
│ ├── ltspiceToKicad.py # LTSpice schematic importer (6K)
│ ├── libConverter.py # Library format converter (3K)
@@ -382,7 +413,7 @@ esim
# Or double-click the eSim desktop icon
```
-### 🪟 Windows
+### Windows
1. Download the eSim installer from [esim.fossee.in/downloads](https://esim.fossee.in/downloads)
2. Disable antivirus temporarily (if required)
@@ -478,7 +509,7 @@ eSim ships with **42 ready-to-simulate example projects** in the `Examples/` dir
---
-## 🤝 Contributing
+## Contributing
We welcome contributions from the community! Whether it's bug fixes, new features, documentation improvements, or example circuits — every contribution matters.
@@ -527,7 +558,7 @@ For detailed contribution guidelines, see [CONTRIBUTING.md](CONTRIBUTING.md).
---
-## 👥 Contributors
+## Contributors
A huge thank you to all **149+ amazing people** who have contributed to eSim! 🎉
From e9dc21728ad3e7e6af717927f3811e33ac98a8aa Mon Sep 17 00:00:00 2001
From: Mausam5055
Date: Mon, 1 Jun 2026 22:05:29 +0530
Subject: [PATCH 13/19] architecture
---
ARCHITECTURE.md | 112 ++++++++++++++++++++++++++++++++++++++++++++++++
README.md | 61 +-------------------------
2 files changed, 113 insertions(+), 60 deletions(-)
create mode 100644 ARCHITECTURE.md
diff --git a/ARCHITECTURE.md b/ARCHITECTURE.md
new file mode 100644
index 000000000..418290e5e
--- /dev/null
+++ b/ARCHITECTURE.md
@@ -0,0 +1,112 @@
+# eSim Architecture & Workflows
+
+This document contains detailed flowcharts and diagrams mapping out the inner workings, simulation pipelines, and data transformations within eSim.
+
+---
+
+## 1. Standard Simulation Workflow
+
+This flowchart details the end-to-end user journey for a standard analog/digital simulation in eSim, from project creation to waveform analysis.
+
+```mermaid
+flowchart TD
+ %% Styling
+ classDef startend fill:#2ECC71,stroke:#27AE60,stroke-width:2px,color:#fff
+ classDef process fill:#3498DB,stroke:#2980B9,stroke-width:2px,color:#fff
+ classDef decision fill:#F1C40F,stroke:#F39C12,stroke-width:2px,color:#333
+ classDef io fill:#9B59B6,stroke:#8E44AD,stroke-width:2px,color:#fff
+
+ START([Start eSim Project]):::startend --> CREATE{New or Existing?}:::decision
+ CREATE -- New --> PROJ[Create Project Structure]:::process
+ CREATE -- Existing --> OPEN[Open Project Workspace]:::process
+
+ PROJ --> SCHEM[Draw Schematic in KiCad]:::process
+ OPEN --> SCHEM
+
+ SCHEM --> CHECK{Mixed Signal?}:::decision
+ CHECK -- Yes --> VHDL[Write VHDL/Verilog Models]:::process
+ VHDL --> GHDL[Compile via NGHDL/NgVeri]:::process
+ GHDL --> SYM[Generate KiCad Symbol]:::process
+ SYM --> SCHEM
+
+ CHECK -- No --> K2N[Run KiCad-to-Ngspice]:::process
+ K2N --> PARSE[Parse XML Netlist]:::process
+ PARSE --> SRC[Configure Sources & Analysis]:::process
+ SRC --> DEV[Configure Device Models]:::process
+
+ DEV --> SPICE[Generate .cir SPICE Netlist]:::io
+ SPICE --> NGSPICE[Execute Ngspice Simulation]:::process
+
+ NGSPICE --> OUT{Simulation Success?}:::decision
+ OUT -- No --> ERR[View Error Log & Debug]:::process
+ ERR --> SCHEM
+
+ OUT -- Yes --> RAW[Generate RAW Output Data]:::io
+ RAW --> PLOT[Extract Data for Plotting]:::process
+ PLOT --> MAT[Render matplotlib Waveforms]:::process
+
+ MAT --> END([Analyze Results]):::startend
+```
+
+---
+
+## 2. Mixed-Signal Simulation Flow (NGHDL)
+
+This diagram breaks down how eSim bridges digital logic (VHDL/Verilog) with analog simulation using GHDL and Ngspice code models.
+
+```mermaid
+flowchart TD
+ %% Styling
+ classDef input fill:#34495E,stroke:#2C3E50,stroke-width:2px,color:#fff
+ classDef process fill:#16A085,stroke:#1ABC9C,stroke-width:2px,color:#fff
+ classDef output fill:#8E44AD,stroke:#9B59B6,stroke-width:2px,color:#fff
+
+ VHDL([Write VHDL/Verilog Code]):::input --> UPLOAD[Upload via NGHDL/NgVeri UI]:::process
+ UPLOAD --> COMPILE[GHDL/Verilator Compiles Code to Shared Lib]:::process
+ COMPILE --> MODEL[Create Ngspice Code Model .cm]:::process
+ MODEL --> KICAD[Generate KiCad Component Symbol]:::output
+
+ KICAD --> SCHEM([Place Symbol in Schematic]):::input
+ SCHEM --> BRIDGE[ADC/DAC Bridge Insertion]:::process
+ BRIDGE --> SIM[Execute Mixed-Signal Co-Simulation]:::output
+```
+
+---
+
+## 3. KiCad-to-Ngspice Netlist Conversion
+
+A deep dive into the `Convert.py` backend pipeline, showing how KiCad's XML data is processed into an executable SPICE netlist.
+
+```mermaid
+flowchart TD
+ %% Styling
+ classDef input fill:#34495E,stroke:#2C3E50,stroke-width:2px,color:#fff
+ classDef process fill:#E67E22,stroke:#D35400,stroke-width:2px,color:#fff
+ classDef io fill:#9B59B6,stroke:#8E44AD,stroke-width:2px,color:#fff
+
+ XML([KiCad XML Netlist]):::input --> PARSE[Parse XML DOM]:::process
+ PARSE --> EXTRACT[Extract Components & Connections]:::process
+ EXTRACT --> MAP[Map Pins to Ngspice Nodes]:::process
+ MAP --> SUB[Resolve Subcircuits & Macros]:::process
+ SUB --> INJECT[Inject Device Parameters & Models]:::process
+ INJECT --> SPICE([Generate .cir SPICE Netlist]):::io
+```
+
+---
+
+## 4. Device Model Generation Pipeline
+
+Outlining how user-defined models (Diodes, BJTs, MOSFETs) are integrated via the Model Editor.
+
+```mermaid
+flowchart LR
+ %% Styling
+ classDef input fill:#2C3E50,stroke:#1A252F,stroke-width:2px,color:#fff
+ classDef process fill:#E74C3C,stroke:#C0392B,stroke-width:2px,color:#fff
+ classDef output fill:#F39C12,stroke:#E67E22,stroke-width:2px,color:#fff
+
+ UI([Model Editor UI]):::input --> VAL[Validate Parameters]:::process
+ VAL --> TEMPLATE[Inject Data into SPICE Template]:::process
+ TEMPLATE --> LIB([Save to project .lib file]):::output
+ LIB --> K2N([Attached during Netlist Conversion]):::output
+```
diff --git a/README.md b/README.md
index 13e22e36e..32747e7b3 100644
--- a/README.md
+++ b/README.md
@@ -139,66 +139,7 @@ graph TB
KICAD -- Netlist --> PCB
```
-### Simulation Workflow
-
-```mermaid
-flowchart TD
- %% Styling
- classDef startend fill:#2ECC71,stroke:#27AE60,stroke-width:2px,color:#fff
- classDef process fill:#3498DB,stroke:#2980B9,stroke-width:2px,color:#fff
- classDef decision fill:#F1C40F,stroke:#F39C12,stroke-width:2px,color:#333
- classDef io fill:#9B59B6,stroke:#8E44AD,stroke-width:2px,color:#fff
-
- START([Start eSim Project]):::startend --> CREATE{New or Existing?}:::decision
- CREATE -- New --> PROJ[Create Project Structure]:::process
- CREATE -- Existing --> OPEN[Open Project Workspace]:::process
-
- PROJ --> SCHEM[Draw Schematic in KiCad]:::process
- OPEN --> SCHEM
-
- SCHEM --> CHECK{Mixed Signal?}:::decision
- CHECK -- Yes --> VHDL[Write VHDL/Verilog Models]:::process
- VHDL --> GHDL[Compile via NGHDL/NgVeri]:::process
- GHDL --> SYM[Generate KiCad Symbol]:::process
- SYM --> SCHEM
-
- CHECK -- No --> K2N[Run KiCad-to-Ngspice]:::process
- K2N --> PARSE[Parse XML Netlist]:::process
- PARSE --> SRC[Configure Sources & Analysis]:::process
- SRC --> DEV[Configure Device Models]:::process
-
- DEV --> SPICE[Generate .cir SPICE Netlist]:::io
- SPICE --> NGSPICE[Execute Ngspice Simulation]:::process
-
- NGSPICE --> OUT{Simulation Success?}:::decision
- OUT -- No --> ERR[View Error Log & Debug]:::process
- ERR --> SCHEM
-
- OUT -- Yes --> RAW[Generate RAW Output Data]:::io
- RAW --> PLOT[Extract Data for Plotting]:::process
- PLOT --> MAT[Render matplotlib Waveforms]:::process
-
- MAT --> END([Analyze Results]):::startend
-```
-
-### Mixed-Signal Simulation Flow (NGHDL)
-
-```mermaid
-flowchart TD
- %% Styling
- classDef input fill:#34495E,stroke:#2C3E50,stroke-width:2px,color:#fff
- classDef process fill:#16A085,stroke:#1ABC9C,stroke-width:2px,color:#fff
- classDef output fill:#8E44AD,stroke:#9B59B6,stroke-width:2px,color:#fff
-
- VHDL([Write VHDL/Verilog Code]):::input --> UPLOAD[Upload via NGHDL/NgVeri UI]:::process
- UPLOAD --> COMPILE[GHDL/Verilator Compiles Code to Shared Lib]:::process
- COMPILE --> MODEL[Create Ngspice Code Model .cm]:::process
- MODEL --> KICAD[Generate KiCad Component Symbol]:::output
-
- KICAD --> SCHEM([Place Symbol in Schematic]):::input
- SCHEM --> BRIDGE[ADC/DAC Bridge Insertion]:::process
- BRIDGE --> SIM[Execute Mixed-Signal Co-Simulation]:::output
-```
+*For detailed simulation workflows, sub-system operations, and system flowcharts, please refer to our [Architecture & Workflows Guide](ARCHITECTURE.md).*
---
From f648d604dc955ef8fa812781647c530f70207ffb Mon Sep 17 00:00:00 2001
From: Mausam5055
Date: Mon, 1 Jun 2026 22:07:34 +0530
Subject: [PATCH 14/19] Update README.md
---
README.md | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/README.md b/README.md
index 32747e7b3..f425e266f 100644
--- a/README.md
+++ b/README.md
@@ -38,7 +38,7 @@
---
-## About
+## 📖 About
**eSim** is a free and open-source EDA (Electronic Design Automation) tool for circuit design, simulation, analysis, and PCB design. It is an integrated tool built using open-source software such as **KiCad**, **Ngspice**, **GHDL**, and **Makerchip**, providing a seamless workflow from schematic capture to simulation results.
@@ -48,7 +48,7 @@ eSim is designed for electronics engineers, students, educators, and hobbyists w
---
-## Features
+## ✨ Features
| Category | Feature | Description |
|:---------|:--------|:------------|
@@ -68,7 +68,7 @@ eSim is designed for electronics engineers, students, educators, and hobbyists w
---
-## Architecture
+## 🏗️ Architecture
### High-Level System Architecture
@@ -143,7 +143,7 @@ graph TB
---
-## Project Structure
+## 📂 Project Structure
### Root Directory
@@ -354,7 +354,7 @@ esim
# Or double-click the eSim desktop icon
```
-### Windows
+### 🪟 Windows
1. Download the eSim installer from [esim.fossee.in/downloads](https://esim.fossee.in/downloads)
2. Disable antivirus temporarily (if required)
@@ -450,7 +450,7 @@ eSim ships with **42 ready-to-simulate example projects** in the `Examples/` dir
---
-## Contributing
+## 🤝 Contributing
We welcome contributions from the community! Whether it's bug fixes, new features, documentation improvements, or example circuits — every contribution matters.
@@ -499,7 +499,7 @@ For detailed contribution guidelines, see [CONTRIBUTING.md](CONTRIBUTING.md).
---
-## Contributors
+## 👥 Contributors
A huge thank you to all **149+ amazing people** who have contributed to eSim! 🎉
From d22bf98e2bdfa928c3336b874657819f4a0f99fb Mon Sep 17 00:00:00 2001
From: Mausam5055
Date: Mon, 1 Jun 2026 22:09:26 +0530
Subject: [PATCH 15/19] Update README.md
---
README.md | 19 -------------------
1 file changed, 19 deletions(-)
diff --git a/README.md b/README.md
index f425e266f..fa61e53b8 100644
--- a/README.md
+++ b/README.md
@@ -552,26 +552,7 @@ A huge thank you to all **149+ amazing people** who have contributed to eSim!
---
-## 🔒 Security
-For information on reporting security vulnerabilities, please see [SECURITY.md](SECURITY.md).
-
----
-
-## 📄 License
-
-eSim is released under the **GNU General Public License v3.0** — see the [LICENSE](LICENSE) file for details.
-
-```
-Copyright (C) FOSSEE, IIT Bombay
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation, either version 3 of the License, or
-(at your option) any later version.
-```
-
----
Built with ❤️ by the FOSSEE Team at IIT Bombay
From 8b1e10cba5c6af14263fa7f4c20e16a8f7117d23 Mon Sep 17 00:00:00 2001
From: Mausam5055
Date: Mon, 1 Jun 2026 22:10:32 +0530
Subject: [PATCH 16/19] docs: update security policy
---
SECURITY.md | 65 ++++++++++++++++++++++++++++++++++++++++-------------
1 file changed, 50 insertions(+), 15 deletions(-)
diff --git a/SECURITY.md b/SECURITY.md
index 034e84803..a4d483fb3 100644
--- a/SECURITY.md
+++ b/SECURITY.md
@@ -1,21 +1,56 @@
-# Security Policy
+# 🔒 Security Policy
-## Supported Versions
+The eSim project takes security seriously. As a desktop EDA application handling various local file formats, external executables (Ngspice, GHDL, KiCad), and third-party models, we are committed to providing a secure environment for our users.
-Use this section to tell people about which versions of your project are
-currently being supported with security updates.
+---
-| Version | Supported |
-| ------- | ------------------ |
-| 5.1.x | :white_check_mark: |
-| 5.0.x | :x: |
-| 4.0.x | :white_check_mark: |
-| < 4.0 | :x: |
+## ✅ Supported Versions
-## Reporting a Vulnerability
+Security updates are provided for the latest stable release of eSim. Older releases may receive critical patches at the discretion of the core maintainers.
-Use this section to tell people how to report a vulnerability.
+| eSim Version | Status | Security Support |
+| :--- | :--- | :--- |
+| **2.5.x** | Current Stable | 🟢 Supported |
+| **2.4.x** | Previous Stable | 🟡 Critical Fixes Only |
+| **< 2.4** | End of Life | 🔴 Not Supported |
-Tell them where to go, how often they can expect to get an update on a
-reported vulnerability, what to expect if the vulnerability is accepted or
-declined, etc.
+---
+
+## 🚨 Reporting a Vulnerability
+
+If you discover a security vulnerability in eSim (or its integration with bundled tools like Ngspice or GHDL), **please do not report it through public GitHub issues.** Instead, we ask that you practice responsible disclosure.
+
+### Where to Report
+Please email your findings to the core security team at:
+📧 **contact-esim@fossee.in** (Subject: `[SECURITY] Vulnerability Report`)
+
+### What to Include
+To help us quickly understand and reproduce the issue, please include the following in your report:
+- **Description:** A clear summary of the vulnerability and its potential impact (e.g., Local Privilege Escalation, Arbitrary Code Execution via crafted netlists).
+- **Environment:** Your OS version, Python version, and the eSim version.
+- **Reproduction Steps:** Step-by-step instructions, including any malicious/crafted `.cir`, `.sch`, or XML files used.
+- **Proof of Concept (PoC):** Code snippets or a video demonstrating the exploit, if possible.
+
+### Expected Response Timeline
+- **Acknowledgement:** We will acknowledge receipt of your vulnerability report within **48 hours**.
+- **Assessment:** A preliminary assessment and timeline for a patch will be provided within **1 week**.
+- **Fix & Disclosure:** We aim to release a patch and issue a CVE (if applicable) within **30-90 days**, depending on the severity and complexity of the issue. We will keep you updated throughout the process.
+
+---
+
+## 🛡️ Scope of Security
+
+When reporting vulnerabilities, please keep in mind the architecture of eSim.
+
+### In-Scope (Please Report)
+- Vulnerabilities in the core Python application (`src/` codebase).
+- Arbitrary code execution triggered by opening malicious eSim projects, `.xml` files, or schematic files.
+- Insecure handling of permissions or temporary directories during the KiCad-to-Ngspice conversion pipeline.
+
+### Out-of-Scope (Do Not Report Here)
+- Upstream vulnerabilities strictly within the core engines of **KiCad**, **Ngspice**, or **GHDL** that are not exacerbated by eSim's wrapper implementations. Please report these directly to their respective upstream maintainers.
+- Social engineering, phishing, or physical access attacks.
+
+---
+
+*Thank you for helping keep the eSim community safe and secure!*
From a5b6f583992e1db5f4c6e3181045cb9d1b6ae7bc Mon Sep 17 00:00:00 2001
From: Mausam5055
Date: Mon, 1 Jun 2026 22:13:20 +0530
Subject: [PATCH 17/19] Update README.md
---
README.md | 6 +++++-
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diff --git a/README.md b/README.md
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eSim is designed for electronics engineers, students, educators, and hobbyists who want a powerful yet cost-free alternative to proprietary EDA tools. It supports analog, digital, and **mixed-signal simulations**, including microcontroller integration.
-> 📥 **Download**: [esim.fossee.in/downloads](https://esim.fossee.in/downloads) | 📄 **User Manual**: [eSim Manual v2.5 (PDF)](https://static.fossee.in/esim/manuals/eSim_Manual_2.5.pdf) | 📚 **Developer Docs**: [esim.readthedocs.io](https://esim.readthedocs.io/en/latest/)
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