From e2dfdcbac9f16a22a8b206ceab812eca93bd5afa Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 21:23:01 +0530 Subject: [PATCH 01/19] Update README.md --- README.md | 647 ++++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 599 insertions(+), 48 deletions(-) diff --git a/README.md b/README.md index 62b294793..819cd389a 100644 --- a/README.md +++ b/README.md @@ -1,61 +1,612 @@ -![GitHub release (latest by date)](https://img.shields.io/github/v/release/fossee/esim?color=blueviolet) -![GitHub](https://img.shields.io/github/license/fossee/esim?color=blue) -![Python](https://img.shields.io/badge/python-v3.6+-blue.svg) -[![PEP8](https://img.shields.io/badge/code%20style-pep8-orange.svg)](https://www.python.org/dev/peps/pep-0008/) -![Travis (.com)](https://img.shields.io/travis/com/Eyantra698Sumanto/eSim) -[![Documentation Status](https://readthedocs.org/projects/esim/badge/?version=latest)](https://esim.readthedocs.io/en/latest/?badge=latest) -[![GitHub forks](https://img.shields.io/github/forks/fossee/esim)](https://github.com/fossee/esim/network) -[![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg?style=flat)](https://github.com/fossee/esim) -![GitHub contributors](https://img.shields.io/github/contributors/fossee/esim) - -## eSim - -[eSim](https://esim.fossee.in/) is an open source EDA tool for circuit design, simulation, analysis and PCB design, developed by [FOSSEE Team](https://www.fossee.in/) at [IIT Bombay](https://www.iitb.ac.in/). -It is an integrated tool build using open source softwares such as KiCad, Ngspice and GHDL. - -## Releases and Installation -eSim is released for the following distributions (operating systems): -* **All Linux distributions** (Fedora, Ubuntu, openSUSE, Arch, etc.) via Flatpak -* Ubuntu 22.04, 23.04, 24.04 LTS versions (native installer) -* Microsoft Windows 8, 10 and 11 - -**For Fedora and other Linux distributions:** Use the Flatpak method for easy installation: +

+ eSim Logo +

+ +

eSim — Electronic Circuit Simulation

+ +

+ An Open-Source EDA Tool for Circuit Design, Simulation, Analysis & PCB Design
+ Developed by FOSSEE Team at IIT Bombay +

+ +

+ Release + License + Python + PyQt6 +

+ +

+ Docs + Forks + Stars + Issues + PRs Welcome + Contributors + PEP8 +

+ +

+ Features • + Architecture • + Installation • + Project Structure • + Tech Stack • + Contributing • + License +

+ +--- + +## 📖 About + +**eSim** is a free and open-source EDA (Electronic Design Automation) tool for circuit design, simulation, analysis, and PCB design. It is an integrated tool built using open-source software such as **KiCad**, **Ngspice**, **GHDL**, and **Makerchip**, providing a seamless workflow from schematic capture to simulation results. + +eSim is designed for electronics engineers, students, educators, and hobbyists who want a powerful yet cost-free alternative to proprietary EDA tools. It supports analog, digital, and **mixed-signal simulations**, including microcontroller integration. + +> 📥 **Download**: [esim.fossee.in/downloads](https://esim.fossee.in/downloads)  |  📄 **User Manual**: [eSim Manual v2.5 (PDF)](https://static.fossee.in/esim/manuals/eSim_Manual_2.5.pdf)  |  📚 **Developer Docs**: [esim.readthedocs.io](https://esim.readthedocs.io/en/latest/) + +--- + +## ✨ Features + +| Category | Feature | Description | +|:---------|:--------|:------------| +| 🎨 **Design** | Schematic Capture | Draw circuit schematics using KiCad's schematic editor with eSim's custom symbol libraries | +| 🔄 **Conversion** | KiCad to Ngspice | Convert KiCad schematics to Ngspice-compatible netlists for simulation | +| ⚡ **Simulation** | Ngspice Engine | Run DC, AC, Transient, and other SPICE analyses with real-time interactive plots | +| 📊 **Analysis** | Waveform Plotting | Visualize simulation results with matplotlib-based Python plots and Ngspice native plots | +| 🔧 **Model Editor** | Device Models | Create and edit SPICE device models (Diodes, BJTs, MOSFETs, JFETs, IGBTs, etc.) | +| 🧩 **Subcircuits** | Subcircuit Builder | Build, manage, and upload reusable subcircuit blocks | +| 🖥️ **Mixed-Signal** | NGHDL Integration | Interface VHDL digital models (via GHDL) with analog Ngspice simulations | +| 🌐 **Verilog** | Makerchip + NgVeri | Use Makerchip IDE for Verilog/TL-Verilog design and convert to Ngspice models | +| 🏭 **PCB** | Layout Design | Design PCB layouts using KiCad's PCB editor with eSim's footprint libraries | +| 🔁 **Converters** | Schematic Import | Convert PSpice and LTSpice schematics/libraries to KiCad-compatible formats | +| 📐 **Modelica** | Ngspice-to-Modelica | Convert Ngspice netlists to Modelica models for OpenModelica simulation | +| 🏗️ **SKY130 PDK** | SkyWater 130nm | Support for SkyWater SKY130 open-source Process Design Kit | +| 🔬 **IHP PDK** | IHP OpenPDK | Integration with IHP SG13G2 open-source PDK for SiGe BiCMOS | + +--- + +## 🏗️ Architecture + +### High-Level System Architecture + +```mermaid +graph TB + subgraph USER["👤 User Interface Layer"] + APP["Application.py
Main Window (PyQt6)"] + PE["ProjectExplorer
File Browser"] + DA["DockArea
Tabbed Workspace"] + TE["TimeExplorer
Snapshot Manager"] + CON["Console
Log Output"] + end + + subgraph CORE["⚙️ Core Engine Layer"] + KNG["KiCad-to-Ngspice
Converter"] + SIM["Ngspice Simulation
Engine"] + PLT["Plot Window
matplotlib"] + ME["Model Editor"] + SC["Subcircuit
Manager"] + end + + subgraph INTEGRATION["🔌 Integration Layer"] + NGHDL["NGHDL
GHDL Interface"] + MKR["Makerchip/NgVeri
Verilog Models"] + MOD["Modelica Converter
OpenModelica"] + CONV["Schematic Converters
PSpice / LTSpice"] + end + + subgraph EXTERNAL["📦 External Tools"] + KICAD["KiCad
Schematic + PCB"] + NGSPICE["Ngspice
SPICE Simulator"] + GHDL["GHDL
VHDL Simulator"] + VERILATOR["Verilator
Verilog Simulator"] + OMEDIT["OpenModelica
Modelica IDE"] + end + + APP --> PE + APP --> DA + APP --> TE + APP --> CON + + DA --> KNG + DA --> SIM + DA --> ME + DA --> SC + DA --> NGHDL + DA --> MKR + DA --> MOD + DA --> CONV + + KNG --> KICAD + SIM --> NGSPICE + SIM --> PLT + NGHDL --> GHDL + MKR --> VERILATOR + MOD --> OMEDIT + + style USER fill:#1a1a2e,stroke:#e94560,color:#fff + style CORE fill:#16213e,stroke:#0f3460,color:#fff + style INTEGRATION fill:#0f3460,stroke:#533483,color:#fff + style EXTERNAL fill:#533483,stroke:#e94560,color:#fff +``` + +### Simulation Workflow + +```mermaid +flowchart LR + A["📝 Create/Open
Project"] --> B["🎨 Draw
Schematic
KiCad"] + B --> C["🔄 Convert
KiCad → Ngspice"] + C --> D["⚙️ Configure
Analysis &
Parameters"] + D --> E["▶️ Run
Simulation
Ngspice"] + E --> F["📊 Plot &
Analyze
Results"] + + style A fill:#6c5ce7,stroke:#a29bfe,color:#fff + style B fill:#00b894,stroke:#55efc4,color:#fff + style C fill:#fdcb6e,stroke:#f9ca24,color:#333 + style D fill:#e17055,stroke:#fab1a0,color:#fff + style E fill:#0984e3,stroke:#74b9ff,color:#fff + style F fill:#d63031,stroke:#ff7675,color:#fff +``` + +### Mixed-Signal Simulation Flow (NGHDL) + +```mermaid +flowchart TB + V["📄 Write VHDL Code"] --> U["⬆️ Upload via NGHDL"] + U --> G["🔧 GHDL Compiles
VHDL to Shared Lib"] + G --> CM["📦 Create Ngspice
Code Model"] + CM --> KS["🎨 Create KiCad
Symbol"] + KS --> SC["📝 Use in
Schematic"] + SC --> SIM["⚡ Mixed-Signal
Simulation"] + + style V fill:#a29bfe,stroke:#6c5ce7,color:#fff + style U fill:#74b9ff,stroke:#0984e3,color:#fff + style G fill:#55efc4,stroke:#00b894,color:#fff + style CM fill:#ffeaa7,stroke:#fdcb6e,color:#333 + style KS fill:#fab1a0,stroke:#e17055,color:#fff + style SIM fill:#fd79a8,stroke:#e84393,color:#fff +``` + +--- + +## 📂 Project Structure + +### Root Directory + +| Path | Type | Description | +|:-----|:-----|:------------| +| `src/` | 📁 Directory | **Core application source code** — all Python modules for the eSim GUI and backend | +| `library/` | 📁 Directory | **Component libraries** — device models, KiCad symbols, subcircuits, and PDK data | +| `nghdl/` | 📁 Directory | **NGHDL module** — Ngspice-GHDL interface for mixed-signal VHDL simulation | +| `Examples/` | 📁 Directory | **42 example projects** — ready-to-simulate circuits (RC, BJT, Op-Amp, Mixed-Signal, etc.) | +| `images/` | 📁 Directory | **UI assets** — application icons, toolbar images, logos, and splash screen | +| `scripts/` | 📁 Directory | **Launch & setup scripts** — shell scripts for Linux installation and launching | +| `docs/` | 📁 Directory | **Sphinx documentation** — RST files for ReadTheDocs auto-generated developer docs | +| `code/` | 📁 Directory | **Sphinx autodoc config** — mirrors `src/` structure for API documentation generation | +| `flatpak/` | 📁 Directory | **Flatpak packaging** — manifest and wrapper scripts for universal Linux distribution | +| `appimage/` | 📁 Directory | **AppImage packaging** — build scripts for portable Linux AppImage bundles | +| `docker-launcher/` | 📁 Directory | **Docker support** — Dockerfile, launcher script, and CI workflows for containerized builds | +| `snap/` | 📁 Directory | **Snap packaging** — `snapcraft.yaml` for building Snap packages | +| `ihp/` | 📁 Directory | **IHP PDK integration** — install script for IHP SG13G2 open-source SiGe BiCMOS PDK | +| `patches/` | 📁 Directory | **Source patches** — patch files for modifying Ngspice/GHDL behavior in sandboxed environments | +| `.github/` | 📁 Directory | **GitHub config** — issue templates, PR templates, and CI/CD workflow definitions | +| `setup.py` | 📄 File | Python package configuration for pip installation | +| `requirements.txt` | 📄 File | Python dependency list (PyQt6, matplotlib, numpy, scipy, etc.) | +| `conf.py` | 📄 File | Sphinx documentation configuration | +| `VERSION` | 📄 File | Current version identifier (`2.5`) | +| `INSTALL` | 📄 File | Detailed multi-platform installation instructions | +| `LICENSE` | 📄 File | GNU General Public License v3.0 | + +### Source Code (`src/`) — Detailed Module Breakdown + +``` +src/ +├── frontEnd/ # 🖥️ GUI & Main Application +│ ├── Application.py # Main window, toolbar setup, menu actions (960 lines) +│ ├── DockArea.py # Tabbed dock workspace for editors/simulators (24K) +│ ├── ProjectExplorer.py # File tree browser for project navigation (20K) +│ ├── TimeExplorer.py # Project snapshot/version management (8K) +│ ├── TerminalUi.py # Embedded terminal widget (5K) +│ └── Workspace.py # Workspace selection dialog (6K) +│ +├── kicadtoNgspice/ # 🔄 KiCad-to-Ngspice Conversion Engine +│ ├── KicadtoNgspice.py # Main conversion controller & UI (41K) +│ ├── Convert.py # Netlist parsing and SPICE generation (40K) +│ ├── Analysis.py # Analysis type configuration (DC, AC, Transient) (32K) +│ ├── DeviceModel.py # Device model parameter handling (56K) +│ ├── Source.py # Source component configuration (15K) +│ ├── Processing.py # Netlist processing pipeline (26K) +│ ├── SubcircuitTab.py # Subcircuit selection in converter (9K) +│ ├── Microcontroller.py # Microcontroller model support (10K) +│ ├── Model.py # Model file handling (6K) +│ └── TrackWidget.py # UI tracking widget (1K) +│ +├── ngspiceSimulation/ # ⚡ Simulation Engine & Plotting +│ ├── NgspiceWidget.py # Ngspice process management & execution (16K) +│ ├── plot_window.py # matplotlib-based waveform plotter (66K) +│ ├── plotting_widgets.py # Custom plot controls and widgets (8K) +│ └── data_extraction.py # Simulation data file parser (11K) +│ +├── modelEditor/ # 🔧 SPICE Model Editor +│ └── ModelEditor.py # GUI for creating/editing device models (33K) +│ +├── subcircuit/ # 🧩 Subcircuit Management +│ ├── Subcircuit.py # Subcircuit manager main window (3K) +│ ├── newSub.py # Create new subcircuit (3K) +│ ├── openSub.py # Open existing subcircuit (1K) +│ ├── uploadSub.py # Upload subcircuit to library (4K) +│ └── convertSub.py # Subcircuit format conversion (2K) +│ +├── maker/ # 🌐 Makerchip & NgVeri Integration +│ ├── Maker.py # Makerchip IDE integration (23K) +│ ├── NgVeri.py # Verilog-to-Ngspice model generator (17K) +│ ├── ModelGeneration.py # Auto model generation pipeline (48K) +│ ├── createkicad.py # KiCad symbol creation for models (14K) +│ ├── makerchip.py # Makerchip cloud IDE connector (3K) +│ └── Appconfig.py # Maker-specific configuration (2K) +│ +├── converter/ # 🔁 Schematic Format Converters +│ ├── pspiceToKicad.py # PSpice schematic importer (5K) +│ ├── ltspiceToKicad.py # LTSpice schematic importer (6K) +│ ├── libConverter.py # Library format converter (3K) +│ ├── LtspiceLibConverter.py # LTSpice library converter (4K) +│ ├── browseSchematic.py # File browser for schematics (550B) +│ ├── LTSpiceToKiCadConverter/ # LTSpice conversion engine +│ └── schematic_converters/ # Additional schematic parsers +│ +├── ngspicetoModelica/ # 📐 Ngspice-to-Modelica Converter +│ ├── NgspicetoModelica.py # Core conversion engine (54K) +│ └── ModelicaUI.py # Modelica converter GUI (10K) +│ +├── configuration/ # ⚙️ Application Configuration +│ └── Appconfig.py # Global config, paths, process tracking (4K) +│ +├── projManagement/ # 📋 Project Management +│ ├── Kicad.py # KiCad integration (launch schematic/PCB editor) (9K) +│ ├── Validation.py # Tool and file validation utilities (7K) +│ ├── Worker.py # Background process/thread management (3K) +│ ├── newProject.py # New project creation logic (5K) +│ └── openProject.py # Open existing project logic (3K) +│ +└── browser/ # 📖 Help & Documentation + ├── Welcome.py # Welcome screen display (941B) + └── UserManual.py # User manual viewer (731B) +``` + +### Library Directory (`library/`) — Component Libraries + +| Path | Description | +|:-----|:------------| +| `deviceModelLibrary/` | SPICE device models organized by type: Diode, BJT (Transistor), MOSFET (MOS), JFET, IGBT, LEDs, Switches, Transmission Lines, and user libraries | +| `kicadLibrary/` | KiCad schematic symbols (`eSim-symbols/`), footprint libraries (`kicad_eSim-Library/`), and project templates | +| `SubcircuitLibrary/` | Reusable subcircuit definitions for common circuit blocks | +| `modelParamXML/` | XML parameter definitions for device model editor forms | +| `ngspicetoModelica/` | Mapping files for Ngspice-to-Modelica component translation | +| `browser/` | HTML/resource files for the built-in help browser | +| `tlv/` | TL-Verilog support files for Makerchip integration | + +### NGHDL Module (`nghdl/`) — Mixed-Signal Interface + +| Path | Description | +|:-----|:------------| +| `src/ngspice_ghdl.py` | Core interface: manages VHDL upload, GHDL compilation, and Ngspice code model creation | +| `src/model_generation.py` | Generates C code models from VHDL port definitions for Ngspice | +| `src/createKicadLibrary.py` | Auto-generates KiCad symbols from VHDL entity definitions | +| `src/ghdlserver/` | GHDL foreign interface server for inter-process communication with Ngspice | +| `install-nghdl.sh` | Automated installer for NGHDL dependencies (GHDL, Verilator, Ngspice) | +| `Example/` | Example VHDL models and mixed-signal simulation projects | + +--- + +## 🛠️ Tech Stack + +| Layer | Technology | Purpose | +|:------|:-----------|:--------| +| **Language** | ![Python](https://img.shields.io/badge/Python_3.6+-3776AB?style=flat-square&logo=python&logoColor=white) | Core application logic | +| **GUI Framework** | ![PyQt6](https://img.shields.io/badge/PyQt6-41CD52?style=flat-square&logo=qt&logoColor=white) | Desktop GUI (windows, dialogs, toolbars, docks) | +| **Plotting** | ![matplotlib](https://img.shields.io/badge/matplotlib-11557c?style=flat-square&logo=plotly&logoColor=white) | Waveform visualization and data plotting | +| **Numerics** | ![NumPy](https://img.shields.io/badge/NumPy-013243?style=flat-square&logo=numpy&logoColor=white) ![SciPy](https://img.shields.io/badge/SciPy-8CAAE6?style=flat-square&logo=scipy&logoColor=white) | Numerical computation and signal processing | +| **Schematic & PCB** | ![KiCad](https://img.shields.io/badge/KiCad-314CB0?style=flat-square&logo=kicad&logoColor=white) | Schematic capture and PCB layout design | +| **SPICE Simulation** | ![Ngspice](https://img.shields.io/badge/Ngspice-darkgreen?style=flat-square) | Analog/mixed-signal circuit simulation engine | +| **VHDL Simulation** | ![GHDL](https://img.shields.io/badge/GHDL-2ea44f?style=flat-square) | VHDL analysis, compilation, and simulation | +| **Verilog** | ![Verilator](https://img.shields.io/badge/Verilator-527FFF?style=flat-square) | Verilog HDL simulation and model generation | +| **HDL Cloud IDE** | ![Makerchip](https://img.shields.io/badge/Makerchip-FF6B6B?style=flat-square) | Online Verilog/TL-Verilog IDE integration | +| **Modelica** | ![OpenModelica](https://img.shields.io/badge/OpenModelica-1B2A49?style=flat-square) | Multi-domain modeling and simulation | +| **PDK** | ![SkyWater](https://img.shields.io/badge/SKY130_PDK-blue?style=flat-square) | SkyWater 130nm open-source process design kit | +| **Packaging** | ![Flatpak](https://img.shields.io/badge/Flatpak-4A86CF?style=flat-square&logo=flatpak&logoColor=white) ![Docker](https://img.shields.io/badge/Docker-2496ED?style=flat-square&logo=docker&logoColor=white) | Cross-distribution Linux packaging & containers | +| **Documentation** | ![Sphinx](https://img.shields.io/badge/Sphinx-000000?style=flat-square&logo=sphinx&logoColor=white) ![RTD](https://img.shields.io/badge/ReadTheDocs-8CA1AF?style=flat-square&logo=readthedocs&logoColor=white) | Auto-generated developer documentation | +| **CI/CD** | ![GitHub Actions](https://img.shields.io/badge/GitHub_Actions-2088FF?style=flat-square&logo=githubactions&logoColor=white) | Automated builds, Docker images, and releases | + +### Key Python Dependencies + +| Package | Version | Purpose | +|:--------|:--------|:--------| +| `PyQt6` | ≥ 6.5.0 | GUI framework | +| `matplotlib` | 3.7.5 | Waveform plotting | +| `numpy` | 1.24.4 | Numerical computation | +| `scipy` | 1.10.1 | Scientific computing | +| `pillow` | 12.2.0 | Image processing | +| `hdlparse` | 1.0.4 | HDL file parsing | +| `watchdog` | 4.0.2 | File system monitoring | +| `pyparsing` | 3.1.4 | Parser building toolkit | + +--- + +## 💻 Installation + +### Supported Platforms + +| Platform | Method | Status | +|:---------|:-------|:------:| +| **All Linux** (Fedora, Ubuntu, openSUSE, Arch, etc.) | Flatpak | ✅ Recommended | +| **Ubuntu** 22.04 / 23.04 / 24.04 LTS | Native Installer | ✅ Supported | +| **Windows** 8 / 10 / 11 | Windows Installer | ✅ Supported | +| **Docker** (any OS) | Docker Container | ✅ Supported | + +### 🐧 Linux — Flatpak (Recommended for all distributions) + ```bash +# 1. Install Flatpak (if not already installed) +# Fedora: sudo dnf install flatpak +# Ubuntu: sudo apt install flatpak +# openSUSE: sudo zypper install flatpak +# Arch: sudo pacman -S flatpak + +# 2. Add Flathub repository +flatpak remote-add --if-not-exists flathub https://dl.flathub.org/repo/flathub.flatpakrepo + +# 3. Install eSim flatpak install flathub org.fossee.eSim + +# 4. Run eSim flatpak run org.fossee.eSim ``` -Or build from source: `flatpak-builder build flatpak/org.fossee.eSim.yml --install --user` -**For Ubuntu and Windows:** Please refer to [downloads](https://esim.fossee.in/downloads) for installation guidelines. +> **⚠️ Flatpak Limitations:** NGHDL, Makerchip, and SKY130 PDK are not included in the Flatpak build. For full mixed-signal support, use the Ubuntu native installer. + +### 🐧 Ubuntu — Native Installer + +```bash +# 1. Download and extract eSim +unzip eSim-2.5.zip +cd eSim-2.5 + +# 2. Install eSim with all dependencies +chmod +x install-eSim.sh +./install-eSim.sh --install + +# 3. Run eSim +esim +# Or double-click the eSim desktop icon +``` + +### 🪟 Windows + +1. Download the eSim installer from [esim.fossee.in/downloads](https://esim.fossee.in/downloads) +2. Disable antivirus temporarily (if required) +3. **Important:** Remove MinGW/MSYS from the PATH environment variable if previously installed +4. Run the installer and follow the on-screen instructions +5. Launch eSim from the Start Menu or desktop shortcut + +### 🐋 Docker + +Refer to the [Docker Launcher README](docker-launcher/README.md) for instructions on running eSim in a containerized environment. + +### 📦 Build from Source (Flatpak) + +```bash +cd eSim +flatpak-builder build flatpak/org.fossee.eSim.yml --install --user +``` + +> 📖 For comprehensive installation instructions, see the [INSTALL](INSTALL) file. + +--- + +## 🔄 CI/CD & Packaging + +| Workflow | File | Purpose | +|:---------|:-----|:--------| +| Docker Image Build | `.github/workflows/docker-image.yml` | Builds and publishes the eSim Docker image | +| Docker Launcher Build | `.github/workflows/docker-launcher-build.yml` | Builds the cross-platform Python launcher | +| Ubuntu Release | `.github/workflows/release_ubuntu.yml` | Automated Ubuntu `.deb` package builds | + +| Packaging Format | Directory | Description | +|:-----------------|:----------|:------------| +| Flatpak | `flatpak/` | Universal Linux package via Flathub | +| AppImage | `appimage/` | Portable single-file Linux executable | +| Snap | `snap/` | Ubuntu Snap Store package | +| Docker | `docker-launcher/` | Containerized distribution with GUI forwarding | + +--- + +## 📋 Example Projects + +eSim ships with **42 ready-to-simulate example projects** in the `Examples/` directory: + +
+📂 Click to expand full example list + +| # | Category | Example | Description | +|:-:|:---------|:--------|:------------| +| 1 | 🔌 Basic | `RC` | RC circuit transient analysis | +| 2 | 🔌 Basic | `RL` | RL circuit transient analysis | +| 3 | 🔌 Basic | `RLC` | RLC circuit resonance analysis | +| 4 | 🔌 Basic | `Series_Resonance` | Series RLC resonance | +| 5 | 🔌 Basic | `Parallel_Resonance` | Parallel RLC resonance | +| 6 | 💡 Diodes | `Diode_characteristics` | Diode I-V characteristics | +| 7 | 💡 Diodes | `Halfwave_Rectifier` | Half-wave rectifier circuit | +| 8 | 💡 Diodes | `Fullwavebridgerectifier` | Full-wave bridge rectifier | +| 9 | 💡 Diodes | `Clippercircuit` | Diode clipper circuit | +| 10 | 💡 Diodes | `Clampercircuit` | Diode clamper circuit | +| 11 | 💡 Diodes | `Zener_Characteristic` | Zener diode characteristics | +| 12 | 🔋 BJT | `BJT_CE_config` | BJT common-emitter configuration | +| 13 | 🔋 BJT | `BJT_CB_config` | BJT common-base configuration | +| 14 | 🔋 BJT | `BJT_amplifier` | BJT amplifier circuit | +| 15 | 🔋 BJT | `BJT_Biascircuit` | BJT bias circuit design | +| 16 | 🔋 BJT | `BJT_Frequency_Response` | BJT frequency response analysis | +| 17 | 📟 FET | `FET_Characteristic` | FET output characteristics | +| 18 | 📟 FET | `FET_Amplifier` | FET amplifier circuit | +| 19 | 📟 FET | `FrequencyResponse_JFET` | JFET frequency response | +| 20 | 🎛️ Op-Amp | `InvertingAmplifier` | Op-amp inverting amplifier (LM741) | +| 21 | 🎛️ Op-Amp | `Differentiator` | Op-amp differentiator circuit | +| 22 | 🎛️ Op-Amp | `Integrator_LM_741` | Op-amp integrator | +| 23 | 🎛️ Op-Amp | `Precision_Rectifiers_using_LM741` | Precision rectifier circuits | +| 24 | 🔲 Digital | `BasicGates` | Basic logic gates | +| 25 | 🔲 Digital | `Half_Adder` | Half-adder circuit | +| 26 | 🔲 Digital | `FullAdder` | Full-adder circuit | +| 27 | 🔲 Digital | `JK_Flipflop` | JK flip-flop circuit | +| 28 | 🔲 Digital | `4_bit_JK_ff` | 4-bit JK flip-flop counter | +| 29 | 🔲 Digital | `CMOS_NAND_Gate` | CMOS NAND gate | +| 30 | 🔲 Digital | `Analysis_Of_Digital_IC` | Digital IC analysis | +| 31 | ⏱️ Timers | `Astable555` | 555 timer astable mode | +| 32 | ⏱️ Timers | `Monostable555` | 555 timer monostable mode | +| 33 | 🔁 SCR | `HalfwaveRectifier_SCR` | SCR half-wave rectifier | +| 34 | 🔁 SCR | `FullwaveRectifier_SCR` | SCR full-wave rectifier | +| 35 | 📡 Filters | `High_Pass_Filter` | High-pass filter design | +| 36 | 📡 Filters | `Low_Pass_Filter` | Low-pass filter design | +| 37 | ⚡ Regulators | `7805VoltageRegulator` | 7805 voltage regulator | +| 38 | ⚡ Regulators | `7812VoltageRegulator` | 7812 voltage regulator | +| 39 | 🌀 Oscillators | `UJT_Relaxation_Oscillator` | UJT relaxation oscillator | +| 40 | 🌀 Oscillators | `Phase_Locked_Loop` | PLL circuit | +| 41 | 🔀 Mixed-Signal | `Mixed_Signal` | Mixed analog-digital simulation (NGHDL) | +| 42 | 🔌 Power | `Transformer` | Transformer circuit analysis | + +
+ +--- + +## 🤝 Contributing + +We welcome contributions from the community! Whether it's bug fixes, new features, documentation improvements, or example circuits — every contribution matters. + +### How to Contribute + +```mermaid +flowchart LR + A["🍴 Fork
Repository"] --> B["🌿 Create
Branch"] + B --> C["💻 Make
Changes"] + C --> D["✅ Commit &
Push"] + D --> E["📬 Open
Pull Request"] + + style A fill:#6c5ce7,color:#fff + style B fill:#00b894,color:#fff + style C fill:#0984e3,color:#fff + style D fill:#fdcb6e,color:#333 + style E fill:#e17055,color:#fff +``` + +1. **Fork** the repository to your GitHub account +2. **Clone** your fork: + ```bash + git clone https://github.com//eSim.git + ``` +3. **Create a new branch** for your changes: + ```bash + git checkout -b feature/your-feature-name + ``` +4. **Make your changes** and commit with a descriptive message: + ```bash + git add + git commit -m "Fixes issue # - Brief description of changes" + ``` +5. **Push** to your fork and **open a Pull Request**: + ```bash + git push origin feature/your-feature-name + ``` + +> **📌 Guidelines:** +> - Each PR should reference an existing issue +> - One commit per pull request (squash if needed) +> - Follow [PEP 8](https://www.python.org/dev/peps/pep-0008/) code style +> - Include a commit body describing what you changed and why + +For detailed contribution guidelines, see [CONTRIBUTION.md](CONTRIBUTION.md). + +--- + +## 👥 Top Contributors -See [INSTALL](INSTALL) for detailed installation instructions for all platforms. +A huge thank you to all the amazing people who have contributed to eSim! 🎉 -## Features -* An open-source EDA tool. -* Perform Circuit Design. -* Perform Simulation. -* Perform Layout Design. -* Model and Subcircuit builder. -* Support for Mixed-Signal Simulations including Microcontrollers. -* eSim has been successfully ported to low cost FOSSEE [laptop](https://laptop.fossee.in/) +| # | Contributor | Commits | GitHub Profile | +|:-:|:------------|:-------:|:---------------| +| 🥇 | **Sumanto Kar** | 280 | [![GitHub](https://img.shields.io/badge/-Eyantra698Sumanto-181717?style=flat-square&logo=github)](https://github.com/Eyantra698Sumanto) | +| 🥈 | **Rahul Paknikar** | 262 | [![GitHub](https://img.shields.io/badge/-rahulp13-181717?style=flat-square&logo=github)](https://github.com/rahulp13) | +| 🥉 | **Fahim Khan** | 244 | [![GitHub](https://img.shields.io/badge/-fahim--eSim-181717?style=flat-square&logo=github)](https://github.com/fahim-oscad) | +| 4 | **Saurabh Bansod** | 46 | [![GitHub](https://img.shields.io/badge/-saurabhb17-181717?style=flat-square&logo=github)](https://github.com/saurabhb17) | +| 5 | **Athul George** | 37 | [![GitHub](https://img.shields.io/badge/-athulappadan-181717?style=flat-square&logo=github)](https://github.com/athulappadan) | +| 6 | **Nil Shah** | 36 | [![GitHub](https://img.shields.io/badge/-nilshah98-181717?style=flat-square&logo=github)](https://github.com/nilshah98) | +| 7 | **Pranav P** | 34 | [![GitHub](https://img.shields.io/badge/-pranavsdreams-181717?style=flat-square&logo=github)](https://github.com/pranavsdreams) | +| 8 | **Annesha Dey** | 33 | [![GitHub](https://img.shields.io/badge/-AD20047-181717?style=flat-square&logo=github)](https://github.com/AD20047) | +| 9 | **Sunil Shetye** | 33 | [![GitHub](https://img.shields.io/badge/-sunilshetye-181717?style=flat-square&logo=github)](https://github.com/sunilshetye) | +| 10 | **Anjali Jaiswal** | 32 | [![GitHub](https://img.shields.io/badge/-anjalijaiswal08-181717?style=flat-square&logo=github)](https://github.com/anjalijaiswal08) | +| 11 | **Hariom Thakur** | 28 | [![GitHub](https://img.shields.io/badge/-hariom-181717?style=flat-square&logo=github)](https://github.com/hariom) | +| 12 | **Shanthi Priya** | 24 | [![GitHub](https://img.shields.io/badge/-shanthipriya-181717?style=flat-square&logo=github)](https://github.com/shanthipriya) | +| 13 | **Aditya Minocha** | 23 | [![GitHub](https://img.shields.io/badge/-adityaminocha-181717?style=flat-square&logo=github)](https://github.com/adityaminocha) | +| 14 | **Ganderla Chaithanya** | 22 | [![GitHub](https://img.shields.io/badge/-GanderlaChaithanya-181717?style=flat-square&logo=github)](https://github.com/GanderlaChaithanya) | +| 15 | **Anwesha** | 21 | [![GitHub](https://img.shields.io/badge/-Anwesha06-181717?style=flat-square&logo=github)](https://github.com/Anwesha06) | -## Open-Source Softwares Used -* [Python](https://www.python.org/) -* [KiCad](https://www.kicad.org/) -* [NGHDL](https://github.com/fossee/nghdl/) -* [Makerchip](https://www.makerchip.com/) -* [SkyWater SKY130 PDK](https://skywater-pdk.rtfd.io/) +

+ + Contributors + +

-## eSim Manual -To know everything about eSim, how it works and it's feature please download the manual from [here](https://static.fossee.in/esim/manuals/eSim_Manual_2.5.pdf) +

149+ contributors and counting! View all →

+ +--- + +## 📞 Contact & Support + +| Channel | Link | +|:--------|:-----| +| 📧 **Email** | [contact-esim@fossee.in](mailto:contact-esim@fossee.in) | +| 🌐 **Website** | [esim.fossee.in](https://esim.fossee.in/) | +| 💬 **Forum** | [forums.fossee.in](https://forums.fossee.in/) | +| 📞 **Contact Page** | [esim.fossee.in/contact-us](https://esim.fossee.in/contact-us) | +| 📄 **User Manual** | [eSim Manual v2.5 (PDF)](https://static.fossee.in/esim/manuals/eSim_Manual_2.5.pdf) | +| 📚 **Developer Docs** | [esim.readthedocs.io](https://esim.readthedocs.io/en/latest/) | + +--- + +## 🔒 Security + +For information on reporting security vulnerabilities, please see [SECURITY.md](SECURITY.md). + +--- + +## 📄 License + +eSim is released under the **GNU General Public License v3.0** — see the [LICENSE](LICENSE) file for details. + +``` +Copyright (C) FOSSEE, IIT Bombay + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. +``` -## Contact -For any queries regarding eSim please write us on at this [email address](mailto:contact-esim@fossee.in). +--- -Other Contact Details are available [here](https://esim.fossee.in/contact-us). +

+ Built with ❤️ by the FOSSEE Team at IIT Bombay +

-## Contribution -Please refer [here](https://github.com/FOSSEE/eSim/blob/master/CONTRIBUTION.md) for further details. +

+ + FOSSEE Logo + +      + + IIT Bombay Logo + +

-## License -It is developed by FOSSEE Team at IIT Bombay and is released under GNU GPL License. +

+ ⭐ If you find eSim useful, consider giving it a star on GitHub! +

From 447d1883c07eab29c223613650526cc0edc62858 Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 21:29:41 +0530 Subject: [PATCH 02/19] Create CONTRIBUTORS.md --- CONTRIBUTORS.md | 364 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 364 insertions(+) create mode 100644 CONTRIBUTORS.md diff --git a/CONTRIBUTORS.md b/CONTRIBUTORS.md new file mode 100644 index 000000000..edc788eb8 --- /dev/null +++ b/CONTRIBUTORS.md @@ -0,0 +1,364 @@ +

+ eSim Logo +

+ +

🏆 eSim Contributors

+ +

+ Honoring the people who built eSim — since February 2015
+ An open-source EDA tool by FOSSEE at IIT Bombay +

+ +

+ Contributors + Total Commits + Stars + PRs Welcome +

+ +--- + +eSim is built by a vibrant community of **149+ contributors** — students, researchers, engineers, and open-source enthusiasts from around the world. This page recognizes everyone who has contributed code, documentation, bug fixes, and features to the project since its first commit on **February 5, 2015**. + +--- + +## 🏛️ Project Leads & Organization + +| Role | Name | Affiliation | +|:-----|:-----|:------------| +| **Developed by** | [FOSSEE Team](https://www.fossee.in/) | IIT Bombay | +| **Original Author** | Fahim Khan | eSim / FOSSEE, IIT Bombay | +| **Lead Maintainer** | Sumanto Kar | FOSSEE, IIT Bombay | +| **Core Maintainer** | Rahul Paknikar | FOSSEE, IIT Bombay | +| **Core Maintainer** | Pranav P | FOSSEE, IIT Bombay | + +--- + +## 🥇 Core Maintainers + +These individuals have made sustained, foundational contributions to eSim's architecture, features, and long-term maintenance. + + + + + + + +
+ + Sumanto Kar
+ Sumanto Kar +

+ 320 commits
+ GitHub +
+ + Rahul Paknikar
+ Rahul Paknikar +

+ 265 commits
+ GitHub +
+ + Fahim Khan
+ Fahim Khan +

+ 244 commits
+ GitHub +
+ +--- + +## 🥈 Major Contributors + +Contributors with **20+ commits** who have made significant impact on major features, modules, or subsystems. + +| # | Contributor | Commits | GitHub | Key Contributions | +|:-:|:------------|:-------:|:------:|:------------------| +| 1 | **Saurabh Bansode** | 49 | [![GitHub](https://img.shields.io/badge/-saurabhb17-181717?style=flat-square&logo=github)](https://github.com/saurabhb17) | Schematic converters, KiCad integration | +| 2 | **Athul George** | 37 | [![GitHub](https://img.shields.io/badge/-athulappadan-181717?style=flat-square&logo=github)](https://github.com/athulappadan) | Frontend, project management | +| 3 | **Nil Shah** | 36 | [![GitHub](https://img.shields.io/badge/-nilshah98-181717?style=flat-square&logo=github)](https://github.com/nilshah98) | Core modules, simulation engine | +| 4 | **Pranav P** | 34 | [![GitHub](https://img.shields.io/badge/-pranavsdreams-181717?style=flat-square&logo=github)](https://github.com/pranavsdreams) | Application UI, maintenance | +| 5 | **Annesha Dey** | 33 | [![GitHub](https://img.shields.io/badge/-AD20047-181717?style=flat-square&logo=github)](https://github.com/AD20047) | Feature development | +| 6 | **Sunil Shetye** | 33 | [![GitHub](https://img.shields.io/badge/-sunilshetye-181717?style=flat-square&logo=github)](https://github.com/sunilshetye) | Flatpak packaging, build system | +| 7 | **Anjali Jaiswal** | 35 | [![GitHub](https://img.shields.io/badge/-anjalijaiswal08-181717?style=flat-square&logo=github)](https://github.com/anjalijaiswal08) | Module development | +| 8 | **Hariom Thakur** | 28 | [![GitHub](https://img.shields.io/badge/-hariomthakur-181717?style=flat-square&logo=github)](https://github.com/hariomthakur) | Feature contributions | +| 9 | **Shanthi Priya** | 36 | [![GitHub](https://img.shields.io/badge/-Shanthipriya20-181717?style=flat-square&logo=github)](https://github.com/Shanthipriya20) | Module development | +| 10 | **Aditya Minocha** | 23 | [![GitHub](https://img.shields.io/badge/-adityaminocha-181717?style=flat-square&logo=github)](https://github.com/adityaminocha) | Feature contributions | +| 11 | **R. Krishnan** | 23 | [![GitHub](https://img.shields.io/badge/-rkrish00568-181717?style=flat-square&logo=github)](https://github.com/rkrish00568) | Feature development | +| 12 | **Ganderla Chaithanya** | 22 | [![GitHub](https://img.shields.io/badge/-GanderlaChaithanya-181717?style=flat-square&logo=github)](https://github.com/GanderlaChaithanya) | Module contributions | +| 13 | **Anwesha** | 21 | [![GitHub](https://img.shields.io/badge/-Anwesha06-181717?style=flat-square&logo=github)](https://github.com/Anwesha06) | Feature development | + +--- + +## 🥉 Active Contributors + +Contributors with **10–19 commits** who have made valuable and consistent contributions. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
Ankush

19 commits +
+
Anup Kumar Pandey

19 commits +
+
G Jaswanth

19 commits +
+
E Kamalesh

18 commits +
+
Sai Charan

18 commits +
+
Ajay Boddu

15 commits +
+
PSR

15 commits +
+
Komal Sheth

15 commits +
+
Athish I.S

15 commits +
+
Nishit Bayen

14 commits +
+
Suchinton

13 commits +
+
Karthick Naveen S

13 commits +
+
Sabarish Mohan

12 commits +
+
Harshal

11 commits +
+
D Tharun

11 commits +
+
Jovin P John

11 commits +
+
Madhav Krishnan

11 commits +
+
Ragul

11 commits +
+
Dilip Boidya

15 commits +
+
Jawwaad

10 commits +
+
Nirmitha N

10 commits +
+
Pavan

10 commits +
+
Senbagaseelan

10 commits +
+
Tanisha

10 commits +
+ +--- + +## 🌟 Community Contributors + +Every contribution counts — from single bug fixes to documentation improvements. Thank you to everyone listed below. + +
+📋 Contributors with 5–9 commits (click to expand) + +
+ +| Contributor | Commits | GitHub | +|:------------|:-------:|:------:| +| Maanit | 9 | [![GitHub](https://img.shields.io/badge/-Maanit-181717?style=flat-square&logo=github)](https://github.com/Maanit) | +| Myo Thinzar | 9 | [![GitHub](https://img.shields.io/badge/-Myo--Thinzar-181717?style=flat-square&logo=github)](https://github.com/Myo-Thinzar) | +| Partha Pratim Nath | 9 | [![GitHub](https://img.shields.io/badge/-parthapratimn-181717?style=flat-square&logo=github)](https://github.com/parthapratimn) | +| Sakhi Sharma | 9 | [![GitHub](https://img.shields.io/badge/-Sakhi1011-181717?style=flat-square&logo=github)](https://github.com/Sakhi1011) | +| Temshinaro Jamir | 9 | [![GitHub](https://img.shields.io/badge/-TemshinaroJamir-181717?style=flat-square&logo=github)](https://github.com/TemshinaroJamir) | +| Xoher | 9 | [![GitHub](https://img.shields.io/badge/-xoher-181717?style=flat-square&logo=github)](https://github.com/xoher) | +| Abhishek Shakya | 8 | [![GitHub](https://img.shields.io/badge/-AbhishekShakya-181717?style=flat-square&logo=github)](https://github.com/AbhishekShakya) | +| Aishwarya Sinha | 8 | [![GitHub](https://img.shields.io/badge/-AishwaryaSinha-181717?style=flat-square&logo=github)](https://github.com/AishwaryaSinha) | +| Aman Shukla | 8 | [![GitHub](https://img.shields.io/badge/-AmanShukla111-181717?style=flat-square&logo=github)](https://github.com/AmanShukla111) | +| Chandru | 8 | [![GitHub](https://img.shields.io/badge/-Chandru__136-181717?style=flat-square&logo=github)](https://github.com/Chandru136) | +| SAGARIKAA | 8 | [![GitHub](https://img.shields.io/badge/-SAGARIKAA760-181717?style=flat-square&logo=github)](https://github.com/SAGARIKAA760) | +| Sakshi Pandey | 8 | [![GitHub](https://img.shields.io/badge/-SakshiPandey-181717?style=flat-square&logo=github)](https://github.com/SakshiPandey) | +| Shaili Sahu | 8 | [![GitHub](https://img.shields.io/badge/-ShailiSahu-181717?style=flat-square&logo=github)](https://github.com/ShailiSahu) | +| Anish R. Khapare | 8 | [![GitHub](https://img.shields.io/badge/-anishrkhapare--bit-181717?style=flat-square&logo=github)](https://github.com/anishrkhapare-bit) | +| Deen Efil | 8 | [![GitHub](https://img.shields.io/badge/-deen--efil-181717?style=flat-square&logo=github)](https://github.com/deen-efil) | +| Priyanka | 8 | [![GitHub](https://img.shields.io/badge/-Priyanka-181717?style=flat-square&logo=github)](https://github.com/Priyanka) | +| Velugoti Ashok Kumar | 10 | [![GitHub](https://img.shields.io/badge/-velugotiashokkumar-181717?style=flat-square&logo=github)](https://github.com/velugotiashokkumar) | +| 092vk (Vivek Kumar) | 7 | [![GitHub](https://img.shields.io/badge/-092vk-181717?style=flat-square&logo=github)](https://github.com/092vk) | +| Bladen Martin | 7 | [![GitHub](https://img.shields.io/badge/-BladenMartin-181717?style=flat-square&logo=github)](https://github.com/BladenMartin) | +| Jay Mistry | 7 | [![GitHub](https://img.shields.io/badge/-mistryjay-181717?style=flat-square&logo=github)](https://github.com/mistryjay) | +| Vanshika Tanwar | 7 | [![GitHub](https://img.shields.io/badge/-VanshikaTanwar-181717?style=flat-square&logo=github)](https://github.com/VanshikaTanwar) | +| Varadha | 7 | [![GitHub](https://img.shields.io/badge/-VaradhaCodes-181717?style=flat-square&logo=github)](https://github.com/VaradhaCodes) | +| Suprraja | 7 | [![GitHub](https://img.shields.io/badge/-suprraja-181717?style=flat-square&logo=github)](https://github.com/suprraja) | +| Taeolis | 7 | [![GitHub](https://img.shields.io/badge/-taeolis-181717?style=flat-square&logo=github)](https://github.com/taeolis) | +| Arpit Sharma | 6 | [![GitHub](https://img.shields.io/badge/-ArpitSharma-181717?style=flat-square&logo=github)](https://github.com/ArpitSharma) | +| Gaurav Supal | 6 | [![GitHub](https://img.shields.io/badge/-GauravSupal-181717?style=flat-square&logo=github)](https://github.com/GauravSupal) | +| Jayanth | 6 | [![GitHub](https://img.shields.io/badge/-Jayanth--4547-181717?style=flat-square&logo=github)](https://github.com/Jayanth-4547) | +| Manimaran K | 6 | [![GitHub](https://img.shields.io/badge/-ManimaranK-181717?style=flat-square&logo=github)](https://github.com/ManimaranK) | +| Rachith H | 6 | [![GitHub](https://img.shields.io/badge/-Rachith--H-181717?style=flat-square&logo=github)](https://github.com/Rachith-H) | +| Tanay Mathur | 6 | [![GitHub](https://img.shields.io/badge/-TanayMathur-181717?style=flat-square&logo=github)](https://github.com/TanayMathur) | +| Maddy | 6 | [![GitHub](https://img.shields.io/badge/-maddy--2-181717?style=flat-square&logo=github)](https://github.com/maddy-2) | +| Abhishek Soni | 5 | [![GitHub](https://img.shields.io/badge/-Abhishek--Soni--25-181717?style=flat-square&logo=github)](https://github.com/Abhishek-Soni-25) | +| Barun | 5 | [![GitHub](https://img.shields.io/badge/-Barun-181717?style=flat-square&logo=github)](https://github.com/Barun) | +| Varad Patil | 5 | [![GitHub](https://img.shields.io/badge/-OfficialVarad-181717?style=flat-square&logo=github)](https://github.com/OfficialVarad) | +| Yash Kiran Ekhande | 5 | [![GitHub](https://img.shields.io/badge/-YashEkhande-181717?style=flat-square&logo=github)](https://github.com/YashEkhande) | +| Krishna Goutam | 5 | [![GitHub](https://img.shields.io/badge/-krishnaGoutam-181717?style=flat-square&logo=github)](https://github.com/krishnaGoutam) | +| Rohinthram | 5 | [![GitHub](https://img.shields.io/badge/-rohinthram-181717?style=flat-square&logo=github)](https://github.com/rohinthram) | + +
+ +
+📋 Contributors with 2–4 commits (click to expand) + +
+ +| Contributor | Commits | GitHub | +|:------------|:-------:|:------:| +| Akshay Rukade | 4 | [![GitHub](https://img.shields.io/badge/-AkshayRukade-181717?style=flat-square&logo=github)](https://github.com/AkshayRukade) | +| Vatsal Patel | 4 | [![GitHub](https://img.shields.io/badge/-PatelVatsalB21-181717?style=flat-square&logo=github)](https://github.com/PatelVatsalB21) | +| Anjali Jaiswal | 3 | [![GitHub](https://img.shields.io/badge/-AnjaliJaiswal-181717?style=flat-square&logo=github)](https://github.com/AnjaliJaiswal) | +| Ankur Gupta | 3 | [![GitHub](https://img.shields.io/badge/-ankur--gupta--29-181717?style=flat-square&logo=github)](https://github.com/ankur-gupta-29) | +| Anup Kumar Pandey | 3 | [![GitHub](https://img.shields.io/badge/-Anupkumarpandey1-181717?style=flat-square&logo=github)](https://github.com/Anupkumarpandey1) | +| E Balakrishna | 3 | [![GitHub](https://img.shields.io/badge/-EBalakrishna-181717?style=flat-square&logo=github)](https://github.com/EBalakrishna) | +| Gaurav Gupta | 3 | [![GitHub](https://img.shields.io/badge/-gauravgupta654-181717?style=flat-square&logo=github)](https://github.com/gauravgupta654) | +| Harshit Singh Negi | 3 | [![GitHub](https://img.shields.io/badge/-demon2202-181717?style=flat-square&logo=github)](https://github.com/demon2202) | +| Pranav Karuvally | 3 | [![GitHub](https://img.shields.io/badge/-theunixdisaster-181717?style=flat-square&logo=github)](https://github.com/theunixdisaster) | +| Saurabh Bansode | 3 | [![GitHub](https://img.shields.io/badge/-saurabhb17-181717?style=flat-square&logo=github)](https://github.com/saurabhb17) | +| Abinash Singh | 2 | [![GitHub](https://img.shields.io/badge/-avinashlalotra-181717?style=flat-square&logo=github)](https://github.com/avinashlalotra) | +| Harvi | 2 | [![GitHub](https://img.shields.io/badge/-Harvi--2215-181717?style=flat-square&logo=github)](https://github.com/Harvi-2215) | +| Kavya Manohar | 2 | [![GitHub](https://img.shields.io/badge/-KavyaManohar-181717?style=flat-square&logo=github)](https://github.com/KavyaManohar) | +| Pyae Sone | 2 | [![GitHub](https://img.shields.io/badge/-Autumn--21-181717?style=flat-square&logo=github)](https://github.com/Autumn-21) | +| S. Shiva Krishna Reddy | 2 | [![GitHub](https://img.shields.io/badge/-Shiva0krishna-181717?style=flat-square&logo=github)](https://github.com/Shiva0krishna) | +| Sangavi GR | 2 | [![GitHub](https://img.shields.io/badge/-SangaviGR-181717?style=flat-square&logo=github)](https://github.com/SangaviGR) | +| Vivek Kumar | 2 | [![GitHub](https://img.shields.io/badge/-092vk-181717?style=flat-square&logo=github)](https://github.com/092vk) | +| Manasi Yadav | 2 | [![GitHub](https://img.shields.io/badge/-manasiyadav-181717?style=flat-square&logo=github)](https://github.com/manasiyadav) | + +
+ +
+📋 Contributors with 1 commit (click to expand) + +
+ +| Contributor | GitHub | +|:------------|:------:| +| Aditya Bhattacharya | [![GitHub](https://img.shields.io/badge/-ADITYA--BHATTACHARYA--DEV-181717?style=flat-square&logo=github)](https://github.com/ADITYA-BHATTACHARYA-DEV) | +| Abhishek Soni | [![GitHub](https://img.shields.io/badge/-Abhishek--Soni--25-181717?style=flat-square&logo=github)](https://github.com/Abhishek-Soni-25) | +| Ashwith Rego | [![GitHub](https://img.shields.io/badge/-ashwith-181717?style=flat-square&logo=github)](https://github.com/ashwith) | +| Athul George | [![GitHub](https://img.shields.io/badge/-athulappadan-181717?style=flat-square&logo=github)](https://github.com/athulappadan) | +| Boddu Ajay | [![GitHub](https://img.shields.io/badge/-ajayboddu--2006-181717?style=flat-square&logo=github)](https://github.com/ajayboddu-2006) | +| Charaan | [![GitHub](https://img.shields.io/badge/-Charaan-181717?style=flat-square&logo=github)](https://github.com/Charaan) | +| GiGi Koneti | [![GitHub](https://img.shields.io/badge/-GiGiKoneti-181717?style=flat-square&logo=github)](https://github.com/GiGiKoneti) | +| Keerthana | [![GitHub](https://img.shields.io/badge/-Keerthana-181717?style=flat-square&logo=github)](https://github.com/Keerthana) | +| Kusum Kisori | [![GitHub](https://img.shields.io/badge/-KusumKisori-181717?style=flat-square&logo=github)](https://github.com/KusumKisori) | +| Mausam | [![GitHub](https://img.shields.io/badge/-Mausam5055-181717?style=flat-square&logo=github)](https://github.com/Mausam5055) | +| Mudit Joshi | [![GitHub](https://img.shields.io/badge/-MuditJoshi-181717?style=flat-square&logo=github)](https://github.com/MuditJoshi) | +| Naman Patel | [![GitHub](https://img.shields.io/badge/-NamanPatel-181717?style=flat-square&logo=github)](https://github.com/NamanPatel) | +| Varad Patil | [![GitHub](https://img.shields.io/badge/-OfficialVarad-181717?style=flat-square&logo=github)](https://github.com/OfficialVarad) | +| Pavan Mantri | [![GitHub](https://img.shields.io/badge/-PavanMantri-181717?style=flat-square&logo=github)](https://github.com/PavanMantri) | +| Pavithra W | [![GitHub](https://img.shields.io/badge/-Pavithraw24-181717?style=flat-square&logo=github)](https://github.com/Pavithraw24) | +| Raksha Dave | [![GitHub](https://img.shields.io/badge/-RakshaDave-181717?style=flat-square&logo=github)](https://github.com/RakshaDave) | +| Rudra Mani Upadhyay | [![GitHub](https://img.shields.io/badge/-Rudramani1-181717?style=flat-square&logo=github)](https://github.com/Rudramani1) | +| Shravan A Y | [![GitHub](https://img.shields.io/badge/-ShravanAY-181717?style=flat-square&logo=github)](https://github.com/ShravanAY) | +| Vikas Mulaje | [![GitHub](https://img.shields.io/badge/-VikasMulaje-181717?style=flat-square&logo=github)](https://github.com/VikasMulaje) | +| Aamir Thekiya | [![GitHub](https://img.shields.io/badge/-aamirthekiya-181717?style=flat-square&logo=github)](https://github.com/aamirthekiya) | +| Bhavya Bhardwaj | [![GitHub](https://img.shields.io/badge/-bhavyabhardwaj001-181717?style=flat-square&logo=github)](https://github.com/bhavyabhardwaj001) | +| Mahak Gupta | [![GitHub](https://img.shields.io/badge/-mahakgupta0123-181717?style=flat-square&logo=github)](https://github.com/mahakgupta0123) | +| Nuh Too Wai | [![GitHub](https://img.shields.io/badge/-nuhtoowai-181717?style=flat-square&logo=github)](https://github.com/nuhtoowai) | + +
+ +--- + +## 📊 Contribution Statistics + +| Metric | Value | +|:-------|:------| +| **Total Contributors** | 149+ | +| **Total Commits** | 2,400+ | +| **Project Age** | Since February 2015 (10+ years) | +| **License** | GNU GPL v3.0 | +| **Active Branches** | `master` (main), `installers`, feature branches | + +### Contributor Growth Over Time + +``` +2015 ██░░░░░░░░░░░░░░░░░░ Project founded by Fahim Khan +2016 ████░░░░░░░░░░░░░░░░ Core team (Fahim, Rahul) establishes architecture +2017 ██████░░░░░░░░░░░░░░ NGHDL integration, community grows +2018 ████████░░░░░░░░░░░░ Saurabh, Nil, Athul join; converter modules added +2019 ██████████░░░░░░░░░░ PyQt migration, model editor expansion +2020 ████████████░░░░░░░░ Sumanto Kar becomes lead; Makerchip integration +2021 ██████████████░░░░░░ SKY130 PDK, NgVeri, major feature wave +2022 ████████████████░░░░ Flatpak packaging, Docker support, PyQt6 migration +2023 ██████████████████░░ IHP PDK, schematic converters, 100+ contributors +2024 ████████████████████ Community-driven enhancements, 149+ contributors +``` + +--- + +## 🙌 How to Get Listed + +Anyone who contributes to the eSim codebase is automatically listed here! Ways to contribute: + +- 🐛 **Bug Fixes** — Find and fix issues in the [issue tracker](https://github.com/fossee/esim/issues) +- ✨ **Features** — Implement new features or enhance existing ones +- 📝 **Documentation** — Improve docs, comments, or tutorials +- 🧪 **Testing** — Add tests or report bugs with reproducible steps +- 🎨 **UI/UX** — Improve the user interface and experience +- 🌐 **Translations** — Help localize eSim for different languages +- 📦 **Packaging** — Help with Flatpak, Snap, AppImage, or Docker builds +- 📚 **Examples** — Add new example circuits to the `Examples/` directory + +See [CONTRIBUTION.md](CONTRIBUTION.md) for step-by-step instructions. + +--- + +## 🖼️ All Contributors Mosaic + +

+ + All Contributors + +

+ +

+ Auto-generated via contrib.rocks — shows GitHub avatar for every contributor +

+ +--- + +

+ Thank you to every single contributor who has made eSim possible! ❤️
+ This file is maintained alongside the project. If your contribution is missing, please open an issue. +

+ +

+ FOSSEE Logo +      + IIT Bombay Logo +

From 534c2054d4b85efd61a4bac8c08351102cb0eea9 Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 21:30:39 +0530 Subject: [PATCH 03/19] Update README.md --- README.md | 34 ++++++++++++---------------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/README.md b/README.md index 819cd389a..9ef2c689b 100644 --- a/README.md +++ b/README.md @@ -527,27 +527,14 @@ For detailed contribution guidelines, see [CONTRIBUTION.md](CONTRIBUTION.md). --- -## 👥 Top Contributors - -A huge thank you to all the amazing people who have contributed to eSim! 🎉 - -| # | Contributor | Commits | GitHub Profile | -|:-:|:------------|:-------:|:---------------| -| 🥇 | **Sumanto Kar** | 280 | [![GitHub](https://img.shields.io/badge/-Eyantra698Sumanto-181717?style=flat-square&logo=github)](https://github.com/Eyantra698Sumanto) | -| 🥈 | **Rahul Paknikar** | 262 | [![GitHub](https://img.shields.io/badge/-rahulp13-181717?style=flat-square&logo=github)](https://github.com/rahulp13) | -| 🥉 | **Fahim Khan** | 244 | [![GitHub](https://img.shields.io/badge/-fahim--eSim-181717?style=flat-square&logo=github)](https://github.com/fahim-oscad) | -| 4 | **Saurabh Bansod** | 46 | [![GitHub](https://img.shields.io/badge/-saurabhb17-181717?style=flat-square&logo=github)](https://github.com/saurabhb17) | -| 5 | **Athul George** | 37 | [![GitHub](https://img.shields.io/badge/-athulappadan-181717?style=flat-square&logo=github)](https://github.com/athulappadan) | -| 6 | **Nil Shah** | 36 | [![GitHub](https://img.shields.io/badge/-nilshah98-181717?style=flat-square&logo=github)](https://github.com/nilshah98) | -| 7 | **Pranav P** | 34 | [![GitHub](https://img.shields.io/badge/-pranavsdreams-181717?style=flat-square&logo=github)](https://github.com/pranavsdreams) | -| 8 | **Annesha Dey** | 33 | [![GitHub](https://img.shields.io/badge/-AD20047-181717?style=flat-square&logo=github)](https://github.com/AD20047) | -| 9 | **Sunil Shetye** | 33 | [![GitHub](https://img.shields.io/badge/-sunilshetye-181717?style=flat-square&logo=github)](https://github.com/sunilshetye) | -| 10 | **Anjali Jaiswal** | 32 | [![GitHub](https://img.shields.io/badge/-anjalijaiswal08-181717?style=flat-square&logo=github)](https://github.com/anjalijaiswal08) | -| 11 | **Hariom Thakur** | 28 | [![GitHub](https://img.shields.io/badge/-hariom-181717?style=flat-square&logo=github)](https://github.com/hariom) | -| 12 | **Shanthi Priya** | 24 | [![GitHub](https://img.shields.io/badge/-shanthipriya-181717?style=flat-square&logo=github)](https://github.com/shanthipriya) | -| 13 | **Aditya Minocha** | 23 | [![GitHub](https://img.shields.io/badge/-adityaminocha-181717?style=flat-square&logo=github)](https://github.com/adityaminocha) | -| 14 | **Ganderla Chaithanya** | 22 | [![GitHub](https://img.shields.io/badge/-GanderlaChaithanya-181717?style=flat-square&logo=github)](https://github.com/GanderlaChaithanya) | -| 15 | **Anwesha** | 21 | [![GitHub](https://img.shields.io/badge/-Anwesha06-181717?style=flat-square&logo=github)](https://github.com/Anwesha06) | +## 👥 Contributors + +A huge thank you to all **149+ amazing people** who have contributed to eSim! 🎉 + +| 🥇 Core Maintainer | 🥈 Core Maintainer | 🥉 Core Maintainer | +|:---:|:---:|:---:| +| [![Sumanto Kar](https://github.com/Eyantra698Sumanto.png?size=80)](https://github.com/Eyantra698Sumanto) | [![Rahul Paknikar](https://github.com/rahulp13.png?size=80)](https://github.com/rahulp13) | [![Fahim Khan](https://github.com/fahim-oscad.png?size=80)](https://github.com/fahim-oscad) | +| **Sumanto Kar** · 320 commits | **Rahul Paknikar** · 265 commits | **Fahim Khan** · 244 commits |

@@ -555,7 +542,10 @@ A huge thank you to all the amazing people who have contributed to eSim! 🎉

-

149+ contributors and counting! View all →

+

+ 📋 View the full Contributors page →
+ Complete list with profiles, commit counts, and contribution tiers for all 149+ contributors +

--- From 18e2eada77535afc63d1c95ceb8380c8dab2056d Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 21:38:20 +0530 Subject: [PATCH 04/19] commit --- CONTRIBUTING.md | 249 +++++++++++++++++++++++++++++++++ CONTRIBUTION.md | 24 ---- CONTRIBUTORS.md | 364 ------------------------------------------------ 3 files changed, 249 insertions(+), 388 deletions(-) create mode 100644 CONTRIBUTING.md delete mode 100644 CONTRIBUTION.md delete mode 100644 CONTRIBUTORS.md diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md new file mode 100644 index 000000000..4dc1f4459 --- /dev/null +++ b/CONTRIBUTING.md @@ -0,0 +1,249 @@ +# Contributing to eSim + +Thank you for your interest in contributing to **eSim**! 🎉 +Every contribution — whether it's a bug fix, new feature, documentation improvement, or example circuit — helps make eSim better for everyone. + +

+ Open Issues + Open PRs + Contributors +

+ +--- + +## 📋 Table of Contents + +- [Getting Started](#-getting-started) +- [Ways to Contribute](#-ways-to-contribute) +- [Development Setup](#-development-setup) +- [Pull Request Workflow](#-pull-request-workflow) +- [Commit Guidelines](#-commit-guidelines) +- [Code Style](#-code-style) +- [Reporting Bugs](#-reporting-bugs) +- [Requesting Features](#-requesting-features) +- [Community](#-community) + +--- + +## 🚀 Getting Started + +1. **Find an issue** — Browse the [issue tracker](https://github.com/fossee/esim/issues) for bugs or features you'd like to work on +2. **Claim it** — Comment on the issue with *"I would like to work on this"* so maintainers can assign it to you +3. **Fork & code** — Follow the [Pull Request Workflow](#-pull-request-workflow) below +4. **Submit a PR** — Every pull request **must reference an issue** + +> **💡 First-time contributor?** Look for issues labeled [`good first issue`](https://github.com/fossee/esim/labels/good%20first%20issue) — these are beginner-friendly tasks curated by maintainers. + +--- + +## 🤝 Ways to Contribute + +| Type | Description | Difficulty | +|:-----|:------------|:----------:| +| 🐛 **Bug Fixes** | Fix reported issues from the [issue tracker](https://github.com/fossee/esim/issues) | ⭐ – ⭐⭐ | +| ✨ **New Features** | Implement new functionality or enhance existing modules | ⭐⭐ – ⭐⭐⭐ | +| 📝 **Documentation** | Improve docs, docstrings, README, or Sphinx docs in `docs/` | ⭐ | +| 🧪 **Testing** | Add test cases or report bugs with reproducible steps | ⭐ – ⭐⭐ | +| 🎨 **UI/UX** | Improve the PyQt6 user interface and user experience | ⭐⭐ | +| 📚 **Examples** | Add new example circuits to the `Examples/` directory | ⭐ | +| 📦 **Packaging** | Help with Flatpak, Snap, AppImage, or Docker builds | ⭐⭐⭐ | +| 🌐 **Integration** | Improve KiCad, Ngspice, GHDL, or Makerchip integration | ⭐⭐⭐ | + +--- + +## 🔧 Development Setup + +### Prerequisites + +| Tool | Version | Purpose | +|:-----|:--------|:--------| +| Python | 3.6+ | Core application runtime | +| PyQt6 | ≥ 6.5.0 | GUI framework | +| KiCad | Latest | Schematic & PCB editor | +| Ngspice | 35+ | Circuit simulation engine | +| Git | Latest | Version control | + +### Setup Steps + +```bash +# 1. Fork the repository on GitHub, then clone your fork +git clone https://github.com//eSim.git +cd eSim + +# 2. Install Python dependencies +pip install -r requirements.txt + +# 3. (Optional) Install additional tools for full functionality +# See INSTALL file for KiCad, Ngspice, and GHDL setup +``` + +--- + +## 📬 Pull Request Workflow + +```mermaid +flowchart LR + A["🍴 Fork"] --> B["🌿 Branch"] + B --> C["💻 Code"] + C --> D["✅ Commit"] + D --> E["⬆️ Push"] + E --> F["📬 PR"] + + style A fill:#6c5ce7,color:#fff + style B fill:#00b894,color:#fff + style C fill:#0984e3,color:#fff + style D fill:#fdcb6e,color:#333 + style E fill:#e17055,color:#fff + style F fill:#d63031,color:#fff +``` + +### Step-by-Step + +**1. Fork & Clone** + +```bash +# Fork via GitHub UI, then: +git clone https://github.com//eSim.git +cd eSim +``` + +**2. Create a Feature Branch** + +```bash +# Always branch from master — never commit directly to master +git checkout -b fix/issue-42-rectifier-bug +``` + +> **Branch naming convention:** +> - `fix/issue--short-description` — for bug fixes +> - `feature/issue--short-description` — for new features +> - `docs/short-description` — for documentation changes + +**3. Make Your Changes** + +- Write clean, well-commented code +- Follow the [Code Style](#-code-style) guidelines +- Test your changes locally + +**4. Commit Your Changes** + +```bash +git add +git commit -m "Fixes issue #42 - Fix half-wave rectifier simulation error" +``` + +> ⚠️ **One commit per pull request.** If you have multiple commits, squash them before submitting. + +**5. Push & Open a PR** + +```bash +git push origin fix/issue-42-rectifier-bug +``` + +Then open a Pull Request on GitHub targeting the `master` branch. + +--- + +## 📝 Commit Guidelines + +### Commit Message Format + +``` +Fixes issue # - + + +- What was the problem? +- What did you change? +- Why this approach? +``` + +### Examples + +``` +Fixes issue #42 - Fix AC analysis crash when frequency range is empty + +The AC analysis module threw an unhandled exception when the user +left the frequency range fields blank. Added input validation in +Analysis.py to show an error dialog instead of crashing. +``` + +``` +Fixes issue #87 - Add 4-bit counter example circuit + +Added a new example project under Examples/4_bit_counter with +schematic, netlist, and simulation configuration files. +``` + +### Rules + +| Rule | Details | +|:-----|:--------| +| **Reference an issue** | Every PR must link to an existing GitHub issue | +| **One commit per PR** | Squash multiple commits before submitting | +| **Clear subject line** | Format: `Fixes issue #N - Brief description` | +| **Add a body** | Explain *what* you changed and *why* | + +--- + +## 🎨 Code Style + +eSim follows **[PEP 8](https://www.python.org/dev/peps/pep-0008/)** — the Python community's style guide. + +| Rule | Details | +|:-----|:--------| +| **Style** | PEP 8 compliant | +| **Indentation** | 4 spaces (no tabs) | +| **Line length** | Max 79 characters | +| **Docstrings** | Required for all public functions and classes | +| **Imports** | Group by stdlib → third-party → local; one per line | +| **Naming** | `snake_case` for functions/variables, `PascalCase` for classes | + +### Linting + +```bash +# Check your code before submitting +flake8 src/ +``` + +--- + +## 🐛 Reporting Bugs + +Found a bug? Please [open an issue](https://github.com/fossee/esim/issues/new) with: + +1. **Title** — Clear, concise summary of the problem +2. **Environment** — OS, Python version, eSim version +3. **Steps to reproduce** — Exact steps to trigger the bug +4. **Expected behavior** — What should happen +5. **Actual behavior** — What actually happens +6. **Screenshots/Logs** — If applicable, attach console output or screenshots + +--- + +## 💡 Requesting Features + +Have an idea for a new feature? [Open an issue](https://github.com/fossee/esim/issues/new) with: + +1. **Title** — Prefix with `[Feature Request]` +2. **Problem** — What problem does this solve? +3. **Proposed solution** — How should it work? +4. **Alternatives considered** — Any other approaches you thought of? +5. **Additional context** — Mockups, references, or related issues + +--- + +## 💬 Community + +| Channel | Link | +|:--------|:-----| +| 📧 **Email** | [contact-esim@fossee.in](mailto:contact-esim@fossee.in) | +| 💬 **Forum** | [forums.fossee.in](https://forums.fossee.in/) | +| 🌐 **Website** | [esim.fossee.in](https://esim.fossee.in/) | +| 📚 **Dev Docs** | [esim.readthedocs.io](https://esim.readthedocs.io/en/latest/) | + +--- + +

+ Thank you for contributing to eSim! ❤️
+ Every contribution, no matter how small, makes a difference. +

diff --git a/CONTRIBUTION.md b/CONTRIBUTION.md deleted file mode 100644 index ce6338b78..000000000 --- a/CONTRIBUTION.md +++ /dev/null @@ -1,24 +0,0 @@ -## Contribution -If you want to add any enhancement feature or have found any bug and want to work on it, please open a new issue regarding that and put a message "I would like to work on it." And make sure every pull request should reference to an issue. - -#### Points on how to make pull request -* You need to fork this repository to your account. - -* Clone it using ``` git clone https://github.com/FOSSEE/eSim.git ``` - -* Always create a new branch before making any changes. You can create new branch using ```git branch ``` - -* Checkout into your new branch using ```git checkout ``` - -* Make changes to code and once you are done use ```git add ```. Now commit changes with proper message using ```git commit -m "Your message"```. - -* After commiting your changes push your changes to your forked repository using ```git push origin ``` -Finally create a pull request from github. -There should be only one commit per pull request. - - -* Please follow below guidelines for your commit message : - * Commit message should be like : Fixes issue #[issue_number] - one line message of work you did. - * After commit message, there should be a commit body where you can mention what you did in short or in detail. - -Please follow above method to file pull requests. diff --git a/CONTRIBUTORS.md b/CONTRIBUTORS.md deleted file mode 100644 index edc788eb8..000000000 --- a/CONTRIBUTORS.md +++ /dev/null @@ -1,364 +0,0 @@ -

- eSim Logo -

- -

🏆 eSim Contributors

- -

- Honoring the people who built eSim — since February 2015
- An open-source EDA tool by FOSSEE at IIT Bombay -

- -

- Contributors - Total Commits - Stars - PRs Welcome -

- ---- - -eSim is built by a vibrant community of **149+ contributors** — students, researchers, engineers, and open-source enthusiasts from around the world. This page recognizes everyone who has contributed code, documentation, bug fixes, and features to the project since its first commit on **February 5, 2015**. - ---- - -## 🏛️ Project Leads & Organization - -| Role | Name | Affiliation | -|:-----|:-----|:------------| -| **Developed by** | [FOSSEE Team](https://www.fossee.in/) | IIT Bombay | -| **Original Author** | Fahim Khan | eSim / FOSSEE, IIT Bombay | -| **Lead Maintainer** | Sumanto Kar | FOSSEE, IIT Bombay | -| **Core Maintainer** | Rahul Paknikar | FOSSEE, IIT Bombay | -| **Core Maintainer** | Pranav P | FOSSEE, IIT Bombay | - ---- - -## 🥇 Core Maintainers - -These individuals have made sustained, foundational contributions to eSim's architecture, features, and long-term maintenance. - - - - - - - -
- - Sumanto Kar
- Sumanto Kar -

- 320 commits
- GitHub -
- - Rahul Paknikar
- Rahul Paknikar -

- 265 commits
- GitHub -
- - Fahim Khan
- Fahim Khan -

- 244 commits
- GitHub -
- ---- - -## 🥈 Major Contributors - -Contributors with **20+ commits** who have made significant impact on major features, modules, or subsystems. - -| # | Contributor | Commits | GitHub | Key Contributions | -|:-:|:------------|:-------:|:------:|:------------------| -| 1 | **Saurabh Bansode** | 49 | [![GitHub](https://img.shields.io/badge/-saurabhb17-181717?style=flat-square&logo=github)](https://github.com/saurabhb17) | Schematic converters, KiCad integration | -| 2 | **Athul George** | 37 | [![GitHub](https://img.shields.io/badge/-athulappadan-181717?style=flat-square&logo=github)](https://github.com/athulappadan) | Frontend, project management | -| 3 | **Nil Shah** | 36 | [![GitHub](https://img.shields.io/badge/-nilshah98-181717?style=flat-square&logo=github)](https://github.com/nilshah98) | Core modules, simulation engine | -| 4 | **Pranav P** | 34 | [![GitHub](https://img.shields.io/badge/-pranavsdreams-181717?style=flat-square&logo=github)](https://github.com/pranavsdreams) | Application UI, maintenance | -| 5 | **Annesha Dey** | 33 | [![GitHub](https://img.shields.io/badge/-AD20047-181717?style=flat-square&logo=github)](https://github.com/AD20047) | Feature development | -| 6 | **Sunil Shetye** | 33 | [![GitHub](https://img.shields.io/badge/-sunilshetye-181717?style=flat-square&logo=github)](https://github.com/sunilshetye) | Flatpak packaging, build system | -| 7 | **Anjali Jaiswal** | 35 | [![GitHub](https://img.shields.io/badge/-anjalijaiswal08-181717?style=flat-square&logo=github)](https://github.com/anjalijaiswal08) | Module development | -| 8 | **Hariom Thakur** | 28 | [![GitHub](https://img.shields.io/badge/-hariomthakur-181717?style=flat-square&logo=github)](https://github.com/hariomthakur) | Feature contributions | -| 9 | **Shanthi Priya** | 36 | [![GitHub](https://img.shields.io/badge/-Shanthipriya20-181717?style=flat-square&logo=github)](https://github.com/Shanthipriya20) | Module development | -| 10 | **Aditya Minocha** | 23 | [![GitHub](https://img.shields.io/badge/-adityaminocha-181717?style=flat-square&logo=github)](https://github.com/adityaminocha) | Feature contributions | -| 11 | **R. Krishnan** | 23 | [![GitHub](https://img.shields.io/badge/-rkrish00568-181717?style=flat-square&logo=github)](https://github.com/rkrish00568) | Feature development | -| 12 | **Ganderla Chaithanya** | 22 | [![GitHub](https://img.shields.io/badge/-GanderlaChaithanya-181717?style=flat-square&logo=github)](https://github.com/GanderlaChaithanya) | Module contributions | -| 13 | **Anwesha** | 21 | [![GitHub](https://img.shields.io/badge/-Anwesha06-181717?style=flat-square&logo=github)](https://github.com/Anwesha06) | Feature development | - ---- - -## 🥉 Active Contributors - -Contributors with **10–19 commits** who have made valuable and consistent contributions. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-
Ankush

19 commits -
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Anup Kumar Pandey

19 commits -
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G Jaswanth

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E Kamalesh

18 commits -
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Sai Charan

18 commits -
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Ajay Boddu

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PSR

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Komal Sheth

15 commits -
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Athish I.S

15 commits -
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Nishit Bayen

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Suchinton

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Karthick Naveen S

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Sabarish Mohan

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Harshal

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Nirmitha N

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Pavan

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Tanisha

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- ---- - -## 🌟 Community Contributors - -Every contribution counts — from single bug fixes to documentation improvements. Thank you to everyone listed below. - -
-📋 Contributors with 5–9 commits (click to expand) - -
- -| Contributor | Commits | GitHub | -|:------------|:-------:|:------:| -| Maanit | 9 | [![GitHub](https://img.shields.io/badge/-Maanit-181717?style=flat-square&logo=github)](https://github.com/Maanit) | -| Myo Thinzar | 9 | [![GitHub](https://img.shields.io/badge/-Myo--Thinzar-181717?style=flat-square&logo=github)](https://github.com/Myo-Thinzar) | -| Partha Pratim Nath | 9 | [![GitHub](https://img.shields.io/badge/-parthapratimn-181717?style=flat-square&logo=github)](https://github.com/parthapratimn) | -| Sakhi Sharma | 9 | [![GitHub](https://img.shields.io/badge/-Sakhi1011-181717?style=flat-square&logo=github)](https://github.com/Sakhi1011) | -| Temshinaro Jamir | 9 | [![GitHub](https://img.shields.io/badge/-TemshinaroJamir-181717?style=flat-square&logo=github)](https://github.com/TemshinaroJamir) | -| Xoher | 9 | [![GitHub](https://img.shields.io/badge/-xoher-181717?style=flat-square&logo=github)](https://github.com/xoher) | -| Abhishek Shakya | 8 | [![GitHub](https://img.shields.io/badge/-AbhishekShakya-181717?style=flat-square&logo=github)](https://github.com/AbhishekShakya) | -| Aishwarya Sinha | 8 | [![GitHub](https://img.shields.io/badge/-AishwaryaSinha-181717?style=flat-square&logo=github)](https://github.com/AishwaryaSinha) | -| Aman Shukla | 8 | [![GitHub](https://img.shields.io/badge/-AmanShukla111-181717?style=flat-square&logo=github)](https://github.com/AmanShukla111) | -| Chandru | 8 | [![GitHub](https://img.shields.io/badge/-Chandru__136-181717?style=flat-square&logo=github)](https://github.com/Chandru136) | -| SAGARIKAA | 8 | [![GitHub](https://img.shields.io/badge/-SAGARIKAA760-181717?style=flat-square&logo=github)](https://github.com/SAGARIKAA760) | -| Sakshi Pandey | 8 | [![GitHub](https://img.shields.io/badge/-SakshiPandey-181717?style=flat-square&logo=github)](https://github.com/SakshiPandey) | -| Shaili Sahu | 8 | [![GitHub](https://img.shields.io/badge/-ShailiSahu-181717?style=flat-square&logo=github)](https://github.com/ShailiSahu) | -| Anish R. Khapare | 8 | [![GitHub](https://img.shields.io/badge/-anishrkhapare--bit-181717?style=flat-square&logo=github)](https://github.com/anishrkhapare-bit) | -| Deen Efil | 8 | [![GitHub](https://img.shields.io/badge/-deen--efil-181717?style=flat-square&logo=github)](https://github.com/deen-efil) | -| Priyanka | 8 | [![GitHub](https://img.shields.io/badge/-Priyanka-181717?style=flat-square&logo=github)](https://github.com/Priyanka) | -| Velugoti Ashok Kumar | 10 | [![GitHub](https://img.shields.io/badge/-velugotiashokkumar-181717?style=flat-square&logo=github)](https://github.com/velugotiashokkumar) | -| 092vk (Vivek Kumar) | 7 | [![GitHub](https://img.shields.io/badge/-092vk-181717?style=flat-square&logo=github)](https://github.com/092vk) | -| Bladen Martin | 7 | [![GitHub](https://img.shields.io/badge/-BladenMartin-181717?style=flat-square&logo=github)](https://github.com/BladenMartin) | -| Jay Mistry | 7 | [![GitHub](https://img.shields.io/badge/-mistryjay-181717?style=flat-square&logo=github)](https://github.com/mistryjay) | -| Vanshika Tanwar | 7 | [![GitHub](https://img.shields.io/badge/-VanshikaTanwar-181717?style=flat-square&logo=github)](https://github.com/VanshikaTanwar) | -| Varadha | 7 | [![GitHub](https://img.shields.io/badge/-VaradhaCodes-181717?style=flat-square&logo=github)](https://github.com/VaradhaCodes) | -| Suprraja | 7 | [![GitHub](https://img.shields.io/badge/-suprraja-181717?style=flat-square&logo=github)](https://github.com/suprraja) | -| Taeolis | 7 | [![GitHub](https://img.shields.io/badge/-taeolis-181717?style=flat-square&logo=github)](https://github.com/taeolis) | -| Arpit Sharma | 6 | [![GitHub](https://img.shields.io/badge/-ArpitSharma-181717?style=flat-square&logo=github)](https://github.com/ArpitSharma) | -| Gaurav Supal | 6 | [![GitHub](https://img.shields.io/badge/-GauravSupal-181717?style=flat-square&logo=github)](https://github.com/GauravSupal) | -| Jayanth | 6 | [![GitHub](https://img.shields.io/badge/-Jayanth--4547-181717?style=flat-square&logo=github)](https://github.com/Jayanth-4547) | -| Manimaran K | 6 | [![GitHub](https://img.shields.io/badge/-ManimaranK-181717?style=flat-square&logo=github)](https://github.com/ManimaranK) | -| Rachith H | 6 | [![GitHub](https://img.shields.io/badge/-Rachith--H-181717?style=flat-square&logo=github)](https://github.com/Rachith-H) | -| Tanay Mathur | 6 | [![GitHub](https://img.shields.io/badge/-TanayMathur-181717?style=flat-square&logo=github)](https://github.com/TanayMathur) | -| Maddy | 6 | [![GitHub](https://img.shields.io/badge/-maddy--2-181717?style=flat-square&logo=github)](https://github.com/maddy-2) | -| Abhishek Soni | 5 | [![GitHub](https://img.shields.io/badge/-Abhishek--Soni--25-181717?style=flat-square&logo=github)](https://github.com/Abhishek-Soni-25) | -| Barun | 5 | [![GitHub](https://img.shields.io/badge/-Barun-181717?style=flat-square&logo=github)](https://github.com/Barun) | -| Varad Patil | 5 | [![GitHub](https://img.shields.io/badge/-OfficialVarad-181717?style=flat-square&logo=github)](https://github.com/OfficialVarad) | -| Yash Kiran Ekhande | 5 | [![GitHub](https://img.shields.io/badge/-YashEkhande-181717?style=flat-square&logo=github)](https://github.com/YashEkhande) | -| Krishna Goutam | 5 | [![GitHub](https://img.shields.io/badge/-krishnaGoutam-181717?style=flat-square&logo=github)](https://github.com/krishnaGoutam) | -| Rohinthram | 5 | [![GitHub](https://img.shields.io/badge/-rohinthram-181717?style=flat-square&logo=github)](https://github.com/rohinthram) | - -
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-📋 Contributors with 2–4 commits (click to expand) - -
- -| Contributor | Commits | GitHub | -|:------------|:-------:|:------:| -| Akshay Rukade | 4 | [![GitHub](https://img.shields.io/badge/-AkshayRukade-181717?style=flat-square&logo=github)](https://github.com/AkshayRukade) | -| Vatsal Patel | 4 | [![GitHub](https://img.shields.io/badge/-PatelVatsalB21-181717?style=flat-square&logo=github)](https://github.com/PatelVatsalB21) | -| Anjali Jaiswal | 3 | [![GitHub](https://img.shields.io/badge/-AnjaliJaiswal-181717?style=flat-square&logo=github)](https://github.com/AnjaliJaiswal) | -| Ankur Gupta | 3 | [![GitHub](https://img.shields.io/badge/-ankur--gupta--29-181717?style=flat-square&logo=github)](https://github.com/ankur-gupta-29) | -| Anup Kumar Pandey | 3 | [![GitHub](https://img.shields.io/badge/-Anupkumarpandey1-181717?style=flat-square&logo=github)](https://github.com/Anupkumarpandey1) | -| E Balakrishna | 3 | [![GitHub](https://img.shields.io/badge/-EBalakrishna-181717?style=flat-square&logo=github)](https://github.com/EBalakrishna) | -| Gaurav Gupta | 3 | [![GitHub](https://img.shields.io/badge/-gauravgupta654-181717?style=flat-square&logo=github)](https://github.com/gauravgupta654) | -| Harshit Singh Negi | 3 | [![GitHub](https://img.shields.io/badge/-demon2202-181717?style=flat-square&logo=github)](https://github.com/demon2202) | -| Pranav Karuvally | 3 | [![GitHub](https://img.shields.io/badge/-theunixdisaster-181717?style=flat-square&logo=github)](https://github.com/theunixdisaster) | -| Saurabh Bansode | 3 | [![GitHub](https://img.shields.io/badge/-saurabhb17-181717?style=flat-square&logo=github)](https://github.com/saurabhb17) | -| Abinash Singh | 2 | [![GitHub](https://img.shields.io/badge/-avinashlalotra-181717?style=flat-square&logo=github)](https://github.com/avinashlalotra) | -| Harvi | 2 | [![GitHub](https://img.shields.io/badge/-Harvi--2215-181717?style=flat-square&logo=github)](https://github.com/Harvi-2215) | -| Kavya Manohar | 2 | [![GitHub](https://img.shields.io/badge/-KavyaManohar-181717?style=flat-square&logo=github)](https://github.com/KavyaManohar) | -| Pyae Sone | 2 | [![GitHub](https://img.shields.io/badge/-Autumn--21-181717?style=flat-square&logo=github)](https://github.com/Autumn-21) | -| S. Shiva Krishna Reddy | 2 | [![GitHub](https://img.shields.io/badge/-Shiva0krishna-181717?style=flat-square&logo=github)](https://github.com/Shiva0krishna) | -| Sangavi GR | 2 | [![GitHub](https://img.shields.io/badge/-SangaviGR-181717?style=flat-square&logo=github)](https://github.com/SangaviGR) | -| Vivek Kumar | 2 | [![GitHub](https://img.shields.io/badge/-092vk-181717?style=flat-square&logo=github)](https://github.com/092vk) | -| Manasi Yadav | 2 | [![GitHub](https://img.shields.io/badge/-manasiyadav-181717?style=flat-square&logo=github)](https://github.com/manasiyadav) | - -
- -
-📋 Contributors with 1 commit (click to expand) - -
- -| Contributor | GitHub | -|:------------|:------:| -| Aditya Bhattacharya | [![GitHub](https://img.shields.io/badge/-ADITYA--BHATTACHARYA--DEV-181717?style=flat-square&logo=github)](https://github.com/ADITYA-BHATTACHARYA-DEV) | -| Abhishek Soni | [![GitHub](https://img.shields.io/badge/-Abhishek--Soni--25-181717?style=flat-square&logo=github)](https://github.com/Abhishek-Soni-25) | -| Ashwith Rego | [![GitHub](https://img.shields.io/badge/-ashwith-181717?style=flat-square&logo=github)](https://github.com/ashwith) | -| Athul George | [![GitHub](https://img.shields.io/badge/-athulappadan-181717?style=flat-square&logo=github)](https://github.com/athulappadan) | -| Boddu Ajay | [![GitHub](https://img.shields.io/badge/-ajayboddu--2006-181717?style=flat-square&logo=github)](https://github.com/ajayboddu-2006) | -| Charaan | [![GitHub](https://img.shields.io/badge/-Charaan-181717?style=flat-square&logo=github)](https://github.com/Charaan) | -| GiGi Koneti | [![GitHub](https://img.shields.io/badge/-GiGiKoneti-181717?style=flat-square&logo=github)](https://github.com/GiGiKoneti) | -| Keerthana | [![GitHub](https://img.shields.io/badge/-Keerthana-181717?style=flat-square&logo=github)](https://github.com/Keerthana) | -| Kusum Kisori | [![GitHub](https://img.shields.io/badge/-KusumKisori-181717?style=flat-square&logo=github)](https://github.com/KusumKisori) | -| Mausam | [![GitHub](https://img.shields.io/badge/-Mausam5055-181717?style=flat-square&logo=github)](https://github.com/Mausam5055) | -| Mudit Joshi | [![GitHub](https://img.shields.io/badge/-MuditJoshi-181717?style=flat-square&logo=github)](https://github.com/MuditJoshi) | -| Naman Patel | [![GitHub](https://img.shields.io/badge/-NamanPatel-181717?style=flat-square&logo=github)](https://github.com/NamanPatel) | -| Varad Patil | [![GitHub](https://img.shields.io/badge/-OfficialVarad-181717?style=flat-square&logo=github)](https://github.com/OfficialVarad) | -| Pavan Mantri | [![GitHub](https://img.shields.io/badge/-PavanMantri-181717?style=flat-square&logo=github)](https://github.com/PavanMantri) | -| Pavithra W | [![GitHub](https://img.shields.io/badge/-Pavithraw24-181717?style=flat-square&logo=github)](https://github.com/Pavithraw24) | -| Raksha Dave | [![GitHub](https://img.shields.io/badge/-RakshaDave-181717?style=flat-square&logo=github)](https://github.com/RakshaDave) | -| Rudra Mani Upadhyay | [![GitHub](https://img.shields.io/badge/-Rudramani1-181717?style=flat-square&logo=github)](https://github.com/Rudramani1) | -| Shravan A Y | [![GitHub](https://img.shields.io/badge/-ShravanAY-181717?style=flat-square&logo=github)](https://github.com/ShravanAY) | -| Vikas Mulaje | [![GitHub](https://img.shields.io/badge/-VikasMulaje-181717?style=flat-square&logo=github)](https://github.com/VikasMulaje) | -| Aamir Thekiya | [![GitHub](https://img.shields.io/badge/-aamirthekiya-181717?style=flat-square&logo=github)](https://github.com/aamirthekiya) | -| Bhavya Bhardwaj | [![GitHub](https://img.shields.io/badge/-bhavyabhardwaj001-181717?style=flat-square&logo=github)](https://github.com/bhavyabhardwaj001) | -| Mahak Gupta | [![GitHub](https://img.shields.io/badge/-mahakgupta0123-181717?style=flat-square&logo=github)](https://github.com/mahakgupta0123) | -| Nuh Too Wai | [![GitHub](https://img.shields.io/badge/-nuhtoowai-181717?style=flat-square&logo=github)](https://github.com/nuhtoowai) | - -
- ---- - -## 📊 Contribution Statistics - -| Metric | Value | -|:-------|:------| -| **Total Contributors** | 149+ | -| **Total Commits** | 2,400+ | -| **Project Age** | Since February 2015 (10+ years) | -| **License** | GNU GPL v3.0 | -| **Active Branches** | `master` (main), `installers`, feature branches | - -### Contributor Growth Over Time - -``` -2015 ██░░░░░░░░░░░░░░░░░░ Project founded by Fahim Khan -2016 ████░░░░░░░░░░░░░░░░ Core team (Fahim, Rahul) establishes architecture -2017 ██████░░░░░░░░░░░░░░ NGHDL integration, community grows -2018 ████████░░░░░░░░░░░░ Saurabh, Nil, Athul join; converter modules added -2019 ██████████░░░░░░░░░░ PyQt migration, model editor expansion -2020 ████████████░░░░░░░░ Sumanto Kar becomes lead; Makerchip integration -2021 ██████████████░░░░░░ SKY130 PDK, NgVeri, major feature wave -2022 ████████████████░░░░ Flatpak packaging, Docker support, PyQt6 migration -2023 ██████████████████░░ IHP PDK, schematic converters, 100+ contributors -2024 ████████████████████ Community-driven enhancements, 149+ contributors -``` - ---- - -## 🙌 How to Get Listed - -Anyone who contributes to the eSim codebase is automatically listed here! Ways to contribute: - -- 🐛 **Bug Fixes** — Find and fix issues in the [issue tracker](https://github.com/fossee/esim/issues) -- ✨ **Features** — Implement new features or enhance existing ones -- 📝 **Documentation** — Improve docs, comments, or tutorials -- 🧪 **Testing** — Add tests or report bugs with reproducible steps -- 🎨 **UI/UX** — Improve the user interface and experience -- 🌐 **Translations** — Help localize eSim for different languages -- 📦 **Packaging** — Help with Flatpak, Snap, AppImage, or Docker builds -- 📚 **Examples** — Add new example circuits to the `Examples/` directory - -See [CONTRIBUTION.md](CONTRIBUTION.md) for step-by-step instructions. - ---- - -## 🖼️ All Contributors Mosaic - -

- - All Contributors - -

- -

- Auto-generated via contrib.rocks — shows GitHub avatar for every contributor -

- ---- - -

- Thank you to every single contributor who has made eSim possible! ❤️
- This file is maintained alongside the project. If your contribution is missing, please open an issue. -

- -

- FOSSEE Logo -      - IIT Bombay Logo -

From d6c7cf8902c11f76e72e9c08def28f2742354965 Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 21:38:38 +0530 Subject: [PATCH 05/19] Update README.md --- README.md | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index 9ef2c689b..25713fe99 100644 --- a/README.md +++ b/README.md @@ -523,7 +523,7 @@ flowchart LR > - Follow [PEP 8](https://www.python.org/dev/peps/pep-0008/) code style > - Include a commit body describing what you changed and why -For detailed contribution guidelines, see [CONTRIBUTION.md](CONTRIBUTION.md). +For detailed contribution guidelines, see [CONTRIBUTING.md](CONTRIBUTING.md). --- @@ -542,10 +542,7 @@ A huge thank you to all **149+ amazing people** who have contributed to eSim!

-

- 📋 View the full Contributors page →
- Complete list with profiles, commit counts, and contribution tiers for all 149+ contributors -

+

149+ contributors and counting! View all contributors →

--- From db55f36f89f9f45edf0ece87f94e877ab8f97170 Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 21:42:11 +0530 Subject: [PATCH 06/19] Update CONTRIBUTING.md --- CONTRIBUTING.md | 250 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 250 insertions(+) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 4dc1f4459..852f58b8c 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -11,8 +11,258 @@ Every contribution — whether it's a bug fix, new feature, documentation improv --- +## 🏆 Our Contributors + +A huge thank you to all **149+ amazing people** who have built eSim since 2015! 🎉 + +### 🏛️ Project Leads + +| Role | Name | Affiliation | +|:-----|:-----|:------------| +| **Developed by** | [FOSSEE Team](https://www.fossee.in/) | IIT Bombay | +| **Original Author** | Fahim Khan | eSim / FOSSEE, IIT Bombay | +| **Lead Maintainer** | Sumanto Kar | FOSSEE, IIT Bombay | +| **Core Maintainer** | Rahul Paknikar | FOSSEE, IIT Bombay | +| **Core Maintainer** | Pranav P | FOSSEE, IIT Bombay | + +### 🥇 Core Maintainers + + + + + + + +
+ + Sumanto Kar
+ Sumanto Kar +

+ 320 commits
+ GitHub +
+ + Rahul Paknikar
+ Rahul Paknikar +

+ 265 commits
+ GitHub +
+ + Fahim Khan
+ Fahim Khan +

+ 244 commits
+ GitHub +
+ +### 🥈 Major Contributors (20+ commits) + +| # | Contributor | Commits | GitHub | +|:-:|:------------|:-------:|:------:| +| 1 | **Saurabh Bansode** | 49 | [![GitHub](https://img.shields.io/badge/-saurabhb17-181717?style=flat-square&logo=github)](https://github.com/saurabhb17) | +| 2 | **Athul George** | 37 | [![GitHub](https://img.shields.io/badge/-athulappadan-181717?style=flat-square&logo=github)](https://github.com/athulappadan) | +| 3 | **Nil Shah** | 36 | [![GitHub](https://img.shields.io/badge/-nilshah98-181717?style=flat-square&logo=github)](https://github.com/nilshah98) | +| 4 | **Shanthi Priya** | 36 | [![GitHub](https://img.shields.io/badge/-Shanthipriya20-181717?style=flat-square&logo=github)](https://github.com/Shanthipriya20) | +| 5 | **Anjali Jaiswal** | 35 | [![GitHub](https://img.shields.io/badge/-anjalijaiswal08-181717?style=flat-square&logo=github)](https://github.com/anjalijaiswal08) | +| 6 | **Pranav P** | 34 | [![GitHub](https://img.shields.io/badge/-pranavsdreams-181717?style=flat-square&logo=github)](https://github.com/pranavsdreams) | +| 7 | **Annesha Dey** | 33 | [![GitHub](https://img.shields.io/badge/-AD20047-181717?style=flat-square&logo=github)](https://github.com/AD20047) | +| 8 | **Sunil Shetye** | 33 | [![GitHub](https://img.shields.io/badge/-sunilshetye-181717?style=flat-square&logo=github)](https://github.com/sunilshetye) | +| 9 | **Hariom Thakur** | 28 | [![GitHub](https://img.shields.io/badge/-hariomthakur-181717?style=flat-square&logo=github)](https://github.com/hariomthakur) | +| 10 | **Aditya Minocha** | 23 | [![GitHub](https://img.shields.io/badge/-adityaminocha-181717?style=flat-square&logo=github)](https://github.com/adityaminocha) | +| 11 | **R. Krishnan** | 23 | [![GitHub](https://img.shields.io/badge/-rkrish00568-181717?style=flat-square&logo=github)](https://github.com/rkrish00568) | +| 12 | **Ganderla Chaithanya** | 22 | [![GitHub](https://img.shields.io/badge/-GanderlaChaithanya-181717?style=flat-square&logo=github)](https://github.com/GanderlaChaithanya) | +| 13 | **Anwesha** | 21 | [![GitHub](https://img.shields.io/badge/-Anwesha06-181717?style=flat-square&logo=github)](https://github.com/Anwesha06) | + +### 🥉 Active Contributors (10–19 commits) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
Ankush

19 +
+
Anup K. Pandey

19 +
+
G Jaswanth

19 +
+
E Kamalesh

18 +
+
Sai Charan

18 +
+
Ajay Boddu

15 +
+
PSR

15 +
+
Komal Sheth

15 +
+
Dilip Boidya

15 +
+
Nishit Bayen

14 +
+
Suchinton

13 +
+
Karthick N.

13 +
+
Sabarish M.

12 +
+
Harshal

11 +
+
D Tharun

11 +
+
Jovin P John

11 +
+
Madhav K.

11 +
+
Ragul

11 +
+
Jawwaad

10 +
+
Nirmitha N

10 +
+
Pavan

10 +
+
Senbagaseelan

10 +
+
Tanisha

10 +
+
Ashok Kumar

10 +
+ +### 🌟 Community Contributors + +
+Contributors with 5–9 commits (click to expand) +
+ +| Contributor | Commits | GitHub | +|:------------|:-------:|:------:| +| Maanit | 9 | [![GitHub](https://img.shields.io/badge/-Maanit-181717?style=flat-square&logo=github)](https://github.com/Maanit) | +| Myo Thinzar | 9 | [![GitHub](https://img.shields.io/badge/-Myo--Thinzar-181717?style=flat-square&logo=github)](https://github.com/Myo-Thinzar) | +| Partha Pratim Nath | 9 | [![GitHub](https://img.shields.io/badge/-parthapratimn-181717?style=flat-square&logo=github)](https://github.com/parthapratimn) | +| Sakhi Sharma | 9 | [![GitHub](https://img.shields.io/badge/-Sakhi1011-181717?style=flat-square&logo=github)](https://github.com/Sakhi1011) | +| Temshinaro Jamir | 9 | [![GitHub](https://img.shields.io/badge/-TemshinaroJamir-181717?style=flat-square&logo=github)](https://github.com/TemshinaroJamir) | +| Xoher | 9 | [![GitHub](https://img.shields.io/badge/-xoher-181717?style=flat-square&logo=github)](https://github.com/xoher) | +| Abhishek Shakya | 8 | [![GitHub](https://img.shields.io/badge/-AbhishekShakya-181717?style=flat-square&logo=github)](https://github.com/AbhishekShakya) | +| Aishwarya Sinha | 8 | [![GitHub](https://img.shields.io/badge/-AishwaryaSinha-181717?style=flat-square&logo=github)](https://github.com/AishwaryaSinha) | +| Aman Shukla | 8 | [![GitHub](https://img.shields.io/badge/-AmanShukla111-181717?style=flat-square&logo=github)](https://github.com/AmanShukla111) | +| Chandru | 8 | [![GitHub](https://img.shields.io/badge/-Chandru__136-181717?style=flat-square&logo=github)](https://github.com/Chandru136) | +| SAGARIKAA | 8 | [![GitHub](https://img.shields.io/badge/-SAGARIKAA760-181717?style=flat-square&logo=github)](https://github.com/SAGARIKAA760) | +| Sakshi Pandey | 8 | [![GitHub](https://img.shields.io/badge/-SakshiPandey-181717?style=flat-square&logo=github)](https://github.com/SakshiPandey) | +| Shaili Sahu | 8 | [![GitHub](https://img.shields.io/badge/-ShailiSahu-181717?style=flat-square&logo=github)](https://github.com/ShailiSahu) | +| Anish R. Khapare | 8 | [![GitHub](https://img.shields.io/badge/-anishrkhapare--bit-181717?style=flat-square&logo=github)](https://github.com/anishrkhapare-bit) | +| Deen Efil | 8 | [![GitHub](https://img.shields.io/badge/-deen--efil-181717?style=flat-square&logo=github)](https://github.com/deen-efil) | +| Priyanka | 8 | [![GitHub](https://img.shields.io/badge/-Priyanka-181717?style=flat-square&logo=github)](https://github.com/Priyanka) | +| Vivek Kumar | 7 | [![GitHub](https://img.shields.io/badge/-092vk-181717?style=flat-square&logo=github)](https://github.com/092vk) | +| Bladen Martin | 7 | [![GitHub](https://img.shields.io/badge/-BladenMartin-181717?style=flat-square&logo=github)](https://github.com/BladenMartin) | +| Jay Mistry | 7 | [![GitHub](https://img.shields.io/badge/-mistryjay-181717?style=flat-square&logo=github)](https://github.com/mistryjay) | +| Vanshika Tanwar | 7 | [![GitHub](https://img.shields.io/badge/-VanshikaTanwar-181717?style=flat-square&logo=github)](https://github.com/VanshikaTanwar) | +| Varadha | 7 | [![GitHub](https://img.shields.io/badge/-VaradhaCodes-181717?style=flat-square&logo=github)](https://github.com/VaradhaCodes) | +| Suprraja | 7 | [![GitHub](https://img.shields.io/badge/-suprraja-181717?style=flat-square&logo=github)](https://github.com/suprraja) | +| Taeolis | 7 | [![GitHub](https://img.shields.io/badge/-taeolis-181717?style=flat-square&logo=github)](https://github.com/taeolis) | +| Arpit Sharma | 6 | [![GitHub](https://img.shields.io/badge/-ArpitSharma-181717?style=flat-square&logo=github)](https://github.com/ArpitSharma) | +| Gaurav Supal | 6 | [![GitHub](https://img.shields.io/badge/-GauravSupal-181717?style=flat-square&logo=github)](https://github.com/GauravSupal) | +| Jayanth | 6 | [![GitHub](https://img.shields.io/badge/-Jayanth--4547-181717?style=flat-square&logo=github)](https://github.com/Jayanth-4547) | +| Manimaran K | 6 | [![GitHub](https://img.shields.io/badge/-ManimaranK-181717?style=flat-square&logo=github)](https://github.com/ManimaranK) | +| Rachith H | 6 | [![GitHub](https://img.shields.io/badge/-Rachith--H-181717?style=flat-square&logo=github)](https://github.com/Rachith-H) | +| Tanay Mathur | 6 | [![GitHub](https://img.shields.io/badge/-TanayMathur-181717?style=flat-square&logo=github)](https://github.com/TanayMathur) | +| Maddy | 6 | [![GitHub](https://img.shields.io/badge/-maddy--2-181717?style=flat-square&logo=github)](https://github.com/maddy-2) | +| Abhishek Soni | 5 | [![GitHub](https://img.shields.io/badge/-Abhishek--Soni--25-181717?style=flat-square&logo=github)](https://github.com/Abhishek-Soni-25) | +| Barun | 5 | [![GitHub](https://img.shields.io/badge/-Barun-181717?style=flat-square&logo=github)](https://github.com/Barun) | +| Varad Patil | 5 | [![GitHub](https://img.shields.io/badge/-OfficialVarad-181717?style=flat-square&logo=github)](https://github.com/OfficialVarad) | +| Yash Kiran Ekhande | 5 | [![GitHub](https://img.shields.io/badge/-YashEkhande-181717?style=flat-square&logo=github)](https://github.com/YashEkhande) | +| Krishna Goutam | 5 | [![GitHub](https://img.shields.io/badge/-krishnaGoutam-181717?style=flat-square&logo=github)](https://github.com/krishnaGoutam) | +| Rohinthram | 5 | [![GitHub](https://img.shields.io/badge/-rohinthram-181717?style=flat-square&logo=github)](https://github.com/rohinthram) | + +
+ +
+Contributors with 1–4 commits (click to expand) +
+ +| Contributor | Commits | GitHub | +|:------------|:-------:|:------:| +| Akshay Rukade | 4 | [![GitHub](https://img.shields.io/badge/-AkshayRukade-181717?style=flat-square&logo=github)](https://github.com/AkshayRukade) | +| Vatsal Patel | 4 | [![GitHub](https://img.shields.io/badge/-PatelVatsalB21-181717?style=flat-square&logo=github)](https://github.com/PatelVatsalB21) | +| Ankur Gupta | 3 | [![GitHub](https://img.shields.io/badge/-ankur--gupta--29-181717?style=flat-square&logo=github)](https://github.com/ankur-gupta-29) | +| E Balakrishna | 3 | [![GitHub](https://img.shields.io/badge/-EBalakrishna-181717?style=flat-square&logo=github)](https://github.com/EBalakrishna) | +| Gaurav Gupta | 3 | [![GitHub](https://img.shields.io/badge/-gauravgupta654-181717?style=flat-square&logo=github)](https://github.com/gauravgupta654) | +| Harshit Singh Negi | 3 | [![GitHub](https://img.shields.io/badge/-demon2202-181717?style=flat-square&logo=github)](https://github.com/demon2202) | +| Pranav Karuvally | 3 | [![GitHub](https://img.shields.io/badge/-theunixdisaster-181717?style=flat-square&logo=github)](https://github.com/theunixdisaster) | +| Abinash Singh | 2 | [![GitHub](https://img.shields.io/badge/-avinashlalotra-181717?style=flat-square&logo=github)](https://github.com/avinashlalotra) | +| Harvi | 2 | [![GitHub](https://img.shields.io/badge/-Harvi--2215-181717?style=flat-square&logo=github)](https://github.com/Harvi-2215) | +| Kavya Manohar | 2 | [![GitHub](https://img.shields.io/badge/-KavyaManohar-181717?style=flat-square&logo=github)](https://github.com/KavyaManohar) | +| Pyae Sone | 2 | [![GitHub](https://img.shields.io/badge/-Autumn--21-181717?style=flat-square&logo=github)](https://github.com/Autumn-21) | +| S. Shiva Krishna Reddy | 2 | [![GitHub](https://img.shields.io/badge/-Shiva0krishna-181717?style=flat-square&logo=github)](https://github.com/Shiva0krishna) | +| Sangavi GR | 2 | [![GitHub](https://img.shields.io/badge/-SangaviGR-181717?style=flat-square&logo=github)](https://github.com/SangaviGR) | +| Manasi Yadav | 2 | [![GitHub](https://img.shields.io/badge/-manasiyadav-181717?style=flat-square&logo=github)](https://github.com/manasiyadav) | +| Aditya Bhattacharya | 1 | [![GitHub](https://img.shields.io/badge/-ADITYA--BHATTACHARYA--DEV-181717?style=flat-square&logo=github)](https://github.com/ADITYA-BHATTACHARYA-DEV) | +| Ashwith Rego | 1 | [![GitHub](https://img.shields.io/badge/-ashwith-181717?style=flat-square&logo=github)](https://github.com/ashwith) | +| Boddu Ajay | 1 | [![GitHub](https://img.shields.io/badge/-ajayboddu--2006-181717?style=flat-square&logo=github)](https://github.com/ajayboddu-2006) | +| Charaan | 1 | [![GitHub](https://img.shields.io/badge/-Charaan-181717?style=flat-square&logo=github)](https://github.com/Charaan) | +| GiGi Koneti | 1 | [![GitHub](https://img.shields.io/badge/-GiGiKoneti-181717?style=flat-square&logo=github)](https://github.com/GiGiKoneti) | +| Kusum Kisori | 1 | [![GitHub](https://img.shields.io/badge/-KusumKisori-181717?style=flat-square&logo=github)](https://github.com/KusumKisori) | +| Mausam | 1 | [![GitHub](https://img.shields.io/badge/-Mausam5055-181717?style=flat-square&logo=github)](https://github.com/Mausam5055) | +| Mudit Joshi | 1 | [![GitHub](https://img.shields.io/badge/-MuditJoshi-181717?style=flat-square&logo=github)](https://github.com/MuditJoshi) | +| Naman Patel | 1 | [![GitHub](https://img.shields.io/badge/-NamanPatel-181717?style=flat-square&logo=github)](https://github.com/NamanPatel) | +| Pavan Mantri | 1 | [![GitHub](https://img.shields.io/badge/-PavanMantri-181717?style=flat-square&logo=github)](https://github.com/PavanMantri) | +| Pavithra W | 1 | [![GitHub](https://img.shields.io/badge/-Pavithraw24-181717?style=flat-square&logo=github)](https://github.com/Pavithraw24) | +| Raksha Dave | 1 | [![GitHub](https://img.shields.io/badge/-RakshaDave-181717?style=flat-square&logo=github)](https://github.com/RakshaDave) | +| Rudra Mani Upadhyay | 1 | [![GitHub](https://img.shields.io/badge/-Rudramani1-181717?style=flat-square&logo=github)](https://github.com/Rudramani1) | +| Shravan A Y | 1 | [![GitHub](https://img.shields.io/badge/-ShravanAY-181717?style=flat-square&logo=github)](https://github.com/ShravanAY) | +| Vikas Mulaje | 1 | [![GitHub](https://img.shields.io/badge/-VikasMulaje-181717?style=flat-square&logo=github)](https://github.com/VikasMulaje) | +| Aamir Thekiya | 1 | [![GitHub](https://img.shields.io/badge/-aamirthekiya-181717?style=flat-square&logo=github)](https://github.com/aamirthekiya) | +| Bhavya Bhardwaj | 1 | [![GitHub](https://img.shields.io/badge/-bhavyabhardwaj001-181717?style=flat-square&logo=github)](https://github.com/bhavyabhardwaj001) | +| Mahak Gupta | 1 | [![GitHub](https://img.shields.io/badge/-mahakgupta0123-181717?style=flat-square&logo=github)](https://github.com/mahakgupta0123) | +| Nuh Too Wai | 1 | [![GitHub](https://img.shields.io/badge/-nuhtoowai-181717?style=flat-square&logo=github)](https://github.com/nuhtoowai) | + +
+ +### All Contributors Mosaic + +

+ + All Contributors + +

+ +

Auto-generated via contrib.rocksView full list on GitHub →

+ +--- + ## 📋 Table of Contents +- [Our Contributors](#-our-contributors) - [Getting Started](#-getting-started) - [Ways to Contribute](#-ways-to-contribute) - [Development Setup](#-development-setup) From 4dc706f1f9ed40cff8492bf08dd21aee164aa8d6 Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 21:44:59 +0530 Subject: [PATCH 07/19] commit --- CONTRIBUTING.md | 51 ++++++++++++++++++++++--------------------------- README.md | 24 +++++++++++++++++++---- 2 files changed, 43 insertions(+), 32 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 852f58b8c..707751267 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -27,34 +27,29 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015! ### 🥇 Core Maintainers - - - - - - -
- - Sumanto Kar
- Sumanto Kar -

- 320 commits
- GitHub -
- - Rahul Paknikar
- Rahul Paknikar -

- 265 commits
- GitHub -
- - Fahim Khan
- Fahim Khan -

- 244 commits
- GitHub -
+

+ + Sumanto Kar
+ 🥇 Sumanto Kar +

+ Lead Maintainer · 320 commits
+ GitHub +

+ +

+ + Rahul Paknikar
+ 🥈 Rahul Paknikar
+ 265 commits
+ GitHub +
+ + Fahim Khan
+ 🥉 Fahim Khan
+ 244 commits
+ GitHub +
+

### 🥈 Major Contributors (20+ commits) diff --git a/README.md b/README.md index 25713fe99..38d930d34 100644 --- a/README.md +++ b/README.md @@ -531,10 +531,26 @@ For detailed contribution guidelines, see [CONTRIBUTING.md](CONTRIBUTING.md). A huge thank you to all **149+ amazing people** who have contributed to eSim! 🎉 -| 🥇 Core Maintainer | 🥈 Core Maintainer | 🥉 Core Maintainer | -|:---:|:---:|:---:| -| [![Sumanto Kar](https://github.com/Eyantra698Sumanto.png?size=80)](https://github.com/Eyantra698Sumanto) | [![Rahul Paknikar](https://github.com/rahulp13.png?size=80)](https://github.com/rahulp13) | [![Fahim Khan](https://github.com/fahim-oscad.png?size=80)](https://github.com/fahim-oscad) | -| **Sumanto Kar** · 320 commits | **Rahul Paknikar** · 265 commits | **Fahim Khan** · 244 commits | +

+ + Sumanto Kar
+ 🥇 Sumanto Kar +

+ Lead Maintainer · 320 commits +

+ +

+ + Rahul Paknikar
+ 🥈 Rahul Paknikar
+ 265 commits +
+ + Fahim Khan
+ 🥉 Fahim Khan
+ 244 commits +
+

From 24838188c84cda98443afb7f592982e8efff5170 Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 21:47:06 +0530 Subject: [PATCH 08/19] update project documentation layout update project documentation layout --- CONTRIBUTING.md | 83 +++++++++++++++++++++++++++---------------------- README.md | 47 ++++++++++++++++------------ 2 files changed, 72 insertions(+), 58 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 707751267..2aa418fb2 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -11,6 +11,21 @@ Every contribution — whether it's a bug fix, new feature, documentation improv --- +## 📋 Table of Contents + +- [Our Contributors](#-our-contributors) +- [Getting Started](#-getting-started) +- [Ways to Contribute](#-ways-to-contribute) +- [Development Setup](#-development-setup) +- [Pull Request Workflow](#-pull-request-workflow) +- [Commit Guidelines](#-commit-guidelines) +- [Code Style](#-code-style) +- [Reporting Bugs](#-reporting-bugs) +- [Requesting Features](#-requesting-features) +- [Community](#-community) + +--- + ## 🏆 Our Contributors A huge thank you to all **149+ amazing people** who have built eSim since 2015! 🎉 @@ -27,29 +42,36 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015! ### 🥇 Core Maintainers -

- - Sumanto Kar
- 🥇 Sumanto Kar -

- Lead Maintainer · 320 commits
- GitHub -

- -

- - Rahul Paknikar
- 🥈 Rahul Paknikar
- 265 commits
- GitHub -
- - Fahim Khan
- 🥉 Fahim Khan
- 244 commits
- GitHub -
-

+ + + + + + + + +
+ + Sumanto Kar
+ 🥇 Sumanto Kar +

+ Lead Maintainer · 320 commits
+ GitHub +
+ + Rahul Paknikar
+ 🥈 Rahul Paknikar +

+ 265 commits
+ GitHub +
+ + Fahim Khan
+ 🥉 Fahim Khan +

+ 244 commits
+ GitHub +
### 🥈 Major Contributors (20+ commits) @@ -255,21 +277,6 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015! --- -## 📋 Table of Contents - -- [Our Contributors](#-our-contributors) -- [Getting Started](#-getting-started) -- [Ways to Contribute](#-ways-to-contribute) -- [Development Setup](#-development-setup) -- [Pull Request Workflow](#-pull-request-workflow) -- [Commit Guidelines](#-commit-guidelines) -- [Code Style](#-code-style) -- [Reporting Bugs](#-reporting-bugs) -- [Requesting Features](#-requesting-features) -- [Community](#-community) - ---- - ## 🚀 Getting Started 1. **Find an issue** — Browse the [issue tracker](https://github.com/fossee/esim/issues) for bugs or features you'd like to work on diff --git a/README.md b/README.md index 38d930d34..adaef1ccc 100644 --- a/README.md +++ b/README.md @@ -531,26 +531,33 @@ For detailed contribution guidelines, see [CONTRIBUTING.md](CONTRIBUTING.md). A huge thank you to all **149+ amazing people** who have contributed to eSim! 🎉 -

- - Sumanto Kar
- 🥇 Sumanto Kar -

- Lead Maintainer · 320 commits -

- -

- - Rahul Paknikar
- 🥈 Rahul Paknikar
- 265 commits -
- - Fahim Khan
- 🥉 Fahim Khan
- 244 commits -
-

+ + + + + + + + +
+ + Sumanto Kar
+ 🥇 Sumanto Kar +

+ Lead Maintainer · 320 commits +
+ + Rahul Paknikar
+ 🥈 Rahul Paknikar +

+ 265 commits +
+ + Fahim Khan
+ 🥉 Fahim Khan +

+ 244 commits +

From 759228ee629a7a5a6b76a0855b2afcb1761164c6 Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 21:51:23 +0530 Subject: [PATCH 09/19] commit --- CONTRIBUTING.md | 8 +++++--- README.md | 14 +++++++------- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 2aa418fb2..5011593e8 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -4,9 +4,11 @@ Thank you for your interest in contributing to **eSim**! 🎉 Every contribution — whether it's a bug fix, new feature, documentation improvement, or example circuit — helps make eSim better for everyone.

- Open Issues - Open PRs - Contributors + Open Issues + Open PRs + Good First Issues + Contributors + Code Style

--- diff --git a/README.md b/README.md index adaef1ccc..35a443eb9 100644 --- a/README.md +++ b/README.md @@ -17,13 +17,13 @@

- Docs - Forks - Stars - Issues - PRs Welcome - Contributors - PEP8 + Docs + Forks + Stars + Issues + PRs Welcome + Contributors + Code Style

From be43a4b13011afe0c298002d1404b7a5bbcbf995 Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 21:55:21 +0530 Subject: [PATCH 10/19] commit --- CONTRIBUTING.md | 218 ++++++++++++++++++++++++------------------------ README.md | 4 +- 2 files changed, 109 insertions(+), 113 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 5011593e8..6e1f7e5bc 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -46,7 +46,7 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015! - - -
+ Sumanto Kar
🥇 Sumanto Kar @@ -54,8 +54,6 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015! Lead Maintainer · 320 commits
GitHub
Rahul Paknikar
@@ -75,108 +73,15 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015!
-### 🥈 Major Contributors (20+ commits) - -| # | Contributor | Commits | GitHub | -|:-:|:------------|:-------:|:------:| -| 1 | **Saurabh Bansode** | 49 | [![GitHub](https://img.shields.io/badge/-saurabhb17-181717?style=flat-square&logo=github)](https://github.com/saurabhb17) | -| 2 | **Athul George** | 37 | [![GitHub](https://img.shields.io/badge/-athulappadan-181717?style=flat-square&logo=github)](https://github.com/athulappadan) | -| 3 | **Nil Shah** | 36 | [![GitHub](https://img.shields.io/badge/-nilshah98-181717?style=flat-square&logo=github)](https://github.com/nilshah98) | -| 4 | **Shanthi Priya** | 36 | [![GitHub](https://img.shields.io/badge/-Shanthipriya20-181717?style=flat-square&logo=github)](https://github.com/Shanthipriya20) | -| 5 | **Anjali Jaiswal** | 35 | [![GitHub](https://img.shields.io/badge/-anjalijaiswal08-181717?style=flat-square&logo=github)](https://github.com/anjalijaiswal08) | -| 6 | **Pranav P** | 34 | [![GitHub](https://img.shields.io/badge/-pranavsdreams-181717?style=flat-square&logo=github)](https://github.com/pranavsdreams) | -| 7 | **Annesha Dey** | 33 | [![GitHub](https://img.shields.io/badge/-AD20047-181717?style=flat-square&logo=github)](https://github.com/AD20047) | -| 8 | **Sunil Shetye** | 33 | [![GitHub](https://img.shields.io/badge/-sunilshetye-181717?style=flat-square&logo=github)](https://github.com/sunilshetye) | -| 9 | **Hariom Thakur** | 28 | [![GitHub](https://img.shields.io/badge/-hariomthakur-181717?style=flat-square&logo=github)](https://github.com/hariomthakur) | -| 10 | **Aditya Minocha** | 23 | [![GitHub](https://img.shields.io/badge/-adityaminocha-181717?style=flat-square&logo=github)](https://github.com/adityaminocha) | -| 11 | **R. Krishnan** | 23 | [![GitHub](https://img.shields.io/badge/-rkrish00568-181717?style=flat-square&logo=github)](https://github.com/rkrish00568) | -| 12 | **Ganderla Chaithanya** | 22 | [![GitHub](https://img.shields.io/badge/-GanderlaChaithanya-181717?style=flat-square&logo=github)](https://github.com/GanderlaChaithanya) | -| 13 | **Anwesha** | 21 | [![GitHub](https://img.shields.io/badge/-Anwesha06-181717?style=flat-square&logo=github)](https://github.com/Anwesha06) | +### All Contributors Mosaic -### 🥉 Active Contributors (10–19 commits) +

+ + All Contributors + +

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-
Ankush

19 -
-
Anup K. Pandey

19 -
-
G Jaswanth

19 -
-
E Kamalesh

18 -
-
Sai Charan

18 -
-
Ajay Boddu

15 -
-
PSR

15 -
-
Komal Sheth

15 -
-
Dilip Boidya

15 -
-
Nishit Bayen

14 -
-
Suchinton

13 -
-
Karthick N.

13 -
-
Sabarish M.

12 -
-
Harshal

11 -
-
D Tharun

11 -
-
Jovin P John

11 -
-
Madhav K.

11 -
-
Ragul

11 -
-
Jawwaad

10 -
-
Nirmitha N

10 -
-
Pavan

10 -
-
Senbagaseelan

10 -
-
Tanisha

10 -
-
Ashok Kumar

10 -
+

Auto-generated via contrib.rocksView full list on GitHub →

### 🌟 Community Contributors @@ -267,15 +172,108 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015! -### All Contributors Mosaic +### 🥉 Active Contributors (10–19 commits) -

- - All Contributors - -

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
Ankush

19 +
+
Anup K. Pandey

19 +
+
G Jaswanth

19 +
+
E Kamalesh

18 +
+
Sai Charan

18 +
+
Ajay Boddu

15 +
+
PSR

15 +
+
Komal Sheth

15 +
+
Dilip Boidya

15 +
+
Nishit Bayen

14 +
+
Suchinton

13 +
+
Karthick N.

13 +
+
Sabarish M.

12 +
+
Harshal

11 +
+
D Tharun

11 +
+
Jovin P John

11 +
+
Madhav K.

11 +
+
Ragul

11 +
+
Jawwaad

10 +
+
Nirmitha N

10 +
+
Pavan

10 +
+
Senbagaseelan

10 +
+
Tanisha

10 +
+
Ashok Kumar

10 +
-

Auto-generated via contrib.rocksView full list on GitHub →

+### 🥈 Major Contributors (20+ commits) + +| # | Contributor | Commits | GitHub | +|:-:|:------------|:-------:|:------:| +| 1 | **Saurabh Bansode** | 49 | [![GitHub](https://img.shields.io/badge/-saurabhb17-181717?style=flat-square&logo=github)](https://github.com/saurabhb17) | +| 2 | **Athul George** | 37 | [![GitHub](https://img.shields.io/badge/-athulappadan-181717?style=flat-square&logo=github)](https://github.com/athulappadan) | +| 3 | **Nil Shah** | 36 | [![GitHub](https://img.shields.io/badge/-nilshah98-181717?style=flat-square&logo=github)](https://github.com/nilshah98) | +| 4 | **Shanthi Priya** | 36 | [![GitHub](https://img.shields.io/badge/-Shanthipriya20-181717?style=flat-square&logo=github)](https://github.com/Shanthipriya20) | +| 5 | **Anjali Jaiswal** | 35 | [![GitHub](https://img.shields.io/badge/-anjalijaiswal08-181717?style=flat-square&logo=github)](https://github.com/anjalijaiswal08) | +| 6 | **Pranav P** | 34 | [![GitHub](https://img.shields.io/badge/-pranavsdreams-181717?style=flat-square&logo=github)](https://github.com/pranavsdreams) | +| 7 | **Annesha Dey** | 33 | [![GitHub](https://img.shields.io/badge/-AD20047-181717?style=flat-square&logo=github)](https://github.com/AD20047) | +| 8 | **Sunil Shetye** | 33 | [![GitHub](https://img.shields.io/badge/-sunilshetye-181717?style=flat-square&logo=github)](https://github.com/sunilshetye) | +| 9 | **Hariom Thakur** | 28 | [![GitHub](https://img.shields.io/badge/-hariomthakur-181717?style=flat-square&logo=github)](https://github.com/hariomthakur) | +| 10 | **Aditya Minocha** | 23 | [![GitHub](https://img.shields.io/badge/-adityaminocha-181717?style=flat-square&logo=github)](https://github.com/adityaminocha) | +| 11 | **R. Krishnan** | 23 | [![GitHub](https://img.shields.io/badge/-rkrish00568-181717?style=flat-square&logo=github)](https://github.com/rkrish00568) | +| 12 | **Ganderla Chaithanya** | 22 | [![GitHub](https://img.shields.io/badge/-GanderlaChaithanya-181717?style=flat-square&logo=github)](https://github.com/GanderlaChaithanya) | +| 13 | **Anwesha** | 21 | [![GitHub](https://img.shields.io/badge/-Anwesha06-181717?style=flat-square&logo=github)](https://github.com/Anwesha06) | --- diff --git a/README.md b/README.md index 35a443eb9..48dff84fb 100644 --- a/README.md +++ b/README.md @@ -533,15 +533,13 @@ A huge thank you to all **149+ amazing people** who have contributed to eSim! - - - + @@ -211,11 +214,11 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015! + + - - @@ -231,11 +234,11 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015! + + - - @@ -251,6 +254,8 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015! + + diff --git a/library/SubcircuitLibrary/mc1496/mc1496.cir.out b/library/SubcircuitLibrary/mc1496/mc1496.cir.out index c0008ca7c..1db9091db 100644 --- a/library/SubcircuitLibrary/mc1496/mc1496.cir.out +++ b/library/SubcircuitLibrary/mc1496/mc1496.cir.out @@ -1,25 +1,54 @@ -* c:\fossee\esim\library\subcircuitlibrary\mc1496\mc1496.cir - -.include NPN.lib -q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 -q5 net-_q5-pad1_ net-_q5-pad2_ net-_q2-pad3_ Q2N2222 -q6 net-_q2-pad1_ net-_q5-pad2_ net-_q6-pad3_ Q2N2222 -q9 net-_q5-pad1_ net-_q2-pad2_ net-_q6-pad3_ Q2N2222 -q3 net-_q2-pad3_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 -q4 net-_q3-pad3_ net-_q1-pad1_ net-_q4-pad3_ Q2N2222 -q7 net-_q6-pad3_ net-_q7-pad2_ net-_q7-pad3_ Q2N2222 -q8 net-_q7-pad3_ net-_q1-pad1_ net-_q8-pad3_ Q2N2222 -q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2222 -r2 net-_q4-pad3_ net-_r1-pad2_ 500 -r1 net-_q1-pad3_ net-_r1-pad2_ 500 -r3 net-_q8-pad3_ net-_r1-pad2_ 500 -* u1 net-_q7-pad2_ net-_q7-pad3_ net-_q3-pad3_ net-_q3-pad2_ net-_q1-pad1_ net-_q2-pad1_ ? net-_q2-pad2_ ? net-_q5-pad2_ ? net-_q5-pad1_ ? net-_r1-pad2_ port -.tran 0.1e-06 10e-03 0e-03 - -* Control Statements +.title kicad schematic + +.include NMOS-180nm.lib +.include userDiode.lib + +* ---------- Power Supplies ---------- +* define a 5V DC supply between VDD and GND +VDD vdd 0 DC 5 +VEE vee 0 DC 0 +Vbias bias 0 DC 1.2 + +* ---------- Input Sources ---------- +* give each input node a small signal so theyre not floating +Vsig1 signal_input_1 0 SIN(0 1 1k) +Vsig2 signal_input_2 0 SIN(0 1 1k) +Vcar1 carrier_input_1 0 SIN(0 1 10k) +Vcar2 carrier_input_2 0 SIN(0 1 10k) + +* ---------- Circuit ---------- +r1 vee net-_r1-pad2_ 500k +d1 bias net-_r1-pad2_ D1N750 +r2 vee net-_m3-pad3_ 500k +m3 gain_adjust_2 bias net-_m3-pad3_ vee CMOSN W=100u L=100u M=1 +m2 net-_m1-pad3_ signal_input_1 gain_adjust_2 vee CMOSN W=100u L=100u M=1 +m4 net-_m1-pad3_ carrier_input_1 output1 vee CMOSN W=100u L=100u M=1 +m1 output1 carrier_input_2 net-_m1-pad3_ vee CMOSN W=100u L=100u M=1 +m6 gain_adjust_1 bias net-_m6-pad3_ vee CMOSN W=100u L=100u M=1 +r3 vee net-_m6-pad3_ 500k +m7 gain_adjust_1 signal_input_2 net-_m5-pad3_ vee CMOSN W=100u L=100u M=1 +m8 net-_m5-pad3_ carrier_input_2 output1 vee CMOSN W=100u L=100u M=1 +m5 output1 carrier_input_1 net-_m5-pad3_ vee CMOSN W=100u L=100u M=1 + +.option method=gear reltol=0.01 abstol=1e-6 itl1=1000 +.ic v(bias)=1.2 + +.tran 0.1ms 50ms + +* ---------- Control Section ---------- .control run print allv > plot_data_v.txt print alli > plot_data_i.txt + +* Plot useful nodes (these exist now) +plot v(bias) +plot v(signal_input_1) +plot v(signal_input_2) +plot v(carrier_input_1) +plot v(carrier_input_2) +plot v(output1) +plot v(gain_adjust_1) +plot v(gain_adjust_2) .endc .end diff --git a/library/subcircuitLibrary/MC1496/MC1496.cir b/library/subcircuitLibrary/MC1496/MC1496.cir index b114973d5..b9067a27b 100644 --- a/library/subcircuitLibrary/MC1496/MC1496.cir +++ b/library/subcircuitLibrary/MC1496/MC1496.cir @@ -1,15 +1,23 @@ -.title KiCad schematic -M6 gain1 bias Net-_M6-Pad3_ gnd eSim_MOS_N -R3 gnd Net-_M6-Pad3_ 500k -U4 signal_input_1 gain1 gain2 signal_input_2 bias output1 unconnected-_U4-Pad7_ carrier_input_1 unconnected-_U4-Pad9_ carrier_input_2 unconnected-_U4-Pad11_ output1 unconnected-_U4-Pad13_ gnd PORT -R2 gnd Net-_M3-Pad3_ 500k -M2 Net-_M1-Pad3_ signal_input_1 gain2 gnd eSim_MOS_N -M3 gain2 bias Net-_M3-Pad3_ gnd eSim_MOS_N -M4 Net-_M1-Pad3_ carrier_input_1 output1 gnd eSim_MOS_N -M1 output1 carrier_input_2 Net-_M1-Pad3_ gnd eSim_MOS_N -D1 bias Net-_D1-Pad2_ eSim_Diode -R1 gnd Net-_D1-Pad2_ 500k -M5 output1 carrier_input_1 Net-_M5-Pad3_ gnd eSim_MOS_N -M7 gain1 signal_input_2 Net-_M5-Pad3_ gnd eSim_MOS_N -M8 Net-_M5-Pad3_ carrier_input_2 output1 gnd eSim_MOS_N +* C:\FOSSEE\eSim\library\SubcircuitLibrary\mc1496\mc1496.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/12/25 22:39:35 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q5 Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q2-Pad1_ Net-_Q5-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q9 Net-_Q5-Pad1_ Net-_Q2-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q3 Net-_Q2-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q3-Pad3_ Net-_Q1-Pad1_ Net-_Q4-Pad3_ eSim_NPN +Q7 Net-_Q6-Pad3_ Net-_Q7-Pad2_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q7-Pad3_ Net-_Q1-Pad1_ Net-_Q8-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad3_ eSim_NPN +R2 Net-_Q4-Pad3_ Net-_R1-Pad2_ 500 +R1 Net-_Q1-Pad3_ Net-_R1-Pad2_ 500 +R3 Net-_Q8-Pad3_ Net-_R1-Pad2_ 500 +U1 Net-_Q7-Pad2_ Net-_Q7-Pad3_ Net-_Q3-Pad3_ Net-_Q3-Pad2_ Net-_Q1-Pad1_ Net-_Q2-Pad1_ ? Net-_Q2-Pad2_ ? Net-_Q5-Pad2_ ? Net-_Q5-Pad1_ ? Net-_R1-Pad2_ PORT + .end From f17b6f18a9014f45e793ddd17f2a67c6e0cf240f Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 22:59:38 +0530 Subject: [PATCH 19/19] Update CONTRIBUTING.md --- CONTRIBUTING.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 391fe9fec..ed800df00 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -156,7 +156,7 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015! | Charaan | 1 | [![GitHub](https://img.shields.io/badge/-Charaan-181717?style=flat-square&logo=github)](https://github.com/Charaan) | | GiGi Koneti | 1 | [![GitHub](https://img.shields.io/badge/-GiGiKoneti-181717?style=flat-square&logo=github)](https://github.com/GiGiKoneti) | | Kusum Kisori | 1 | [![GitHub](https://img.shields.io/badge/-KusumKisori-181717?style=flat-square&logo=github)](https://github.com/KusumKisori) | -| Mausam | 1 | [![GitHub](https://img.shields.io/badge/-Mausam5055-181717?style=flat-square&logo=github)](https://github.com/Mausam5055) | + | Mudit Joshi | 1 | [![GitHub](https://img.shields.io/badge/-MuditJoshi-181717?style=flat-square&logo=github)](https://github.com/MuditJoshi) | | Naman Patel | 1 | [![GitHub](https://img.shields.io/badge/-NamanPatel-181717?style=flat-square&logo=github)](https://github.com/NamanPatel) | | Pavan Mantri | 1 | [![GitHub](https://img.shields.io/badge/-PavanMantri-181717?style=flat-square&logo=github)](https://github.com/PavanMantri) |
+ Sumanto Kar
🥇 Sumanto Kar

Lead Maintainer · 320 commits
Rahul Paknikar
From e399a694e87fc9340ceff16e4dac65c9fc63f61a Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 21:58:54 +0530 Subject: [PATCH 11/19] update contributing guidelines with repository activity charts --- CONTRIBUTING.md | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 6e1f7e5bc..424390f5d 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -275,6 +275,24 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015! | 12 | **Ganderla Chaithanya** | 22 | [![GitHub](https://img.shields.io/badge/-GanderlaChaithanya-181717?style=flat-square&logo=github)](https://github.com/GanderlaChaithanya) | | 13 | **Anwesha** | 21 | [![GitHub](https://img.shields.io/badge/-Anwesha06-181717?style=flat-square&logo=github)](https://github.com/Anwesha06) | +### 📈 Repository Growth & Activity + +

+ + + + + Star History Chart + + +

+ +

+ + eSim Repo Stats + +

+ --- ## 🚀 Getting Started From 88cfe9c4f5241c02ae9c2d6d9adfdd0030b52bdd Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 22:02:40 +0530 Subject: [PATCH 12/19] Update README.md --- README.md | 235 ++++++++++++++++++++++++++++++------------------------ 1 file changed, 133 insertions(+), 102 deletions(-) diff --git a/README.md b/README.md index 48dff84fb..13e22e36e 100644 --- a/README.md +++ b/README.md @@ -38,7 +38,7 @@ --- -## 📖 About +## About **eSim** is a free and open-source EDA (Electronic Design Automation) tool for circuit design, simulation, analysis, and PCB design. It is an integrated tool built using open-source software such as **KiCad**, **Ngspice**, **GHDL**, and **Makerchip**, providing a seamless workflow from schematic capture to simulation results. @@ -48,130 +48,161 @@ eSim is designed for electronics engineers, students, educators, and hobbyists w --- -## ✨ Features +## Features | Category | Feature | Description | |:---------|:--------|:------------| -| 🎨 **Design** | Schematic Capture | Draw circuit schematics using KiCad's schematic editor with eSim's custom symbol libraries | -| 🔄 **Conversion** | KiCad to Ngspice | Convert KiCad schematics to Ngspice-compatible netlists for simulation | -| ⚡ **Simulation** | Ngspice Engine | Run DC, AC, Transient, and other SPICE analyses with real-time interactive plots | -| 📊 **Analysis** | Waveform Plotting | Visualize simulation results with matplotlib-based Python plots and Ngspice native plots | -| 🔧 **Model Editor** | Device Models | Create and edit SPICE device models (Diodes, BJTs, MOSFETs, JFETs, IGBTs, etc.) | -| 🧩 **Subcircuits** | Subcircuit Builder | Build, manage, and upload reusable subcircuit blocks | -| 🖥️ **Mixed-Signal** | NGHDL Integration | Interface VHDL digital models (via GHDL) with analog Ngspice simulations | -| 🌐 **Verilog** | Makerchip + NgVeri | Use Makerchip IDE for Verilog/TL-Verilog design and convert to Ngspice models | -| 🏭 **PCB** | Layout Design | Design PCB layouts using KiCad's PCB editor with eSim's footprint libraries | -| 🔁 **Converters** | Schematic Import | Convert PSpice and LTSpice schematics/libraries to KiCad-compatible formats | -| 📐 **Modelica** | Ngspice-to-Modelica | Convert Ngspice netlists to Modelica models for OpenModelica simulation | -| 🏗️ **SKY130 PDK** | SkyWater 130nm | Support for SkyWater SKY130 open-source Process Design Kit | -| 🔬 **IHP PDK** | IHP OpenPDK | Integration with IHP SG13G2 open-source PDK for SiGe BiCMOS | +| • **Design** | Schematic Capture | Draw circuit schematics using KiCad's schematic editor with eSim's custom symbol libraries | +| • **Conversion** | KiCad to Ngspice | Convert KiCad schematics to Ngspice-compatible netlists for simulation | +| • **Simulation** | Ngspice Engine | Run DC, AC, Transient, and other SPICE analyses with real-time interactive plots | +| • **Analysis** | Waveform Plotting | Visualize simulation results with matplotlib-based Python plots and Ngspice native plots | +| • **Model Editor** | Device Models | Create and edit SPICE device models (Diodes, BJTs, MOSFETs, JFETs, IGBTs, etc.) | +| • **Subcircuits** | Subcircuit Builder | Build, manage, and upload reusable subcircuit blocks | +| • **Mixed-Signal** | NGHDL Integration | Interface VHDL digital models (via GHDL) with analog Ngspice simulations | +| • **Verilog** | Makerchip + NgVeri | Use Makerchip IDE for Verilog/TL-Verilog design and convert to Ngspice models | +| • **PCB** | Layout Design | Design PCB layouts using KiCad's PCB editor with eSim's footprint libraries | +| • **Converters** | Schematic Import | Convert PSpice and LTSpice schematics/libraries to KiCad-compatible formats | +| • **Modelica** | Ngspice-to-Modelica | Convert Ngspice netlists to Modelica models for OpenModelica simulation | +| • **SKY130 PDK** | SkyWater 130nm | Support for SkyWater SKY130 open-source Process Design Kit | +| • **IHP PDK** | IHP OpenPDK | Integration with IHP SG13G2 open-source PDK for SiGe BiCMOS | --- -## 🏗️ Architecture +## Architecture ### High-Level System Architecture ```mermaid graph TB - subgraph USER["👤 User Interface Layer"] - APP["Application.py
Main Window (PyQt6)"] - PE["ProjectExplorer
File Browser"] - DA["DockArea
Tabbed Workspace"] - TE["TimeExplorer
Snapshot Manager"] - CON["Console
Log Output"] + %% Styling + classDef ui fill:#2A3F54,stroke:#1ABB9C,stroke-width:2px,color:#fff + classDef core fill:#3E536C,stroke:#3498DB,stroke-width:2px,color:#fff + classDef engine fill:#1F2D3D,stroke:#E74C3C,stroke-width:2px,color:#fff + classDef data fill:#E9F0F5,stroke:#95A5A6,stroke-width:1px,color:#333 + + subgraph UI ["User Interface (PyQt6)"] + A[Application Main Window]:::ui + PE[Project Explorer]:::ui + DA[Dock Area Workspace]:::ui + TE[Time Explorer]:::ui + CON[Console Widget]:::ui + + A --> PE & DA & TE & CON end - subgraph CORE["⚙️ Core Engine Layer"] - KNG["KiCad-to-Ngspice
Converter"] - SIM["Ngspice Simulation
Engine"] - PLT["Plot Window
matplotlib"] - ME["Model Editor"] - SC["Subcircuit
Manager"] + subgraph CORE ["Core Python Modules"] + K2N[KiCad-to-Ngspice]:::core + SIM[Ngspice Simulator]:::core + PLT[Matplotlib Plotter]:::core + ME[Model Editor]:::core + SC[Subcircuit Builder]:::core + + DA --> K2N & SIM & ME & SC end - subgraph INTEGRATION["🔌 Integration Layer"] - NGHDL["NGHDL
GHDL Interface"] - MKR["Makerchip/NgVeri
Verilog Models"] - MOD["Modelica Converter
OpenModelica"] - CONV["Schematic Converters
PSpice / LTSpice"] + subgraph INTEGRATION ["Mixed-Signal & External APIs"] + NGHDL[NGHDL Interface]:::core + MKR[Makerchip/NgVeri]:::core + MOD[Modelica Converter]:::core + CONV[PSpice/LTSpice Converter]:::core + + DA --> NGHDL & MKR & MOD & CONV end - subgraph EXTERNAL["📦 External Tools"] - KICAD["KiCad
Schematic + PCB"] - NGSPICE["Ngspice
SPICE Simulator"] - GHDL["GHDL
VHDL Simulator"] - VERILATOR["Verilator
Verilog Simulator"] - OMEDIT["OpenModelica
Modelica IDE"] + subgraph ENGINES ["Simulation & EDA Engines"] + KICAD[KiCad Eeschema]:::engine + PCB[KiCad Pcbnew]:::engine + NGSPICE[Ngspice Backend]:::engine + GHDL[GHDL Simulator]:::engine + VER[Verilator]:::engine + OM[OpenModelica]:::engine end - APP --> PE - APP --> DA - APP --> TE - APP --> CON - - DA --> KNG - DA --> SIM - DA --> ME - DA --> SC - DA --> NGHDL - DA --> MKR - DA --> MOD - DA --> CONV - - KNG --> KICAD - SIM --> NGSPICE - SIM --> PLT - NGHDL --> GHDL - MKR --> VERILATOR - MOD --> OMEDIT - - style USER fill:#1a1a2e,stroke:#e94560,color:#fff - style CORE fill:#16213e,stroke:#0f3460,color:#fff - style INTEGRATION fill:#0f3460,stroke:#533483,color:#fff - style EXTERNAL fill:#533483,stroke:#e94560,color:#fff + %% Data Flow + XML[(Netlist / XML)]:::data + RAW[(Raw Data / txt)]:::data + VHDL[(VHDL Files)]:::data + + K2N -- Generates --> XML + XML -- Consumed by --> NGSPICE + SIM -- Triggers --> NGSPICE + NGSPICE -- Outputs --> RAW + RAW -- Parsed by --> PLT + + NGHDL -- Compiles --> VHDL + VHDL -- Simulated by --> GHDL + GHDL -- Co-simulates --> NGSPICE + + MKR -- Verilog/TL-V --> VER + + KICAD -- Schematic --> K2N + KICAD -- Netlist --> PCB ``` ### Simulation Workflow ```mermaid -flowchart LR - A["📝 Create/Open
Project"] --> B["🎨 Draw
Schematic
KiCad"] - B --> C["🔄 Convert
KiCad → Ngspice"] - C --> D["⚙️ Configure
Analysis &
Parameters"] - D --> E["▶️ Run
Simulation
Ngspice"] - E --> F["📊 Plot &
Analyze
Results"] - - style A fill:#6c5ce7,stroke:#a29bfe,color:#fff - style B fill:#00b894,stroke:#55efc4,color:#fff - style C fill:#fdcb6e,stroke:#f9ca24,color:#333 - style D fill:#e17055,stroke:#fab1a0,color:#fff - style E fill:#0984e3,stroke:#74b9ff,color:#fff - style F fill:#d63031,stroke:#ff7675,color:#fff +flowchart TD + %% Styling + classDef startend fill:#2ECC71,stroke:#27AE60,stroke-width:2px,color:#fff + classDef process fill:#3498DB,stroke:#2980B9,stroke-width:2px,color:#fff + classDef decision fill:#F1C40F,stroke:#F39C12,stroke-width:2px,color:#333 + classDef io fill:#9B59B6,stroke:#8E44AD,stroke-width:2px,color:#fff + + START([Start eSim Project]):::startend --> CREATE{New or Existing?}:::decision + CREATE -- New --> PROJ[Create Project Structure]:::process + CREATE -- Existing --> OPEN[Open Project Workspace]:::process + + PROJ --> SCHEM[Draw Schematic in KiCad]:::process + OPEN --> SCHEM + + SCHEM --> CHECK{Mixed Signal?}:::decision + CHECK -- Yes --> VHDL[Write VHDL/Verilog Models]:::process + VHDL --> GHDL[Compile via NGHDL/NgVeri]:::process + GHDL --> SYM[Generate KiCad Symbol]:::process + SYM --> SCHEM + + CHECK -- No --> K2N[Run KiCad-to-Ngspice]:::process + K2N --> PARSE[Parse XML Netlist]:::process + PARSE --> SRC[Configure Sources & Analysis]:::process + SRC --> DEV[Configure Device Models]:::process + + DEV --> SPICE[Generate .cir SPICE Netlist]:::io + SPICE --> NGSPICE[Execute Ngspice Simulation]:::process + + NGSPICE --> OUT{Simulation Success?}:::decision + OUT -- No --> ERR[View Error Log & Debug]:::process + ERR --> SCHEM + + OUT -- Yes --> RAW[Generate RAW Output Data]:::io + RAW --> PLOT[Extract Data for Plotting]:::process + PLOT --> MAT[Render matplotlib Waveforms]:::process + + MAT --> END([Analyze Results]):::startend ``` ### Mixed-Signal Simulation Flow (NGHDL) ```mermaid -flowchart TB - V["📄 Write VHDL Code"] --> U["⬆️ Upload via NGHDL"] - U --> G["🔧 GHDL Compiles
VHDL to Shared Lib"] - G --> CM["📦 Create Ngspice
Code Model"] - CM --> KS["🎨 Create KiCad
Symbol"] - KS --> SC["📝 Use in
Schematic"] - SC --> SIM["⚡ Mixed-Signal
Simulation"] - - style V fill:#a29bfe,stroke:#6c5ce7,color:#fff - style U fill:#74b9ff,stroke:#0984e3,color:#fff - style G fill:#55efc4,stroke:#00b894,color:#fff - style CM fill:#ffeaa7,stroke:#fdcb6e,color:#333 - style KS fill:#fab1a0,stroke:#e17055,color:#fff - style SIM fill:#fd79a8,stroke:#e84393,color:#fff +flowchart TD + %% Styling + classDef input fill:#34495E,stroke:#2C3E50,stroke-width:2px,color:#fff + classDef process fill:#16A085,stroke:#1ABC9C,stroke-width:2px,color:#fff + classDef output fill:#8E44AD,stroke:#9B59B6,stroke-width:2px,color:#fff + + VHDL([Write VHDL/Verilog Code]):::input --> UPLOAD[Upload via NGHDL/NgVeri UI]:::process + UPLOAD --> COMPILE[GHDL/Verilator Compiles Code to Shared Lib]:::process + COMPILE --> MODEL[Create Ngspice Code Model .cm]:::process + MODEL --> KICAD[Generate KiCad Component Symbol]:::output + + KICAD --> SCHEM([Place Symbol in Schematic]):::input + SCHEM --> BRIDGE[ADC/DAC Bridge Insertion]:::process + BRIDGE --> SIM[Execute Mixed-Signal Co-Simulation]:::output ``` --- -## 📂 Project Structure +## Project Structure ### Root Directory @@ -203,7 +234,7 @@ flowchart TB ``` src/ -├── frontEnd/ # 🖥️ GUI & Main Application +├── frontEnd/ # GUI & Main Application │ ├── Application.py # Main window, toolbar setup, menu actions (960 lines) │ ├── DockArea.py # Tabbed dock workspace for editors/simulators (24K) │ ├── ProjectExplorer.py # File tree browser for project navigation (20K) @@ -211,7 +242,7 @@ src/ │ ├── TerminalUi.py # Embedded terminal widget (5K) │ └── Workspace.py # Workspace selection dialog (6K) │ -├── kicadtoNgspice/ # 🔄 KiCad-to-Ngspice Conversion Engine +├── kicadtoNgspice/ # KiCad-to-Ngspice Conversion Engine │ ├── KicadtoNgspice.py # Main conversion controller & UI (41K) │ ├── Convert.py # Netlist parsing and SPICE generation (40K) │ ├── Analysis.py # Analysis type configuration (DC, AC, Transient) (32K) @@ -223,23 +254,23 @@ src/ │ ├── Model.py # Model file handling (6K) │ └── TrackWidget.py # UI tracking widget (1K) │ -├── ngspiceSimulation/ # ⚡ Simulation Engine & Plotting +├── ngspiceSimulation/ # Simulation Engine & Plotting │ ├── NgspiceWidget.py # Ngspice process management & execution (16K) │ ├── plot_window.py # matplotlib-based waveform plotter (66K) │ ├── plotting_widgets.py # Custom plot controls and widgets (8K) │ └── data_extraction.py # Simulation data file parser (11K) │ -├── modelEditor/ # 🔧 SPICE Model Editor +├── modelEditor/ # SPICE Model Editor │ └── ModelEditor.py # GUI for creating/editing device models (33K) │ -├── subcircuit/ # 🧩 Subcircuit Management +├── subcircuit/ # Subcircuit Management │ ├── Subcircuit.py # Subcircuit manager main window (3K) │ ├── newSub.py # Create new subcircuit (3K) │ ├── openSub.py # Open existing subcircuit (1K) │ ├── uploadSub.py # Upload subcircuit to library (4K) │ └── convertSub.py # Subcircuit format conversion (2K) │ -├── maker/ # 🌐 Makerchip & NgVeri Integration +├── maker/ # Makerchip & NgVeri Integration │ ├── Maker.py # Makerchip IDE integration (23K) │ ├── NgVeri.py # Verilog-to-Ngspice model generator (17K) │ ├── ModelGeneration.py # Auto model generation pipeline (48K) @@ -247,7 +278,7 @@ src/ │ ├── makerchip.py # Makerchip cloud IDE connector (3K) │ └── Appconfig.py # Maker-specific configuration (2K) │ -├── converter/ # 🔁 Schematic Format Converters +├── converter/ # Schematic Format Converters │ ├── pspiceToKicad.py # PSpice schematic importer (5K) │ ├── ltspiceToKicad.py # LTSpice schematic importer (6K) │ ├── libConverter.py # Library format converter (3K) @@ -382,7 +413,7 @@ esim # Or double-click the eSim desktop icon ``` -### 🪟 Windows +### Windows 1. Download the eSim installer from [esim.fossee.in/downloads](https://esim.fossee.in/downloads) 2. Disable antivirus temporarily (if required) @@ -478,7 +509,7 @@ eSim ships with **42 ready-to-simulate example projects** in the `Examples/` dir --- -## 🤝 Contributing +## Contributing We welcome contributions from the community! Whether it's bug fixes, new features, documentation improvements, or example circuits — every contribution matters. @@ -527,7 +558,7 @@ For detailed contribution guidelines, see [CONTRIBUTING.md](CONTRIBUTING.md). --- -## 👥 Contributors +## Contributors A huge thank you to all **149+ amazing people** who have contributed to eSim! 🎉 From e9dc21728ad3e7e6af717927f3811e33ac98a8aa Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 22:05:29 +0530 Subject: [PATCH 13/19] architecture --- ARCHITECTURE.md | 112 ++++++++++++++++++++++++++++++++++++++++++++++++ README.md | 61 +------------------------- 2 files changed, 113 insertions(+), 60 deletions(-) create mode 100644 ARCHITECTURE.md diff --git a/ARCHITECTURE.md b/ARCHITECTURE.md new file mode 100644 index 000000000..418290e5e --- /dev/null +++ b/ARCHITECTURE.md @@ -0,0 +1,112 @@ +# eSim Architecture & Workflows + +This document contains detailed flowcharts and diagrams mapping out the inner workings, simulation pipelines, and data transformations within eSim. + +--- + +## 1. Standard Simulation Workflow + +This flowchart details the end-to-end user journey for a standard analog/digital simulation in eSim, from project creation to waveform analysis. + +```mermaid +flowchart TD + %% Styling + classDef startend fill:#2ECC71,stroke:#27AE60,stroke-width:2px,color:#fff + classDef process fill:#3498DB,stroke:#2980B9,stroke-width:2px,color:#fff + classDef decision fill:#F1C40F,stroke:#F39C12,stroke-width:2px,color:#333 + classDef io fill:#9B59B6,stroke:#8E44AD,stroke-width:2px,color:#fff + + START([Start eSim Project]):::startend --> CREATE{New or Existing?}:::decision + CREATE -- New --> PROJ[Create Project Structure]:::process + CREATE -- Existing --> OPEN[Open Project Workspace]:::process + + PROJ --> SCHEM[Draw Schematic in KiCad]:::process + OPEN --> SCHEM + + SCHEM --> CHECK{Mixed Signal?}:::decision + CHECK -- Yes --> VHDL[Write VHDL/Verilog Models]:::process + VHDL --> GHDL[Compile via NGHDL/NgVeri]:::process + GHDL --> SYM[Generate KiCad Symbol]:::process + SYM --> SCHEM + + CHECK -- No --> K2N[Run KiCad-to-Ngspice]:::process + K2N --> PARSE[Parse XML Netlist]:::process + PARSE --> SRC[Configure Sources & Analysis]:::process + SRC --> DEV[Configure Device Models]:::process + + DEV --> SPICE[Generate .cir SPICE Netlist]:::io + SPICE --> NGSPICE[Execute Ngspice Simulation]:::process + + NGSPICE --> OUT{Simulation Success?}:::decision + OUT -- No --> ERR[View Error Log & Debug]:::process + ERR --> SCHEM + + OUT -- Yes --> RAW[Generate RAW Output Data]:::io + RAW --> PLOT[Extract Data for Plotting]:::process + PLOT --> MAT[Render matplotlib Waveforms]:::process + + MAT --> END([Analyze Results]):::startend +``` + +--- + +## 2. Mixed-Signal Simulation Flow (NGHDL) + +This diagram breaks down how eSim bridges digital logic (VHDL/Verilog) with analog simulation using GHDL and Ngspice code models. + +```mermaid +flowchart TD + %% Styling + classDef input fill:#34495E,stroke:#2C3E50,stroke-width:2px,color:#fff + classDef process fill:#16A085,stroke:#1ABC9C,stroke-width:2px,color:#fff + classDef output fill:#8E44AD,stroke:#9B59B6,stroke-width:2px,color:#fff + + VHDL([Write VHDL/Verilog Code]):::input --> UPLOAD[Upload via NGHDL/NgVeri UI]:::process + UPLOAD --> COMPILE[GHDL/Verilator Compiles Code to Shared Lib]:::process + COMPILE --> MODEL[Create Ngspice Code Model .cm]:::process + MODEL --> KICAD[Generate KiCad Component Symbol]:::output + + KICAD --> SCHEM([Place Symbol in Schematic]):::input + SCHEM --> BRIDGE[ADC/DAC Bridge Insertion]:::process + BRIDGE --> SIM[Execute Mixed-Signal Co-Simulation]:::output +``` + +--- + +## 3. KiCad-to-Ngspice Netlist Conversion + +A deep dive into the `Convert.py` backend pipeline, showing how KiCad's XML data is processed into an executable SPICE netlist. + +```mermaid +flowchart TD + %% Styling + classDef input fill:#34495E,stroke:#2C3E50,stroke-width:2px,color:#fff + classDef process fill:#E67E22,stroke:#D35400,stroke-width:2px,color:#fff + classDef io fill:#9B59B6,stroke:#8E44AD,stroke-width:2px,color:#fff + + XML([KiCad XML Netlist]):::input --> PARSE[Parse XML DOM]:::process + PARSE --> EXTRACT[Extract Components & Connections]:::process + EXTRACT --> MAP[Map Pins to Ngspice Nodes]:::process + MAP --> SUB[Resolve Subcircuits & Macros]:::process + SUB --> INJECT[Inject Device Parameters & Models]:::process + INJECT --> SPICE([Generate .cir SPICE Netlist]):::io +``` + +--- + +## 4. Device Model Generation Pipeline + +Outlining how user-defined models (Diodes, BJTs, MOSFETs) are integrated via the Model Editor. + +```mermaid +flowchart LR + %% Styling + classDef input fill:#2C3E50,stroke:#1A252F,stroke-width:2px,color:#fff + classDef process fill:#E74C3C,stroke:#C0392B,stroke-width:2px,color:#fff + classDef output fill:#F39C12,stroke:#E67E22,stroke-width:2px,color:#fff + + UI([Model Editor UI]):::input --> VAL[Validate Parameters]:::process + VAL --> TEMPLATE[Inject Data into SPICE Template]:::process + TEMPLATE --> LIB([Save to project .lib file]):::output + LIB --> K2N([Attached during Netlist Conversion]):::output +``` diff --git a/README.md b/README.md index 13e22e36e..32747e7b3 100644 --- a/README.md +++ b/README.md @@ -139,66 +139,7 @@ graph TB KICAD -- Netlist --> PCB ``` -### Simulation Workflow - -```mermaid -flowchart TD - %% Styling - classDef startend fill:#2ECC71,stroke:#27AE60,stroke-width:2px,color:#fff - classDef process fill:#3498DB,stroke:#2980B9,stroke-width:2px,color:#fff - classDef decision fill:#F1C40F,stroke:#F39C12,stroke-width:2px,color:#333 - classDef io fill:#9B59B6,stroke:#8E44AD,stroke-width:2px,color:#fff - - START([Start eSim Project]):::startend --> CREATE{New or Existing?}:::decision - CREATE -- New --> PROJ[Create Project Structure]:::process - CREATE -- Existing --> OPEN[Open Project Workspace]:::process - - PROJ --> SCHEM[Draw Schematic in KiCad]:::process - OPEN --> SCHEM - - SCHEM --> CHECK{Mixed Signal?}:::decision - CHECK -- Yes --> VHDL[Write VHDL/Verilog Models]:::process - VHDL --> GHDL[Compile via NGHDL/NgVeri]:::process - GHDL --> SYM[Generate KiCad Symbol]:::process - SYM --> SCHEM - - CHECK -- No --> K2N[Run KiCad-to-Ngspice]:::process - K2N --> PARSE[Parse XML Netlist]:::process - PARSE --> SRC[Configure Sources & Analysis]:::process - SRC --> DEV[Configure Device Models]:::process - - DEV --> SPICE[Generate .cir SPICE Netlist]:::io - SPICE --> NGSPICE[Execute Ngspice Simulation]:::process - - NGSPICE --> OUT{Simulation Success?}:::decision - OUT -- No --> ERR[View Error Log & Debug]:::process - ERR --> SCHEM - - OUT -- Yes --> RAW[Generate RAW Output Data]:::io - RAW --> PLOT[Extract Data for Plotting]:::process - PLOT --> MAT[Render matplotlib Waveforms]:::process - - MAT --> END([Analyze Results]):::startend -``` - -### Mixed-Signal Simulation Flow (NGHDL) - -```mermaid -flowchart TD - %% Styling - classDef input fill:#34495E,stroke:#2C3E50,stroke-width:2px,color:#fff - classDef process fill:#16A085,stroke:#1ABC9C,stroke-width:2px,color:#fff - classDef output fill:#8E44AD,stroke:#9B59B6,stroke-width:2px,color:#fff - - VHDL([Write VHDL/Verilog Code]):::input --> UPLOAD[Upload via NGHDL/NgVeri UI]:::process - UPLOAD --> COMPILE[GHDL/Verilator Compiles Code to Shared Lib]:::process - COMPILE --> MODEL[Create Ngspice Code Model .cm]:::process - MODEL --> KICAD[Generate KiCad Component Symbol]:::output - - KICAD --> SCHEM([Place Symbol in Schematic]):::input - SCHEM --> BRIDGE[ADC/DAC Bridge Insertion]:::process - BRIDGE --> SIM[Execute Mixed-Signal Co-Simulation]:::output -``` +*For detailed simulation workflows, sub-system operations, and system flowcharts, please refer to our [Architecture & Workflows Guide](ARCHITECTURE.md).* --- From f648d604dc955ef8fa812781647c530f70207ffb Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 22:07:34 +0530 Subject: [PATCH 14/19] Update README.md --- README.md | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/README.md b/README.md index 32747e7b3..f425e266f 100644 --- a/README.md +++ b/README.md @@ -38,7 +38,7 @@ --- -## About +## 📖 About **eSim** is a free and open-source EDA (Electronic Design Automation) tool for circuit design, simulation, analysis, and PCB design. It is an integrated tool built using open-source software such as **KiCad**, **Ngspice**, **GHDL**, and **Makerchip**, providing a seamless workflow from schematic capture to simulation results. @@ -48,7 +48,7 @@ eSim is designed for electronics engineers, students, educators, and hobbyists w --- -## Features +## ✨ Features | Category | Feature | Description | |:---------|:--------|:------------| @@ -68,7 +68,7 @@ eSim is designed for electronics engineers, students, educators, and hobbyists w --- -## Architecture +## 🏗️ Architecture ### High-Level System Architecture @@ -143,7 +143,7 @@ graph TB --- -## Project Structure +## 📂 Project Structure ### Root Directory @@ -354,7 +354,7 @@ esim # Or double-click the eSim desktop icon ``` -### Windows +### 🪟 Windows 1. Download the eSim installer from [esim.fossee.in/downloads](https://esim.fossee.in/downloads) 2. Disable antivirus temporarily (if required) @@ -450,7 +450,7 @@ eSim ships with **42 ready-to-simulate example projects** in the `Examples/` dir --- -## Contributing +## 🤝 Contributing We welcome contributions from the community! Whether it's bug fixes, new features, documentation improvements, or example circuits — every contribution matters. @@ -499,7 +499,7 @@ For detailed contribution guidelines, see [CONTRIBUTING.md](CONTRIBUTING.md). --- -## Contributors +## 👥 Contributors A huge thank you to all **149+ amazing people** who have contributed to eSim! 🎉 From d22bf98e2bdfa928c3336b874657819f4a0f99fb Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 22:09:26 +0530 Subject: [PATCH 15/19] Update README.md --- README.md | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/README.md b/README.md index f425e266f..fa61e53b8 100644 --- a/README.md +++ b/README.md @@ -552,26 +552,7 @@ A huge thank you to all **149+ amazing people** who have contributed to eSim! --- -## 🔒 Security -For information on reporting security vulnerabilities, please see [SECURITY.md](SECURITY.md). - ---- - -## 📄 License - -eSim is released under the **GNU General Public License v3.0** — see the [LICENSE](LICENSE) file for details. - -``` -Copyright (C) FOSSEE, IIT Bombay - -This program is free software: you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation, either version 3 of the License, or -(at your option) any later version. -``` - ----

Built with ❤️ by the FOSSEE Team at IIT Bombay From 8b1e10cba5c6af14263fa7f4c20e16a8f7117d23 Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 22:10:32 +0530 Subject: [PATCH 16/19] docs: update security policy --- SECURITY.md | 65 ++++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 50 insertions(+), 15 deletions(-) diff --git a/SECURITY.md b/SECURITY.md index 034e84803..a4d483fb3 100644 --- a/SECURITY.md +++ b/SECURITY.md @@ -1,21 +1,56 @@ -# Security Policy +# 🔒 Security Policy -## Supported Versions +The eSim project takes security seriously. As a desktop EDA application handling various local file formats, external executables (Ngspice, GHDL, KiCad), and third-party models, we are committed to providing a secure environment for our users. -Use this section to tell people about which versions of your project are -currently being supported with security updates. +--- -| Version | Supported | -| ------- | ------------------ | -| 5.1.x | :white_check_mark: | -| 5.0.x | :x: | -| 4.0.x | :white_check_mark: | -| < 4.0 | :x: | +## ✅ Supported Versions -## Reporting a Vulnerability +Security updates are provided for the latest stable release of eSim. Older releases may receive critical patches at the discretion of the core maintainers. -Use this section to tell people how to report a vulnerability. +| eSim Version | Status | Security Support | +| :--- | :--- | :--- | +| **2.5.x** | Current Stable | 🟢 Supported | +| **2.4.x** | Previous Stable | 🟡 Critical Fixes Only | +| **< 2.4** | End of Life | 🔴 Not Supported | -Tell them where to go, how often they can expect to get an update on a -reported vulnerability, what to expect if the vulnerability is accepted or -declined, etc. +--- + +## 🚨 Reporting a Vulnerability + +If you discover a security vulnerability in eSim (or its integration with bundled tools like Ngspice or GHDL), **please do not report it through public GitHub issues.** Instead, we ask that you practice responsible disclosure. + +### Where to Report +Please email your findings to the core security team at: +📧 **contact-esim@fossee.in** (Subject: `[SECURITY] Vulnerability Report`) + +### What to Include +To help us quickly understand and reproduce the issue, please include the following in your report: +- **Description:** A clear summary of the vulnerability and its potential impact (e.g., Local Privilege Escalation, Arbitrary Code Execution via crafted netlists). +- **Environment:** Your OS version, Python version, and the eSim version. +- **Reproduction Steps:** Step-by-step instructions, including any malicious/crafted `.cir`, `.sch`, or XML files used. +- **Proof of Concept (PoC):** Code snippets or a video demonstrating the exploit, if possible. + +### Expected Response Timeline +- **Acknowledgement:** We will acknowledge receipt of your vulnerability report within **48 hours**. +- **Assessment:** A preliminary assessment and timeline for a patch will be provided within **1 week**. +- **Fix & Disclosure:** We aim to release a patch and issue a CVE (if applicable) within **30-90 days**, depending on the severity and complexity of the issue. We will keep you updated throughout the process. + +--- + +## 🛡️ Scope of Security + +When reporting vulnerabilities, please keep in mind the architecture of eSim. + +### In-Scope (Please Report) +- Vulnerabilities in the core Python application (`src/` codebase). +- Arbitrary code execution triggered by opening malicious eSim projects, `.xml` files, or schematic files. +- Insecure handling of permissions or temporary directories during the KiCad-to-Ngspice conversion pipeline. + +### Out-of-Scope (Do Not Report Here) +- Upstream vulnerabilities strictly within the core engines of **KiCad**, **Ngspice**, or **GHDL** that are not exacerbated by eSim's wrapper implementations. Please report these directly to their respective upstream maintainers. +- Social engineering, phishing, or physical access attacks. + +--- + +*Thank you for helping keep the eSim community safe and secure!* From a5b6f583992e1db5f4c6e3181045cb9d1b6ae7bc Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 22:13:20 +0530 Subject: [PATCH 17/19] Update README.md --- README.md | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index fa61e53b8..2a1ee4c82 100644 --- a/README.md +++ b/README.md @@ -44,7 +44,11 @@ eSim is designed for electronics engineers, students, educators, and hobbyists who want a powerful yet cost-free alternative to proprietary EDA tools. It supports analog, digital, and **mixed-signal simulations**, including microcontroller integration. -> 📥 **Download**: [esim.fossee.in/downloads](https://esim.fossee.in/downloads)  |  📄 **User Manual**: [eSim Manual v2.5 (PDF)](https://static.fossee.in/esim/manuals/eSim_Manual_2.5.pdf)  |  📚 **Developer Docs**: [esim.readthedocs.io](https://esim.readthedocs.io/en/latest/) +

+ 📥 Download: v2.5 Release   |   + 📄 Manual: PDF Guide   |   + 📚 Docs: ReadTheDocs +

--- From 132331f9b9769bbf73688bbfa4d7f396ce206cd7 Mon Sep 17 00:00:00 2001 From: Mausam5055 Date: Mon, 1 Jun 2026 22:59:26 +0530 Subject: [PATCH 18/19] commit --- CONTRIBUTING.md | 15 +++-- .../SubcircuitLibrary/mc1496/mc1496.cir.out | 67 +++++++++++++------ library/subcircuitLibrary/MC1496/MC1496.cir | 36 ++++++---- 3 files changed, 80 insertions(+), 38 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 424390f5d..391fe9fec 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -192,10 +192,13 @@ A huge thank you to all **149+ amazing people** who have built eSim since 2015!
Sai Charan

18
-
Ajay Boddu

15 +
Mausam

17
+
Ajay Boddu

15 +

PSR

15

Suchinton

13

Karthick N.

13

Sabarish M.

12

Madhav K.

11

Ragul

11

Jawwaad

10

Tanisha

10

Ashok Kumar

10