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+ 
+ 
+ 
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+  + π₯ Sumanto Kar + + Lead Maintainer Β· 320 commits + 
+ |
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+  + π₯ Rahul Paknikar + + 265 commits +
+ |
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+  + π₯ Fahim Khan + + 244 commits +
+ |
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+
Auto-generated via contrib.rocks β View full list on GitHub β
+ +### π Community Contributors + +
+  Ankush 19 + |
+
+  Anup K. Pandey 19 + |
+
+  G Jaswanth 19 + |
+
+  E Kamalesh 18 + |
+
+  Sai Charan 18 + |
+
+  Mausam 17 + |
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+  Ajay Boddu 15 + |
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+  PSR 15 + |
+
+  Komal Sheth 15 + |
+
+  Dilip Boidya 15 + |
+
+  Nishit Bayen 14 + |
+
+  Suchinton 13 + |
+
+  Karthick N. 13 + |
+
+  Sabarish M. 12 + |
+
+  Harshal 11 + |
+
+  D Tharun 11 + |
+
+  Jovin P John 11 + |
+
+  Madhav K. 11 + |
+
+  Ragul 11 + |
+
+  Jawwaad 10 + |
+
+  Nirmitha N 10 + |
+
+  Pavan 10 + |
+
+  Senbagaseelan 10 + |
+
+  Tanisha 10 + |
+
+  Ashok Kumar 10 + |
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+ Thank you for contributing to eSim! β€οΈ
+ Every contribution, no matter how small, makes a difference.
+
+ 
+
+ An Open-Source EDA Tool for Circuit Design, Simulation, Analysis & PCB Design
+ Developed by FOSSEE Team at IIT Bombay
+
+ 
+ 
+ Features β’ + Architecture β’ + Installation β’ + Project Structure β’ + Tech Stack β’ + Contributing β’ + License +
+ +--- + +## π About + +**eSim** is a free and open-source EDA (Electronic Design Automation) tool for circuit design, simulation, analysis, and PCB design. It is an integrated tool built using open-source software such as **KiCad**, **Ngspice**, **GHDL**, and **Makerchip**, providing a seamless workflow from schematic capture to simulation results. + +eSim is designed for electronics engineers, students, educators, and hobbyists who want a powerful yet cost-free alternative to proprietary EDA tools. It supports analog, digital, and **mixed-signal simulations**, including microcontroller integration. + ++ π₯ Download: v2.5 Release | + π Manual: PDF Guide | + π Docs: ReadTheDocs +
+ +--- + +## β¨ Features + +| Category | Feature | Description | +|:---------|:--------|:------------| +| β’ **Design** | Schematic Capture | Draw circuit schematics using KiCad's schematic editor with eSim's custom symbol libraries | +| β’ **Conversion** | KiCad to Ngspice | Convert KiCad schematics to Ngspice-compatible netlists for simulation | +| β’ **Simulation** | Ngspice Engine | Run DC, AC, Transient, and other SPICE analyses with real-time interactive plots | +| β’ **Analysis** | Waveform Plotting | Visualize simulation results with matplotlib-based Python plots and Ngspice native plots | +| β’ **Model Editor** | Device Models | Create and edit SPICE device models (Diodes, BJTs, MOSFETs, JFETs, IGBTs, etc.) | +| β’ **Subcircuits** | Subcircuit Builder | Build, manage, and upload reusable subcircuit blocks | +| β’ **Mixed-Signal** | NGHDL Integration | Interface VHDL digital models (via GHDL) with analog Ngspice simulations | +| β’ **Verilog** | Makerchip + NgVeri | Use Makerchip IDE for Verilog/TL-Verilog design and convert to Ngspice models | +| β’ **PCB** | Layout Design | Design PCB layouts using KiCad's PCB editor with eSim's footprint libraries | +| β’ **Converters** | Schematic Import | Convert PSpice and LTSpice schematics/libraries to KiCad-compatible formats | +| β’ **Modelica** | Ngspice-to-Modelica | Convert Ngspice netlists to Modelica models for OpenModelica simulation | +| β’ **SKY130 PDK** | SkyWater 130nm | Support for SkyWater SKY130 open-source Process Design Kit | +| β’ **IHP PDK** | IHP OpenPDK | Integration with IHP SG13G2 open-source PDK for SiGe BiCMOS | + +--- + +## ποΈ Architecture + +### High-Level System Architecture + +```mermaid +graph TB + %% Styling + classDef ui fill:#2A3F54,stroke:#1ABB9C,stroke-width:2px,color:#fff + classDef core fill:#3E536C,stroke:#3498DB,stroke-width:2px,color:#fff + classDef engine fill:#1F2D3D,stroke:#E74C3C,stroke-width:2px,color:#fff + classDef data fill:#E9F0F5,stroke:#95A5A6,stroke-width:1px,color:#333 + + subgraph UI ["User Interface (PyQt6)"] + A[Application Main Window]:::ui + PE[Project Explorer]:::ui + DA[Dock Area Workspace]:::ui + TE[Time Explorer]:::ui + CON[Console Widget]:::ui + + A --> PE & DA & TE & CON + end + + subgraph CORE ["Core Python Modules"] + K2N[KiCad-to-Ngspice]:::core + SIM[Ngspice Simulator]:::core + PLT[Matplotlib Plotter]:::core + ME[Model Editor]:::core + SC[Subcircuit Builder]:::core + + DA --> K2N & SIM & ME & SC + end + + subgraph INTEGRATION ["Mixed-Signal & External APIs"] + NGHDL[NGHDL Interface]:::core + MKR[Makerchip/NgVeri]:::core + MOD[Modelica Converter]:::core + CONV[PSpice/LTSpice Converter]:::core + + DA --> NGHDL & MKR & MOD & CONV + end + + subgraph ENGINES ["Simulation & EDA Engines"] + KICAD[KiCad Eeschema]:::engine + PCB[KiCad Pcbnew]:::engine + NGSPICE[Ngspice Backend]:::engine + GHDL[GHDL Simulator]:::engine + VER[Verilator]:::engine + OM[OpenModelica]:::engine + end + + %% Data Flow + XML[(Netlist / XML)]:::data + RAW[(Raw Data / txt)]:::data + VHDL[(VHDL Files)]:::data + + K2N -- Generates --> XML + XML -- Consumed by --> NGSPICE + SIM -- Triggers --> NGSPICE + NGSPICE -- Outputs --> RAW + RAW -- Parsed by --> PLT + + NGHDL -- Compiles --> VHDL + VHDL -- Simulated by --> GHDL + GHDL -- Co-simulates --> NGSPICE + + MKR -- Verilog/TL-V --> VER + + KICAD -- Schematic --> K2N + KICAD -- Netlist --> PCB +``` + +*For detailed simulation workflows, sub-system operations, and system flowcharts, please refer to our [Architecture & Workflows Guide](ARCHITECTURE.md).* + +--- + +## π Project Structure + +### Root Directory + +| Path | Type | Description | +|:-----|:-----|:------------| +| `src/` | π Directory | **Core application source code** β all Python modules for the eSim GUI and backend | +| `library/` | π Directory | **Component libraries** β device models, KiCad symbols, subcircuits, and PDK data | +| `nghdl/` | π Directory | **NGHDL module** β Ngspice-GHDL interface for mixed-signal VHDL simulation | +| `Examples/` | π Directory | **42 example projects** β ready-to-simulate circuits (RC, BJT, Op-Amp, Mixed-Signal, etc.) | +| `images/` | π Directory | **UI assets** β application icons, toolbar images, logos, and splash screen | +| `scripts/` | π Directory | **Launch & setup scripts** β shell scripts for Linux installation and launching | +| `docs/` | π Directory | **Sphinx documentation** β RST files for ReadTheDocs auto-generated developer docs | +| `code/` | π Directory | **Sphinx autodoc config** β mirrors `src/` structure for API documentation generation | +| `flatpak/` | π Directory | **Flatpak packaging** β manifest and wrapper scripts for universal Linux distribution | +| `appimage/` | π Directory | **AppImage packaging** β build scripts for portable Linux AppImage bundles | +| `docker-launcher/` | π Directory | **Docker support** β Dockerfile, launcher script, and CI workflows for containerized builds | +| `snap/` | π Directory | **Snap packaging** β `snapcraft.yaml` for building Snap packages | +| `ihp/` | π Directory | **IHP PDK integration** β install script for IHP SG13G2 open-source SiGe BiCMOS PDK | +| `patches/` | π Directory | **Source patches** β patch files for modifying Ngspice/GHDL behavior in sandboxed environments | +| `.github/` | π Directory | **GitHub config** β issue templates, PR templates, and CI/CD workflow definitions | +| `setup.py` | π File | Python package configuration for pip installation | +| `requirements.txt` | π File | Python dependency list (PyQt6, matplotlib, numpy, scipy, etc.) | +| `conf.py` | π File | Sphinx documentation configuration | +| `VERSION` | π File | Current version identifier (`2.5`) | +| `INSTALL` | π File | Detailed multi-platform installation instructions | +| `LICENSE` | π File | GNU General Public License v3.0 | + +### Source Code (`src/`) β Detailed Module Breakdown + +``` +src/ +βββ frontEnd/ # GUI & Main Application +β βββ Application.py # Main window, toolbar setup, menu actions (960 lines) +β βββ DockArea.py # Tabbed dock workspace for editors/simulators (24K) +β βββ ProjectExplorer.py # File tree browser for project navigation (20K) +β βββ TimeExplorer.py # Project snapshot/version management (8K) +β βββ TerminalUi.py # Embedded terminal widget (5K) +β βββ Workspace.py # Workspace selection dialog (6K) +β +βββ kicadtoNgspice/ # KiCad-to-Ngspice Conversion Engine +β βββ KicadtoNgspice.py # Main conversion controller & UI (41K) +β βββ Convert.py # Netlist parsing and SPICE generation (40K) +β βββ Analysis.py # Analysis type configuration (DC, AC, Transient) (32K) +β βββ DeviceModel.py # Device model parameter handling (56K) +β βββ Source.py # Source component configuration (15K) +β βββ Processing.py # Netlist processing pipeline (26K) +β βββ SubcircuitTab.py # Subcircuit selection in converter (9K) +β βββ Microcontroller.py # Microcontroller model support (10K) +β βββ Model.py # Model file handling (6K) +β βββ TrackWidget.py # UI tracking widget (1K) +β +βββ ngspiceSimulation/ # Simulation Engine & Plotting +β βββ NgspiceWidget.py # Ngspice process management & execution (16K) +β βββ plot_window.py # matplotlib-based waveform plotter (66K) +β βββ plotting_widgets.py # Custom plot controls and widgets (8K) +β βββ data_extraction.py # Simulation data file parser (11K) +β +βββ modelEditor/ # SPICE Model Editor +β βββ ModelEditor.py # GUI for creating/editing device models (33K) +β +βββ subcircuit/ # Subcircuit Management +β βββ Subcircuit.py # Subcircuit manager main window (3K) +β βββ newSub.py # Create new subcircuit (3K) +β βββ openSub.py # Open existing subcircuit (1K) +β βββ uploadSub.py # Upload subcircuit to library (4K) +β βββ convertSub.py # Subcircuit format conversion (2K) +β +βββ maker/ # Makerchip & NgVeri Integration +β βββ Maker.py # Makerchip IDE integration (23K) +β βββ NgVeri.py # Verilog-to-Ngspice model generator (17K) +β βββ ModelGeneration.py # Auto model generation pipeline (48K) +β βββ createkicad.py # KiCad symbol creation for models (14K) +β βββ makerchip.py # Makerchip cloud IDE connector (3K) +β βββ Appconfig.py # Maker-specific configuration (2K) +β +βββ converter/ # Schematic Format Converters +β βββ pspiceToKicad.py # PSpice schematic importer (5K) +β βββ ltspiceToKicad.py # LTSpice schematic importer (6K) +β βββ libConverter.py # Library format converter (3K) +β βββ LtspiceLibConverter.py # LTSpice library converter (4K) +β βββ browseSchematic.py # File browser for schematics (550B) +β βββ LTSpiceToKiCadConverter/ # LTSpice conversion engine +β βββ schematic_converters/ # Additional schematic parsers +β +βββ ngspicetoModelica/ # π Ngspice-to-Modelica Converter +β βββ NgspicetoModelica.py # Core conversion engine (54K) +β βββ ModelicaUI.py # Modelica converter GUI (10K) +β +βββ configuration/ # βοΈ Application Configuration +β βββ Appconfig.py # Global config, paths, process tracking (4K) +β +βββ projManagement/ # π Project Management +β βββ Kicad.py # KiCad integration (launch schematic/PCB editor) (9K) +β βββ Validation.py # Tool and file validation utilities (7K) +β βββ Worker.py # Background process/thread management (3K) +β βββ newProject.py # New project creation logic (5K) +β βββ openProject.py # Open existing project logic (3K) +β +βββ browser/ # π Help & Documentation + βββ Welcome.py # Welcome screen display (941B) + βββ UserManual.py # User manual viewer (731B) +``` + +### Library Directory (`library/`) β Component Libraries + +| Path | Description | +|:-----|:------------| +| `deviceModelLibrary/` | SPICE device models organized by type: Diode, BJT (Transistor), MOSFET (MOS), JFET, IGBT, LEDs, Switches, Transmission Lines, and user libraries | +| `kicadLibrary/` | KiCad schematic symbols (`eSim-symbols/`), footprint libraries (`kicad_eSim-Library/`), and project templates | +| `SubcircuitLibrary/` | Reusable subcircuit definitions for common circuit blocks | +| `modelParamXML/` | XML parameter definitions for device model editor forms | +| `ngspicetoModelica/` | Mapping files for Ngspice-to-Modelica component translation | +| `browser/` | HTML/resource files for the built-in help browser | +| `tlv/` | TL-Verilog support files for Makerchip integration | + +### NGHDL Module (`nghdl/`) β Mixed-Signal Interface + +| Path | Description | +|:-----|:------------| +| `src/ngspice_ghdl.py` | Core interface: manages VHDL upload, GHDL compilation, and Ngspice code model creation | +| `src/model_generation.py` | Generates C code models from VHDL port definitions for Ngspice | +| `src/createKicadLibrary.py` | Auto-generates KiCad symbols from VHDL entity definitions | +| `src/ghdlserver/` | GHDL foreign interface server for inter-process communication with Ngspice | +| `install-nghdl.sh` | Automated installer for NGHDL dependencies (GHDL, Verilator, Ngspice) | +| `Example/` | Example VHDL models and mixed-signal simulation projects | + +--- + +## π οΈ Tech Stack + +| Layer | Technology | Purpose | +|:------|:-----------|:--------| +| **Language** |  | Core application logic | +| **GUI Framework** |  | Desktop GUI (windows, dialogs, toolbars, docks) | +| **Plotting** |  | Waveform visualization and data plotting | +| **Numerics** |   | Numerical computation and signal processing | +| **Schematic & PCB** |  | Schematic capture and PCB layout design | +| **SPICE Simulation** |  | Analog/mixed-signal circuit simulation engine | +| **VHDL Simulation** |  | VHDL analysis, compilation, and simulation | +| **Verilog** |  | Verilog HDL simulation and model generation | +| **HDL Cloud IDE** |  | Online Verilog/TL-Verilog IDE integration | +| **Modelica** |  | Multi-domain modeling and simulation | +| **PDK** |  | SkyWater 130nm open-source process design kit | +| **Packaging** |   | Cross-distribution Linux packaging & containers | +| **Documentation** |   | Auto-generated developer documentation | +| **CI/CD** |  | Automated builds, Docker images, and releases | + +### Key Python Dependencies + +| Package | Version | Purpose | +|:--------|:--------|:--------| +| `PyQt6` | β₯ 6.5.0 | GUI framework | +| `matplotlib` | 3.7.5 | Waveform plotting | +| `numpy` | 1.24.4 | Numerical computation | +| `scipy` | 1.10.1 | Scientific computing | +| `pillow` | 12.2.0 | Image processing | +| `hdlparse` | 1.0.4 | HDL file parsing | +| `watchdog` | 4.0.2 | File system monitoring | +| `pyparsing` | 3.1.4 | Parser building toolkit | + +--- + +## π» Installation + +### Supported Platforms + +| Platform | Method | Status | +|:---------|:-------|:------:| +| **All Linux** (Fedora, Ubuntu, openSUSE, Arch, etc.) | Flatpak | β Recommended | +| **Ubuntu** 22.04 / 23.04 / 24.04 LTS | Native Installer | β Supported | +| **Windows** 8 / 10 / 11 | Windows Installer | β Supported | +| **Docker** (any OS) | Docker Container | β Supported | + +### π§ Linux β Flatpak (Recommended for all distributions) + ```bash +# 1. Install Flatpak (if not already installed) +# Fedora: sudo dnf install flatpak +# Ubuntu: sudo apt install flatpak +# openSUSE: sudo zypper install flatpak +# Arch: sudo pacman -S flatpak + +# 2. Add Flathub repository +flatpak remote-add --if-not-exists flathub https://dl.flathub.org/repo/flathub.flatpakrepo + +# 3. Install eSim flatpak install flathub org.fossee.eSim + +# 4. Run eSim flatpak run org.fossee.eSim ``` -Or build from source: `flatpak-builder build flatpak/org.fossee.eSim.yml --install --user` -**For Ubuntu and Windows:** Please refer to [downloads](https://esim.fossee.in/downloads) for installation guidelines. +> **β οΈ Flatpak Limitations:** NGHDL, Makerchip, and SKY130 PDK are not included in the Flatpak build. For full mixed-signal support, use the Ubuntu native installer. + +### π§ Ubuntu β Native Installer + +```bash +# 1. Download and extract eSim +unzip eSim-2.5.zip +cd eSim-2.5 + +# 2. Install eSim with all dependencies +chmod +x install-eSim.sh +./install-eSim.sh --install + +# 3. Run eSim +esim +# Or double-click the eSim desktop icon +``` + +### πͺ Windows + +1. Download the eSim installer from [esim.fossee.in/downloads](https://esim.fossee.in/downloads) +2. Disable antivirus temporarily (if required) +3. **Important:** Remove MinGW/MSYS from the PATH environment variable if previously installed +4. Run the installer and follow the on-screen instructions +5. Launch eSim from the Start Menu or desktop shortcut + +### π Docker + +Refer to the [Docker Launcher README](docker-launcher/README.md) for instructions on running eSim in a containerized environment. + +### π¦ Build from Source (Flatpak) + +```bash +cd eSim +flatpak-builder build flatpak/org.fossee.eSim.yml --install --user +``` + +> π For comprehensive installation instructions, see the [INSTALL](INSTALL) file. + +--- + +## π CI/CD & Packaging + +| Workflow | File | Purpose | +|:---------|:-----|:--------| +| Docker Image Build | `.github/workflows/docker-image.yml` | Builds and publishes the eSim Docker image | +| Docker Launcher Build | `.github/workflows/docker-launcher-build.yml` | Builds the cross-platform Python launcher | +| Ubuntu Release | `.github/workflows/release_ubuntu.yml` | Automated Ubuntu `.deb` package builds | + +| Packaging Format | Directory | Description | +|:-----------------|:----------|:------------| +| Flatpak | `flatpak/` | Universal Linux package via Flathub | +| AppImage | `appimage/` | Portable single-file Linux executable | +| Snap | `snap/` | Ubuntu Snap Store package | +| Docker | `docker-launcher/` | Containerized distribution with GUI forwarding | + +--- + +## π Example Projects + +eSim ships with **42 ready-to-simulate example projects** in the `Examples/` directory: + +|
+
+ + π₯ Sumanto Kar + + Lead Maintainer Β· 320 commits + |
+
+
+ + π₯ Rahul Paknikar + + 265 commits + |
+
+
+ + π₯ Fahim Khan + + 244 commits + |
+
+
+
+
+
149+ contributors and counting! View all contributors β
+ +--- -See [INSTALL](INSTALL) for detailed installation instructions for all platforms. +## π Contact & Support -## Features -* An open-source EDA tool. -* Perform Circuit Design. -* Perform Simulation. -* Perform Layout Design. -* Model and Subcircuit builder. -* Support for Mixed-Signal Simulations including Microcontrollers. -* eSim has been successfully ported to low cost FOSSEE [laptop](https://laptop.fossee.in/) +| Channel | Link | +|:--------|:-----| +| π§ **Email** | [contact-esim@fossee.in](mailto:contact-esim@fossee.in) | +| π **Website** | [esim.fossee.in](https://esim.fossee.in/) | +| π¬ **Forum** | [forums.fossee.in](https://forums.fossee.in/) | +| π **Contact Page** | [esim.fossee.in/contact-us](https://esim.fossee.in/contact-us) | +| π **User Manual** | [eSim Manual v2.5 (PDF)](https://static.fossee.in/esim/manuals/eSim_Manual_2.5.pdf) | +| π **Developer Docs** | [esim.readthedocs.io](https://esim.readthedocs.io/en/latest/) | -## Open-Source Softwares Used -* [Python](https://www.python.org/) -* [KiCad](https://www.kicad.org/) -* [NGHDL](https://github.com/fossee/nghdl/) -* [Makerchip](https://www.makerchip.com/) -* [SkyWater SKY130 PDK](https://skywater-pdk.rtfd.io/) +--- -## eSim Manual -To know everything about eSim, how it works and it's feature please download the manual from [here](https://static.fossee.in/esim/manuals/eSim_Manual_2.5.pdf) -## Contact -For any queries regarding eSim please write us on at this [email address](mailto:contact-esim@fossee.in). -Other Contact Details are available [here](https://esim.fossee.in/contact-us). ++ Built with β€οΈ by the FOSSEE Team at IIT Bombay +
-## Contribution -Please refer [here](https://github.com/FOSSEE/eSim/blob/master/CONTRIBUTION.md) for further details. + -## License -It is developed by FOSSEE Team at IIT Bombay and is released under GNU GPL License. ++ β If you find eSim useful, consider giving it a star on GitHub! +
diff --git a/SECURITY.md b/SECURITY.md index 034e84803..a4d483fb3 100644 --- a/SECURITY.md +++ b/SECURITY.md @@ -1,21 +1,56 @@ -# Security Policy +# π Security Policy -## Supported Versions +The eSim project takes security seriously. As a desktop EDA application handling various local file formats, external executables (Ngspice, GHDL, KiCad), and third-party models, we are committed to providing a secure environment for our users. -Use this section to tell people about which versions of your project are -currently being supported with security updates. +--- -| Version | Supported | -| ------- | ------------------ | -| 5.1.x | :white_check_mark: | -| 5.0.x | :x: | -| 4.0.x | :white_check_mark: | -| < 4.0 | :x: | +## β Supported Versions -## Reporting a Vulnerability +Security updates are provided for the latest stable release of eSim. Older releases may receive critical patches at the discretion of the core maintainers. -Use this section to tell people how to report a vulnerability. +| eSim Version | Status | Security Support | +| :--- | :--- | :--- | +| **2.5.x** | Current Stable | π’ Supported | +| **2.4.x** | Previous Stable | π‘ Critical Fixes Only | +| **< 2.4** | End of Life | π΄ Not Supported | -Tell them where to go, how often they can expect to get an update on a -reported vulnerability, what to expect if the vulnerability is accepted or -declined, etc. +--- + +## π¨ Reporting a Vulnerability + +If you discover a security vulnerability in eSim (or its integration with bundled tools like Ngspice or GHDL), **please do not report it through public GitHub issues.** Instead, we ask that you practice responsible disclosure. + +### Where to Report +Please email your findings to the core security team at: +π§ **contact-esim@fossee.in** (Subject: `[SECURITY] Vulnerability Report`) + +### What to Include +To help us quickly understand and reproduce the issue, please include the following in your report: +- **Description:** A clear summary of the vulnerability and its potential impact (e.g., Local Privilege Escalation, Arbitrary Code Execution via crafted netlists). +- **Environment:** Your OS version, Python version, and the eSim version. +- **Reproduction Steps:** Step-by-step instructions, including any malicious/crafted `.cir`, `.sch`, or XML files used. +- **Proof of Concept (PoC):** Code snippets or a video demonstrating the exploit, if possible. + +### Expected Response Timeline +- **Acknowledgement:** We will acknowledge receipt of your vulnerability report within **48 hours**. +- **Assessment:** A preliminary assessment and timeline for a patch will be provided within **1 week**. +- **Fix & Disclosure:** We aim to release a patch and issue a CVE (if applicable) within **30-90 days**, depending on the severity and complexity of the issue. We will keep you updated throughout the process. + +--- + +## π‘οΈ Scope of Security + +When reporting vulnerabilities, please keep in mind the architecture of eSim. + +### In-Scope (Please Report) +- Vulnerabilities in the core Python application (`src/` codebase). +- Arbitrary code execution triggered by opening malicious eSim projects, `.xml` files, or schematic files. +- Insecure handling of permissions or temporary directories during the KiCad-to-Ngspice conversion pipeline. + +### Out-of-Scope (Do Not Report Here) +- Upstream vulnerabilities strictly within the core engines of **KiCad**, **Ngspice**, or **GHDL** that are not exacerbated by eSim's wrapper implementations. Please report these directly to their respective upstream maintainers. +- Social engineering, phishing, or physical access attacks. + +--- + +*Thank you for helping keep the eSim community safe and secure!* diff --git a/library/SubcircuitLibrary/mc1496/mc1496.cir.out b/library/SubcircuitLibrary/mc1496/mc1496.cir.out index c0008ca7c..1db9091db 100644 --- a/library/SubcircuitLibrary/mc1496/mc1496.cir.out +++ b/library/SubcircuitLibrary/mc1496/mc1496.cir.out @@ -1,25 +1,54 @@ -* c:\fossee\esim\library\subcircuitlibrary\mc1496\mc1496.cir - -.include NPN.lib -q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 -q5 net-_q5-pad1_ net-_q5-pad2_ net-_q2-pad3_ Q2N2222 -q6 net-_q2-pad1_ net-_q5-pad2_ net-_q6-pad3_ Q2N2222 -q9 net-_q5-pad1_ net-_q2-pad2_ net-_q6-pad3_ Q2N2222 -q3 net-_q2-pad3_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 -q4 net-_q3-pad3_ net-_q1-pad1_ net-_q4-pad3_ Q2N2222 -q7 net-_q6-pad3_ net-_q7-pad2_ net-_q7-pad3_ Q2N2222 -q8 net-_q7-pad3_ net-_q1-pad1_ net-_q8-pad3_ Q2N2222 -q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2222 -r2 net-_q4-pad3_ net-_r1-pad2_ 500 -r1 net-_q1-pad3_ net-_r1-pad2_ 500 -r3 net-_q8-pad3_ net-_r1-pad2_ 500 -* u1 net-_q7-pad2_ net-_q7-pad3_ net-_q3-pad3_ net-_q3-pad2_ net-_q1-pad1_ net-_q2-pad1_ ? net-_q2-pad2_ ? net-_q5-pad2_ ? net-_q5-pad1_ ? net-_r1-pad2_ port -.tran 0.1e-06 10e-03 0e-03 - -* Control Statements +.title kicad schematic + +.include NMOS-180nm.lib +.include userDiode.lib + +* ---------- Power Supplies ---------- +* define a 5V DC supply between VDD and GND +VDD vdd 0 DC 5 +VEE vee 0 DC 0 +Vbias bias 0 DC 1.2 + +* ---------- Input Sources ---------- +* give each input node a small signal so theyre not floating +Vsig1 signal_input_1 0 SIN(0 1 1k) +Vsig2 signal_input_2 0 SIN(0 1 1k) +Vcar1 carrier_input_1 0 SIN(0 1 10k) +Vcar2 carrier_input_2 0 SIN(0 1 10k) + +* ---------- Circuit ---------- +r1 vee net-_r1-pad2_ 500k +d1 bias net-_r1-pad2_ D1N750 +r2 vee net-_m3-pad3_ 500k +m3 gain_adjust_2 bias net-_m3-pad3_ vee CMOSN W=100u L=100u M=1 +m2 net-_m1-pad3_ signal_input_1 gain_adjust_2 vee CMOSN W=100u L=100u M=1 +m4 net-_m1-pad3_ carrier_input_1 output1 vee CMOSN W=100u L=100u M=1 +m1 output1 carrier_input_2 net-_m1-pad3_ vee CMOSN W=100u L=100u M=1 +m6 gain_adjust_1 bias net-_m6-pad3_ vee CMOSN W=100u L=100u M=1 +r3 vee net-_m6-pad3_ 500k +m7 gain_adjust_1 signal_input_2 net-_m5-pad3_ vee CMOSN W=100u L=100u M=1 +m8 net-_m5-pad3_ carrier_input_2 output1 vee CMOSN W=100u L=100u M=1 +m5 output1 carrier_input_1 net-_m5-pad3_ vee CMOSN W=100u L=100u M=1 + +.option method=gear reltol=0.01 abstol=1e-6 itl1=1000 +.ic v(bias)=1.2 + +.tran 0.1ms 50ms + +* ---------- Control Section ---------- .control run print allv > plot_data_v.txt print alli > plot_data_i.txt + +* Plot useful nodes (these exist now) +plot v(bias) +plot v(signal_input_1) +plot v(signal_input_2) +plot v(carrier_input_1) +plot v(carrier_input_2) +plot v(output1) +plot v(gain_adjust_1) +plot v(gain_adjust_2) .endc .end diff --git a/library/subcircuitLibrary/MC1496/MC1496.cir b/library/subcircuitLibrary/MC1496/MC1496.cir index b114973d5..b9067a27b 100644 --- a/library/subcircuitLibrary/MC1496/MC1496.cir +++ b/library/subcircuitLibrary/MC1496/MC1496.cir @@ -1,15 +1,23 @@ -.title KiCad schematic -M6 gain1 bias Net-_M6-Pad3_ gnd eSim_MOS_N -R3 gnd Net-_M6-Pad3_ 500k -U4 signal_input_1 gain1 gain2 signal_input_2 bias output1 unconnected-_U4-Pad7_ carrier_input_1 unconnected-_U4-Pad9_ carrier_input_2 unconnected-_U4-Pad11_ output1 unconnected-_U4-Pad13_ gnd PORT -R2 gnd Net-_M3-Pad3_ 500k -M2 Net-_M1-Pad3_ signal_input_1 gain2 gnd eSim_MOS_N -M3 gain2 bias Net-_M3-Pad3_ gnd eSim_MOS_N -M4 Net-_M1-Pad3_ carrier_input_1 output1 gnd eSim_MOS_N -M1 output1 carrier_input_2 Net-_M1-Pad3_ gnd eSim_MOS_N -D1 bias Net-_D1-Pad2_ eSim_Diode -R1 gnd Net-_D1-Pad2_ 500k -M5 output1 carrier_input_1 Net-_M5-Pad3_ gnd eSim_MOS_N -M7 gain1 signal_input_2 Net-_M5-Pad3_ gnd eSim_MOS_N -M8 Net-_M5-Pad3_ carrier_input_2 output1 gnd eSim_MOS_N +* C:\FOSSEE\eSim\library\SubcircuitLibrary\mc1496\mc1496.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/12/25 22:39:35 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q5 Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q2-Pad1_ Net-_Q5-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q9 Net-_Q5-Pad1_ Net-_Q2-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q3 Net-_Q2-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q3-Pad3_ Net-_Q1-Pad1_ Net-_Q4-Pad3_ eSim_NPN +Q7 Net-_Q6-Pad3_ Net-_Q7-Pad2_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q7-Pad3_ Net-_Q1-Pad1_ Net-_Q8-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad3_ eSim_NPN +R2 Net-_Q4-Pad3_ Net-_R1-Pad2_ 500 +R1 Net-_Q1-Pad3_ Net-_R1-Pad2_ 500 +R3 Net-_Q8-Pad3_ Net-_R1-Pad2_ 500 +U1 Net-_Q7-Pad2_ Net-_Q7-Pad3_ Net-_Q3-Pad3_ Net-_Q3-Pad2_ Net-_Q1-Pad1_ Net-_Q2-Pad1_ ? Net-_Q2-Pad2_ ? Net-_Q5-Pad2_ ? Net-_Q5-Pad1_ ? Net-_R1-Pad2_ PORT + .end
+ 
+