+ + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +ADKCON 09E W P Audio, disk, control write +ADKCONR 010 R P Audio, disk, control read + + BIT# USE + ---- ------------------------------------ + 15 SET/CLR Set/clear control bit. Determines if bits + written with a 1 get set or cleared. Bits + written with a zero are always unchanged. + 14-13 PRECOMP 1-0 + + CODE PRECOMP VALUE + ---- ------------- + 00 none + 01 140 ns + 10 280 ns + 11 560 ns + + 12 MFMPREC ( 1=MFM precomp 0=GCR precomp) + 11 UARTBRK Forces a UART break (clears TXD) if true. + 10 WORDSYNC Enables disk read synchronizing on a word + equal to DISK SYNC CODE, located in + address (3F)*2. + 09 MSBSYNC Enables disk read synchronizing on the MSB + (most significant bit). Appl type GCR. + 08 FAST Disk data clock rate control 1=fast(2us) 0=slow(4us). + (fast for MFM, slow for MFM or GCR) + + 07 USE3PN Use audio channel 3 to modulate nothing. + 06 USE2P3 Use audio channel 2 to modulate period of channel 3. + 05 USE1P2 Use audio channel 1 to modulate period of channel 2. + 04 USE0P1 Use audio channel 0 to modulate period of channel 1. + + 03 USE3VN Use audio channel 3 to modulate nothing. + 02 USE2V3 Use audio channel 2 to modulate volume of channel 3. + 01 USE1V2 Use audio channel 1 to modulate volume of channel 2. + 00 USE0V1 Use audio channel 0 to modulate volume of channel 1. + + NOTE: If both period and volume are modulated on the + same channel, the period and volume will be alternated. + First word xxxxxxxx V6-V0 , Second word P15-P0 (etc) + + ++ + diff --git a/sources/official/saga-registers/adkcon2.htm b/sources/official/saga-registers/adkcon2.htm new file mode 100755 index 0000000..44d7230 --- /dev/null +++ b/sources/official/saga-registers/adkcon2.htm @@ -0,0 +1,32 @@ + + +
+ +INTREQ2 + + This register contains detailed Sprite collision detection + + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 15 | | SET/CLR | + | 14 | | | + | 13 | ETH | Ethernet | + | 12 | | | + | 11 | AUD15 | Audio channel 15 block finished | + | 10 | AUD14 | Audio channel 14 block finished | + | 09 | AUD13 | Audio channel 13 block finished | + | 08 | AUD12 | Audio channel 12 block finished | + | 07 | AUD11 | Audio channel 11 block finished | + | 06 | AUD10 | Audio channel 10 block finished | + | 05 | AUD9 | Audio channel 9 block finished | + | 04 | AUD8 | Audio channel 8 block finished | + | 03 | AUD7 | Audio channel 7 block finished | + | 02 | AUD6 | Audio channel 6 block finished | + | 01 | AUD5 | Audio channel 5 block finished | + | 00 | AUD4 | Audio channel 4 block finished | + +-------+----------+-------------------------------------------+ ++ + diff --git a/sources/official/saga-registers/adkconr.htm b/sources/official/saga-registers/adkconr.htm new file mode 100755 index 0000000..de1ccf2 --- /dev/null +++ b/sources/official/saga-registers/adkconr.htm @@ -0,0 +1,51 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +ADKCON 09E W P Audio, disk, control write +ADKCONR 010 R P Audio, disk, control read + + BIT# USE + ---- ------------------------------------ + 15 SET/CLR Set/clear control bit. Determines if bits + written with a 1 get set or cleared. Bits + written with a zero are always unchanged. + 14-13 PRECOMP 1-0 + + CODE PRECOMP VALUE + ---- ------------- + 00 none + 01 140 ns + 10 280 ns + 11 560 ns + + 12 MFMPREC ( 1=MFM precomp 0=GCR precomp) + 11 UARTBRK Forces a UART break (clears TXD) if true. + 10 WORDSYNC Enables disk read synchronizing on a word + equal to DISK SYNC CODE, located in + address (3F)*2. + 09 MSBSYNC Enables disk read synchronizing on the MSB + (most significant bit). Appl type GCR. + 08 FAST Disk data clock rate control 1=fast(2us) 0=slow(4us). + (fast for MFM, slow for MFM or GCR) + + 07 USE3PN Use audio channel 3 to modulate nothing. + 06 USE2P3 Use audio channel 2 to modulate period of channel 3. + 05 USE1P2 Use audio channel 1 to modulate period of channel 2. + 04 USE0P1 Use audio channel 0 to modulate period of channel 1. + + 03 USE3VN Use audio channel 3 to modulate nothing. + 02 USE2V3 Use audio channel 2 to modulate volume of channel 3. + 01 USE1V2 Use audio channel 1 to modulate volume of channel 2. + 00 USE0V1 Use audio channel 0 to modulate volume of channel 1. + + NOTE: If both period and volume are modulated on the + same channel, the period and volume will be alternated. + First word xxxxxxxx V6-V0 , Second word P15-P0 (etc) ++ + \ No newline at end of file diff --git a/sources/official/saga-registers/audnvol.htm b/sources/official/saga-registers/audnvol.htm new file mode 100755 index 0000000..0919748 --- /dev/null +++ b/sources/official/saga-registers/audnvol.htm @@ -0,0 +1,21 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +AUDnVOL DFF4n8 W P Audio channel x stereo volume + + This register contains the stereo volume setting for + audio channel x. + + Bit# Use + ---- -------------------------- + 15-08 Left Volume + 07-00 Right Volume + ++ + diff --git a/sources/official/saga-registers/audxctrl.htm b/sources/official/saga-registers/audxctrl.htm new file mode 100755 index 0000000..2c50f88 --- /dev/null +++ b/sources/official/saga-registers/audxctrl.htm @@ -0,0 +1,26 @@ + + +
+ +AUDCTRL + + 16bit Audio CONTROL Register + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 2 | Stereo | 16bit/16bit interleaved mode - 64bit align | + | 1 | OneShot | Channel will turn itself off at sample end | + | 0 | 16bit | 0=8bit, 1=16bit samples | + +-------+----------+-------------------------------------------+ + +Supported format: + +8bit signed mono. Data stored in pairs, data aligment 16bit +16bit signed mono, Data stored in pairs, data alignment 32bit +Left/Rigth signed 16bit stereo, Data in memory in pairs, memory alignment 64bit + + ++ + diff --git a/sources/official/saga-registers/audxdat.htm b/sources/official/saga-registers/audxdat.htm new file mode 100755 index 0000000..c621588 --- /dev/null +++ b/sources/official/saga-registers/audxdat.htm @@ -0,0 +1,24 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +AUDxDAT 0AA W P Audio channel x data + + This register is the audio channel x (x=0,1,2,3) + DMA data buffer. It contains 2 bytes of data that + are each 2's complement and are outputted + sequentially (with digital-to-analog conversion) + to the audio output pins. (LSB = 3 MV) The DMA + controller automatically transfers data to this + register from RAM. The processor can also write + directly to this register. When the DMA data is + finished (words outputted=length) and the data in + this register has been used, an audio channel + interrupt request is set. ++ + diff --git a/sources/official/saga-registers/audxl.htm b/sources/official/saga-registers/audxl.htm new file mode 100755 index 0000000..8f678e0 --- /dev/null +++ b/sources/official/saga-registers/audxl.htm @@ -0,0 +1,11 @@ + + +
+ +AUD_PTR + + 32bit pointer to Audio data. + ++ + diff --git a/sources/official/saga-registers/audxlch.htm b/sources/official/saga-registers/audxlch.htm new file mode 100755 index 0000000..7f0f75d --- /dev/null +++ b/sources/official/saga-registers/audxlch.htm @@ -0,0 +1,22 @@ + + +
+ + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +AUDxLCH 0A0 W A( E ) Audio channel x location (high 3 bits, + 5 bits if ECS) +AUDxLCL 0A2 W A Audio channel x location (low 15 bits) + + This pair of registers contains the 18 bit starting + address (location) of audio channel x (x=0,1,2,3) DMA + data. This is not a pointer register and therefore needs + to be reloaded only if a different memory location is to + be outputted. + ++ + \ No newline at end of file diff --git a/sources/official/saga-registers/audxlen.htm b/sources/official/saga-registers/audxlen.htm new file mode 100755 index 0000000..a86a4e7 --- /dev/null +++ b/sources/official/saga-registers/audxlen.htm @@ -0,0 +1,12 @@ + + +
+ +AUDLEN + + 32bit length of audio data. + Count is in pair of samples! + ++ + diff --git a/sources/official/saga-registers/audxper.htm b/sources/official/saga-registers/audxper.htm new file mode 100755 index 0000000..29db542 --- /dev/null +++ b/sources/official/saga-registers/audxper.htm @@ -0,0 +1,19 @@ + + +
+ +AUDPER + + 16bit PERIOD COUNT + + This register contains the period (rate) of + audio channel x DMA data transfer. + The minimum period is 65 color clocks. This means + that the smallest number that should be placed in + this register is 65 decimal. This corresponds to + a maximum sample frequency of 56 khz. + + ++ + diff --git a/sources/official/saga-registers/audxvol.htm b/sources/official/saga-registers/audxvol.htm new file mode 100755 index 0000000..b29109d --- /dev/null +++ b/sources/official/saga-registers/audxvol.htm @@ -0,0 +1,24 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +AUDxVOL 0A8 W P Audio channel x volume + + This register contains the volume setting for + audio channel x. Bits 6,5,4,3,2,1,0 specify 65 + linear volume levels as shown below. + + Bit# Use + ---- -------------------------- + 15-07 Not used + 06 Forces volume to max (64 ones, no zeros) + 05-00 Sets one of 64 levels (000000=no output + (111111=63 1s, one 0) + ++ + diff --git a/sources/official/saga-registers/audxvol2.htm b/sources/official/saga-registers/audxvol2.htm new file mode 100755 index 0000000..0c8182d --- /dev/null +++ b/sources/official/saga-registers/audxvol2.htm @@ -0,0 +1,25 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +AUDxVOL 0A8 W P Audio channel x volume + + This register contains the volume setting for + audio channel x. Bits 6,5,4,3,2,1,0 specify 65 + linear volume levels as shown below. + + Bit# Use + ---- -------------------------- + 15-07 Not used + 06 Forces volume to max (64 ones, no zeros) + 05-00 Sets one of 64 levels (000000=no output + (111111=63 1s, one 0) + + ++ + diff --git a/sources/official/saga-registers/beamcon0.htm b/sources/official/saga-registers/beamcon0.htm new file mode 100755 index 0000000..41030d1 --- /dev/null +++ b/sources/official/saga-registers/beamcon0.htm @@ -0,0 +1,13 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BEAMCON0 1DC W A( E ) Beam counter control register (SHRES,PAL) + ++ + diff --git a/sources/official/saga-registers/bltafwm.htm b/sources/official/saga-registers/bltafwm.htm new file mode 100755 index 0000000..abee88c --- /dev/null +++ b/sources/official/saga-registers/bltafwm.htm @@ -0,0 +1,20 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BLTAFWM 044 W A Blitter first-word mask for source A +BLTALWM 046 W A Blitter last-word mask for source A + + The patterns in these two registers are ANDed with + the first and last words of each line of data from + source A into the blitter. A zero in any bit + overrides data from source A. These registers + should be set to all 1s for fill mode or for + line-drawing mode. ++ + diff --git a/sources/official/saga-registers/bltcon0.htm b/sources/official/saga-registers/bltcon0.htm new file mode 100755 index 0000000..7f5ad58 --- /dev/null +++ b/sources/official/saga-registers/bltcon0.htm @@ -0,0 +1,114 @@ + + +
+
+ Agnus/
+ Read/ Denise/
+Register Address Write Paula Function
+-------- ------- ----- ------- --------
+BLTCON0 040 W A Blitter control register 0
+BLTCON1 042 W A( E ) Blitter control register 1
+
+ These two control registers are used together to
+ control blitter operations. There are two basic
+ modes, area and line, which are selected by bit
+ 0 of BLTCON1, as shown below.
+
+ AREA MODE ("normal")
+ -------------------------
+ BIT# BLTCON0 BLTCON1
+ ---- ------- -------
+ 15 ASH3 BSH3
+ 14 ASH2 BSH2
+ 13 ASH1 BSH1
+ 12 ASA0 BSH0
+ 11 USEA X
+ 10 USEB X
+ 09 USEC X
+ 08 USED X
+ 07 LF7 DOFF
+ 06 LF6 X
+ 05 LF5 X
+ 04 LF4 EFE
+ 03 LF3 IFE
+ 02 LF2 FCI
+ 01 LF1 DESC
+ 00 LF0 LINE(=0)
+
+ ASH3-0 Shift value of A source
+ BSH3-0 Shift value of B source
+ USEA Mode control bit to use source A
+ USEB Mode control bit to use source B
+ USEC Mode control bit to use source C
+ USED Mode control bit to use destination D
+ LF7-0 Logic function minterm select lines
+ EFE Exclusive fill enable
+ IFE Inclusive fill enable
+ FCI Fill carry input
+ DESC Descending (decreasing address) control bit
+ LINE Line mode control bit (set to 0)
+
+ LINE DRAW LINE MODE (line draw)
+ LINE DRAW ------------------------------
+ LINE DRAW BIT# BLTCON0 BLTCON1
+ LINE DRAW ---- ------- -------
+ LINE DRAW 15 START3 TEXTURE3
+ LINE DRAW 14 START2 TEXTURE2
+ LINE DRAW 13 START1 TEXTURE1
+ LINE DRAW 12 START0 TEXTURE0
+ LINE DRAW 11 1 0
+ LINE DRAW 10 0 0
+ LINE DRAW 09 1 0
+ LINE DRAW 08 1 0
+ LINE DRAW 07 LF7 0
+ LINE DRAW 06 LF6 SIGN
+ LINE DRAW 05 LF5 0 (Reserved)
+ LINE DRAW 04 LF4 SUD
+ LINE DRAW 03 LF3 SUL
+ LINE DRAW 02 LF2 AUL
+ LINE DRAW 01 LF1 SING
+ LINE DRAW 00 LF0 LINE(=1)
+ LINE DRAW
+ LINE DRAW START3-0 Starting point of line
+ LINE DRAW (0 thru 15 hex)
+
+ LINE DRAW LF7-0 Logic function minterm
+ LINE DRAW select lines should be preloaded
+ LINE DRAW with 4A to select the equation
+ LINE DRAW D=(AC+ABC). Since A contains a
+ LINE DRAW single bit true (8000), most bits
+ LINE DRAW will pass the C field unchanged
+ LINE DRAW (not A and C), but one bit will
+ LINE DRAW invert the C field and combine it
+ LINE DRAW with texture (A and B and not C).
+ LINE DRAW The A bit is automatically moved
+ LINE DRAW across the word by the hardware.
+ LINE DRAW
+ LINE DRAW LINE Line mode control bit (set to 1)
+ LINE DRAW SIGN Sign flag
+ LINE DRAW 0 Reserved for new mode
+ LINE DRAW SING Single bit per horizontal line for
+ LINE DRAW use with subsequent area fill
+ LINE DRAW SUD Sometimes up or down (=AUD*)
+ LINE DRAW SUL Sometimes up or left
+ LINE DRAW AUL Always up or left
+
+ LINE DRAW The 3 bits above select the octant
+ LINE DRAW for line drawing:
+
+ LINE DRAW OCT SUD SUL AUL
+ LINE DRAW --- --- --- ---
+ LINE DRAW 0 1 1 0
+ LINE DRAW 1 0 0 1
+ LINE DRAW 2 0 1 1
+ LINE DRAW 3 1 1 1
+ LINE DRAW 4 1 0 1
+ LINE DRAW 5 0 1 0
+ LINE DRAW 6 0 0 0
+ LINE DRAW 7 1 0 0
+
+ LINE DRAW The "B" source is used for
+ LINE DRAW texturing the drawn lines.
+
+
+
diff --git a/sources/official/saga-registers/bltddat.htm b/sources/official/saga-registers/bltddat.htm
new file mode 100755
index 0000000..672acbe
--- /dev/null
+++ b/sources/official/saga-registers/bltddat.htm
@@ -0,0 +1,18 @@
+
+
++ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BLTDDAT --- - ---- Blitter destination data register + + This register holds the data resulting from each + word of blitter operation until it is sent to a + RAM destination. This is a dummy address and + cannot be read by the micro. The transfer is + automatic during blitter operation. ++ + diff --git a/sources/official/saga-registers/bltsize.htm b/sources/official/saga-registers/bltsize.htm new file mode 100755 index 0000000..27d65e2 --- /dev/null +++ b/sources/official/saga-registers/bltsize.htm @@ -0,0 +1,39 @@ + + +
+ + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BLTSIZE 058 W A Blitter start and size (window width, + height) + + This register contains the width and height of + the blitter operation (in line mode, width must + = 2, height = line length). Writing to this + register will start the blitter, and should be + done last, after all pointers and control + registers have been initialized. + + BIT# 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00 + ----------------------------------------------- + h9 h8 h7 h6 h5 h4 h3 h2 h1 h0,w5 w4 w3 w2 w1 w0 + + h=height=vertical lines (10 bits=1024 lines max) + w=width =horizontal pixels (6 bits=64 + words=1024 pixels max) + + LINE DRAW BLTSIZE controls the line length and starts + LINE DRAW the line draw when written to. The h field + LINE DRAW controls the line length (10 bits gives + LINE DRAW lines up to 1024 dots long). The w field + LINE DRAW must be set to 02 for all line drawing. + +BLTSIZV 05C W A( E ) Blitter V size (for 15 bit vertical size) +BLTSIZH 05E W A( E ) Blitter H size and start (for 11 bit + H size) ++ + diff --git a/sources/official/saga-registers/bltsizh.htm b/sources/official/saga-registers/bltsizh.htm new file mode 100755 index 0000000..560395a --- /dev/null +++ b/sources/official/saga-registers/bltsizh.htm @@ -0,0 +1,40 @@ + + +
+ + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BLTSIZE 058 W A Blitter start and size (window width, + height) + + This register contains the width and height of + the blitter operation (in line mode, width must + = 2, height = line length). Writing to this + register will start the blitter, and should be + done last, after all pointers and control + registers have been initialized. + + BIT# 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00 + ----------------------------------------------- + h9 h8 h7 h6 h5 h4 h3 h2 h1 h0,w5 w4 w3 w2 w1 w0 + + h=height=vertical lines (10 bits=1024 lines max) + w=width =horizontal pixels (6 bits=64 + words=1024 pixels max) + + LINE DRAW BLTSIZE controls the line length and starts + LINE DRAW the line draw when written to. The h field + LINE DRAW controls the line length (10 bits gives + LINE DRAW lines up to 1024 dots long). The w field + LINE DRAW must be set to 02 for all line drawing. + +BLTSIZV 05C W A( E ) Blitter V size (for 15 bit vertical size) +BLTSIZH 05E W A( E ) Blitter H size and start (for 11 bit + H size) + ++ + diff --git a/sources/official/saga-registers/bltsizv.htm b/sources/official/saga-registers/bltsizv.htm new file mode 100755 index 0000000..560395a --- /dev/null +++ b/sources/official/saga-registers/bltsizv.htm @@ -0,0 +1,40 @@ + + +
+ + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BLTSIZE 058 W A Blitter start and size (window width, + height) + + This register contains the width and height of + the blitter operation (in line mode, width must + = 2, height = line length). Writing to this + register will start the blitter, and should be + done last, after all pointers and control + registers have been initialized. + + BIT# 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00 + ----------------------------------------------- + h9 h8 h7 h6 h5 h4 h3 h2 h1 h0,w5 w4 w3 w2 w1 w0 + + h=height=vertical lines (10 bits=1024 lines max) + w=width =horizontal pixels (6 bits=64 + words=1024 pixels max) + + LINE DRAW BLTSIZE controls the line length and starts + LINE DRAW the line draw when written to. The h field + LINE DRAW controls the line length (10 bits gives + LINE DRAW lines up to 1024 dots long). The w field + LINE DRAW must be set to 02 for all line drawing. + +BLTSIZV 05C W A( E ) Blitter V size (for 15 bit vertical size) +BLTSIZH 05E W A( E ) Blitter H size and start (for 11 bit + H size) + ++ + diff --git a/sources/official/saga-registers/bltxdat.htm b/sources/official/saga-registers/bltxdat.htm new file mode 100755 index 0000000..06d8297 --- /dev/null +++ b/sources/official/saga-registers/bltxdat.htm @@ -0,0 +1,22 @@ + + +
+ Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BLTxDAT 074 W A Blitter source x data register + + This register holds source x (x=A,B,C) data for + use by the blitter. It is normally loaded by the + blitter DMA channel; however, it may also be + preloaded by the microprocessor. + + LINE DRAW BLTADAT is used as an index register + LINE DRAW and must be preloaded with 8000. + LINE DRAW BLTBDAT is used for texture; it must + LINE DRAW be preloaded with FF if no texture + LINE DRAW (solid line) is desired. ++ + diff --git a/sources/official/saga-registers/bltxmod.htm b/sources/official/saga-registers/bltxmod.htm new file mode 100755 index 0000000..5482f02 --- /dev/null +++ b/sources/official/saga-registers/bltxmod.htm @@ -0,0 +1,34 @@ + + +
+ + + + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BLTxMOD 064 W A Blitter modulo x + + This register contains the modulo for blitter + source (x=A,B,C) or destination (x=D). A modulo + is a number that is automatically added to the + address at the end of each line, to make the + address point to the start of the next line. Each + source or destination has its own modulo, allowing + each to be a different size, while an identical + area of each is used in the blitter operation. + + LINE DRAW BLTAMOD and BLTBMOD are used as slope + LINE DRAW storage registers and must be preloaded + LINE DRAW with the values (4Y-4X) and (4Y) + LINE DRAW respectively. Y/X= line slope. + LINE DRAW BLTCMOD and BLTDMOD must both be + LINE DRAW preloaded with the width (in bytes) + LINE DRAW of the image into which the line is + LINE DRAW being drawn (normally two times the + LINE DRAW screen width in words). ++ + diff --git a/sources/official/saga-registers/bltxpth.htm b/sources/official/saga-registers/bltxpth.htm new file mode 100755 index 0000000..d12ed2f --- /dev/null +++ b/sources/official/saga-registers/bltxpth.htm @@ -0,0 +1,30 @@ + + +
+ Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BLTxPTH 050 W A( E ) Blitter pointer to x (high 3 bits, + 5 bits if ECS) +BLTxPTL 052 W A Blitter pointer to x (low 15 bits) + + This pair of registers contains the 18-bit address + of blitter source (x=A,B,C) or destination (x=D) + DMA data. This pointer must be preloaded with the + starting address of the data to be processed by + the blitter. After the blitter is finished, it + will contain the last data address (plus increment + and modulo). + + LINE DRAW BLTAPTL is used as an accumulator + LINE DRAW register and must be preloaded with + LINE DRAW the starting value of (2Y-X) where + LINE DRAW Y/X is the line slope. BLTCPT and + LINE DRAW BLTDPT (both H and L) must be + LINE DRAW preloaded with the starting address + LINE DRAW of the line. + ++ + diff --git a/sources/official/saga-registers/bplcon0.htm b/sources/official/saga-registers/bplcon0.htm new file mode 100755 index 0000000..4356560 --- /dev/null +++ b/sources/official/saga-registers/bplcon0.htm @@ -0,0 +1,65 @@ + + +
+ Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BPLCON0 100 W A D( E ) Bitplane control register (misc. + control bits) +BPLCON1 102 W D Bitplane control register + (horizontal scroll control) +BPLCON2 104 W D( E ) Bitplane control register + (video priority control) + + These registers control the operation of the + bitplanes and various aspects of the display. + + BIT# BPLCON0 BPLCON1 BPLCON2 + ---- -------- -------- -------- + 15 HIRES X X + 14 BPU2 X X + 13 BPU1 X X + 12 BPU0 X X + 11 HOMOD X X + 10 DBLPF X X + 09 COLOR X X + 08 GAUD X X + 07 X PF2H3 X + 06 X PF2H2 PF2PRI + 05 X PF2H1 PF2P2 + 04 X PF2H0 PF2P1 + 03 LPEN PF1H3 PF2P0 + 02 LACE PF1H2 PF1P2 + 01 ERSY PF1H1 PF1P1 + 00 X PF1H0 PF1P0 + + HIRES=High-resolution (70 ns pixels) + BPU =Bitplane use code 000-110 (NONE through 6 inclusive) + HOMOD=Hold-and-modify mode (1 = Hold-and-modify mode (HAM); + 0 = Extra Half Brite (EHB) if HAM=0 and BPU=6 + and DBLPF=0 then bitplane 6 controls an intensity + reduction in the other five bitplanes) + DBLPF=Double playfield (PF1=odd PF2=even bitplanes) + COLOR=Composite video COLOR enable + GAUD=Genlock audio enable (muxed on BKGND pin + during vertical blanking + LPEN =Light pen enable (reset on power up) + LACE =Interlace enable (reset on power up) + ERSY =External resync (HSYNC, VSYNC pads become + inputs) (reset on power up) + PF2PRI=Playfield 2 (even planes) has priority over + (appears in front of) playfield 1 + (odd planes). + PF2P=Playfield 2 priority code (with respect + to sprites) + PF1P=Playfield 1 priority code (with respect + to sprites) + PF2H=Playfield 2 horizontal scroll code + PF1H=Playfield 1 horizontal scroll code + +BPLCON3 106 W D( E ) Bitplane control (enhanced features) + ++ + \ No newline at end of file diff --git a/sources/official/saga-registers/bplcon1.htm b/sources/official/saga-registers/bplcon1.htm new file mode 100755 index 0000000..4356560 --- /dev/null +++ b/sources/official/saga-registers/bplcon1.htm @@ -0,0 +1,65 @@ + + +
+ Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BPLCON0 100 W A D( E ) Bitplane control register (misc. + control bits) +BPLCON1 102 W D Bitplane control register + (horizontal scroll control) +BPLCON2 104 W D( E ) Bitplane control register + (video priority control) + + These registers control the operation of the + bitplanes and various aspects of the display. + + BIT# BPLCON0 BPLCON1 BPLCON2 + ---- -------- -------- -------- + 15 HIRES X X + 14 BPU2 X X + 13 BPU1 X X + 12 BPU0 X X + 11 HOMOD X X + 10 DBLPF X X + 09 COLOR X X + 08 GAUD X X + 07 X PF2H3 X + 06 X PF2H2 PF2PRI + 05 X PF2H1 PF2P2 + 04 X PF2H0 PF2P1 + 03 LPEN PF1H3 PF2P0 + 02 LACE PF1H2 PF1P2 + 01 ERSY PF1H1 PF1P1 + 00 X PF1H0 PF1P0 + + HIRES=High-resolution (70 ns pixels) + BPU =Bitplane use code 000-110 (NONE through 6 inclusive) + HOMOD=Hold-and-modify mode (1 = Hold-and-modify mode (HAM); + 0 = Extra Half Brite (EHB) if HAM=0 and BPU=6 + and DBLPF=0 then bitplane 6 controls an intensity + reduction in the other five bitplanes) + DBLPF=Double playfield (PF1=odd PF2=even bitplanes) + COLOR=Composite video COLOR enable + GAUD=Genlock audio enable (muxed on BKGND pin + during vertical blanking + LPEN =Light pen enable (reset on power up) + LACE =Interlace enable (reset on power up) + ERSY =External resync (HSYNC, VSYNC pads become + inputs) (reset on power up) + PF2PRI=Playfield 2 (even planes) has priority over + (appears in front of) playfield 1 + (odd planes). + PF2P=Playfield 2 priority code (with respect + to sprites) + PF1P=Playfield 1 priority code (with respect + to sprites) + PF2H=Playfield 2 horizontal scroll code + PF1H=Playfield 1 horizontal scroll code + +BPLCON3 106 W D( E ) Bitplane control (enhanced features) + ++ + \ No newline at end of file diff --git a/sources/official/saga-registers/bplcon2.htm b/sources/official/saga-registers/bplcon2.htm new file mode 100755 index 0000000..4356560 --- /dev/null +++ b/sources/official/saga-registers/bplcon2.htm @@ -0,0 +1,65 @@ + + +
+ Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BPLCON0 100 W A D( E ) Bitplane control register (misc. + control bits) +BPLCON1 102 W D Bitplane control register + (horizontal scroll control) +BPLCON2 104 W D( E ) Bitplane control register + (video priority control) + + These registers control the operation of the + bitplanes and various aspects of the display. + + BIT# BPLCON0 BPLCON1 BPLCON2 + ---- -------- -------- -------- + 15 HIRES X X + 14 BPU2 X X + 13 BPU1 X X + 12 BPU0 X X + 11 HOMOD X X + 10 DBLPF X X + 09 COLOR X X + 08 GAUD X X + 07 X PF2H3 X + 06 X PF2H2 PF2PRI + 05 X PF2H1 PF2P2 + 04 X PF2H0 PF2P1 + 03 LPEN PF1H3 PF2P0 + 02 LACE PF1H2 PF1P2 + 01 ERSY PF1H1 PF1P1 + 00 X PF1H0 PF1P0 + + HIRES=High-resolution (70 ns pixels) + BPU =Bitplane use code 000-110 (NONE through 6 inclusive) + HOMOD=Hold-and-modify mode (1 = Hold-and-modify mode (HAM); + 0 = Extra Half Brite (EHB) if HAM=0 and BPU=6 + and DBLPF=0 then bitplane 6 controls an intensity + reduction in the other five bitplanes) + DBLPF=Double playfield (PF1=odd PF2=even bitplanes) + COLOR=Composite video COLOR enable + GAUD=Genlock audio enable (muxed on BKGND pin + during vertical blanking + LPEN =Light pen enable (reset on power up) + LACE =Interlace enable (reset on power up) + ERSY =External resync (HSYNC, VSYNC pads become + inputs) (reset on power up) + PF2PRI=Playfield 2 (even planes) has priority over + (appears in front of) playfield 1 + (odd planes). + PF2P=Playfield 2 priority code (with respect + to sprites) + PF1P=Playfield 1 priority code (with respect + to sprites) + PF2H=Playfield 2 horizontal scroll code + PF1H=Playfield 1 horizontal scroll code + +BPLCON3 106 W D( E ) Bitplane control (enhanced features) + ++ + \ No newline at end of file diff --git a/sources/official/saga-registers/bplcon3.htm b/sources/official/saga-registers/bplcon3.htm new file mode 100755 index 0000000..4356560 --- /dev/null +++ b/sources/official/saga-registers/bplcon3.htm @@ -0,0 +1,65 @@ + + +
+ Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BPLCON0 100 W A D( E ) Bitplane control register (misc. + control bits) +BPLCON1 102 W D Bitplane control register + (horizontal scroll control) +BPLCON2 104 W D( E ) Bitplane control register + (video priority control) + + These registers control the operation of the + bitplanes and various aspects of the display. + + BIT# BPLCON0 BPLCON1 BPLCON2 + ---- -------- -------- -------- + 15 HIRES X X + 14 BPU2 X X + 13 BPU1 X X + 12 BPU0 X X + 11 HOMOD X X + 10 DBLPF X X + 09 COLOR X X + 08 GAUD X X + 07 X PF2H3 X + 06 X PF2H2 PF2PRI + 05 X PF2H1 PF2P2 + 04 X PF2H0 PF2P1 + 03 LPEN PF1H3 PF2P0 + 02 LACE PF1H2 PF1P2 + 01 ERSY PF1H1 PF1P1 + 00 X PF1H0 PF1P0 + + HIRES=High-resolution (70 ns pixels) + BPU =Bitplane use code 000-110 (NONE through 6 inclusive) + HOMOD=Hold-and-modify mode (1 = Hold-and-modify mode (HAM); + 0 = Extra Half Brite (EHB) if HAM=0 and BPU=6 + and DBLPF=0 then bitplane 6 controls an intensity + reduction in the other five bitplanes) + DBLPF=Double playfield (PF1=odd PF2=even bitplanes) + COLOR=Composite video COLOR enable + GAUD=Genlock audio enable (muxed on BKGND pin + during vertical blanking + LPEN =Light pen enable (reset on power up) + LACE =Interlace enable (reset on power up) + ERSY =External resync (HSYNC, VSYNC pads become + inputs) (reset on power up) + PF2PRI=Playfield 2 (even planes) has priority over + (appears in front of) playfield 1 + (odd planes). + PF2P=Playfield 2 priority code (with respect + to sprites) + PF1P=Playfield 1 priority code (with respect + to sprites) + PF2H=Playfield 2 horizontal scroll code + PF1H=Playfield 1 horizontal scroll code + +BPLCON3 106 W D( E ) Bitplane control (enhanced features) + ++ + \ No newline at end of file diff --git a/sources/official/saga-registers/bplhmod.htm b/sources/official/saga-registers/bplhmod.htm new file mode 100755 index 0000000..5d981b1 --- /dev/null +++ b/sources/official/saga-registers/bplhmod.htm @@ -0,0 +1,13 @@ + + +
+ +BPLHMOD + + This is the number (sign extended) that is added to the UHRES bitplane + pointer (BPLHPTL,H) every line, just like the other modulos. + + ++ + diff --git a/sources/official/saga-registers/bplhpth.htm b/sources/official/saga-registers/bplhpth.htm new file mode 100755 index 0000000..248a4dd --- /dev/null +++ b/sources/official/saga-registers/bplhpth.htm @@ -0,0 +1,12 @@ + + +
+ +BPLHPTR + + 32bit pointer to Chunky plane. + The Chunky plane can show 8bit/16Bit/15bit/24bit/32bit screens. + ++ + diff --git a/sources/official/saga-registers/bplxdat.htm b/sources/official/saga-registers/bplxdat.htm new file mode 100755 index 0000000..4d9567a --- /dev/null +++ b/sources/official/saga-registers/bplxdat.htm @@ -0,0 +1,28 @@ + + +
+ + + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BPLxDAT 110 W D Bitplane x data (parallel-to-serial + convert) + + These registers receive the DMA data fetched from + RAM by the bitplane address pointers described + above. They may also be written by either + microprocessor. They act as a six-word parallel- + to-serial buffer for up to six memory bitplanes + (x=1-6). The parallel-to-serial conversion is + triggered whenever bitplane #1 is written, + indicating the completion of all bitplanes for + that word (16 pixels). The MSB is output first, + and is, therefore, always on the left. + + ++ + diff --git a/sources/official/saga-registers/bplxmod.htm b/sources/official/saga-registers/bplxmod.htm new file mode 100755 index 0000000..986d97d --- /dev/null +++ b/sources/official/saga-registers/bplxmod.htm @@ -0,0 +1,24 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BPL1MOD 108 W A Bitplane modulo (odd planes) +BPL2MOD 10A W A Bitplane modulo (even planes) + + These registers contain the modulos for the odd + and even bitplanes. A modulo is a number that is + automatically added to the address at the end of + each line, so that the address then points to the + start of the next line. + Since they have separate modulos, the odd and even + bitplanes may have sizes that are different from + each other, as well as different from the display + window size. + ++ + diff --git a/sources/official/saga-registers/bplxpth.htm b/sources/official/saga-registers/bplxpth.htm new file mode 100755 index 0000000..6bc54b1 --- /dev/null +++ b/sources/official/saga-registers/bplxpth.htm @@ -0,0 +1,20 @@ + + +
+ + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +BPLxPTH 0E0 W A Bitplane x pointer (high 3 bits) +BPLxPTL 0E2 W A Bitplane x pointer (low 15 bits) + + This pair of registers contains the 18-bit pointer to + the address of bitplane x (x=1,2,3,4,5,6) DMA data. + This pointer must be reinitialized by the processor + or copper to point to the beginning of bitplane data + every vertical blank time. ++ + diff --git a/sources/official/saga-registers/chunkycol.htm b/sources/official/saga-registers/chunkycol.htm new file mode 100755 index 0000000..231376c --- /dev/null +++ b/sources/official/saga-registers/chunkycol.htm @@ -0,0 +1,29 @@ + + +
+ +CHUNKY COLOR PORT + + This register allows direct setting of 256 Chunky colors registers + + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 31-24 | index | 8bit Colornumber | + | 23-16 | RED | 8bit Red | + | 15-08 | GREEN | 8bit Green | + | 07-00 | BLUE | 8bit Blue | + +-------+----------+-------------------------------------------+ + +Example: + + move.l #$00FF0000,$DFF388 -- set color0 = RED + move.l #$01FFFF00,$DFF388 -- set color1 = YELLOW + +Copper: + dc.w $8388,$00FF,$0000 -- set color0 = RED + ++ + diff --git a/sources/official/saga-registers/clxcon.htm b/sources/official/saga-registers/clxcon.htm new file mode 100755 index 0000000..00166e8 --- /dev/null +++ b/sources/official/saga-registers/clxcon.htm @@ -0,0 +1,51 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +CLXCON 098 W D Collision control + + This register controls which bitplanes are + included (enabled) in collision detection and + their required state if included. It also controls + the individual inclusion of odd-numbered sprites + in the collision detection by logically OR-ing + them with their corresponding even-numbered sprite. + + BIT# FUNCTION DESCRIPTION + ---- -------- ------------------------------ + 15 ENSP7 Enable sprite 7 (ORed with sprite 6) + 14 ENSP5 Enable sprite 5 (ORed with sprite 4) + 13 ENSP3 Enable sprite 3 (ORed with sprite 2) + 12 ENSP1 Enable sprite 1 (ORed with sprite 0) + 11 ENBP6 Enable bitplane 6 (match required + for collision) + 10 ENBP5 Enable bitplane 5 (match required + for collision) + 09 ENBP4 Enable bitplane 4 (match required + for collision) + 08 ENBP3 Enable bitplane 3 (match required + for collision) + 07 ENBP2 Enable bitplane 2 (match required + for collision) + 06 ENBP1 Enable bitplane 1 (match required + for collision) + 05 MVBP6 Match value for bitplane 6 collision + 04 MVBP5 Match value for bitplane 5 collision + 03 MVBP4 Match value for bitplane 4 collision + 02 MVBP3 Match value for bitplane 3 collision + 01 MVBP2 Match value for bitplane 2 collision + 00 MVBP1 Match value for bitplane 1 collision + + NOTE: Disabled bitplanes cannot prevent + collisions. Therefore if all bitplanes are + disabled, collisions will be continuous, + regardless of the match values. + + ++ + diff --git a/sources/official/saga-registers/clxdat.htm b/sources/official/saga-registers/clxdat.htm new file mode 100755 index 0000000..e8642e6 --- /dev/null +++ b/sources/official/saga-registers/clxdat.htm @@ -0,0 +1,39 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +CLXDAT 00E R D Collision data register (read and clear) + + This address reads (and clears) the collision + detection register. The bit assignments are below. + + NOTE: Playfield 1 is all odd-numbered enabled + bitplanes. Playfield 2 is all even-numbered + enabled bitplanes + + BIT# COLLISIONS REGISTERED + ----- -------------------------- + 15 not used + 14 Sprite 4 (or 5) to sprite 6 (or 7) + 13 Sprite 2 (or 3) to sprite 6 (or 7) + 12 Sprite 2 (or 3) to sprite 4 (or 5) + 11 Sprite 0 (or 1) to sprite 6 (or 7) + 10 Sprite 0 (or 1) to sprite 4 (or 5) + 09 Sprite 0 (or 1) to sprite 2 (or 3) + 08 Playfield 2 to sprite 6 (or 7) + 07 Playfield 2 to sprite 4 (or 5) + 06 Playfield 2 to sprite 2 (or 3) + 05 Playfield 2 to sprite 0 (or 1) + 04 Playfield 1 to sprite 6 (or 7) + 03 Playfield 1 to sprite 4 (or 5) + 02 Playfield 1 to sprite 2 (or 3) + 01 Playfield 1 to sprite 0 (or 1) + 00 Playfield 1 to playfield 2 + ++ + \ No newline at end of file diff --git a/sources/official/saga-registers/clxdatx.htm b/sources/official/saga-registers/clxdatx.htm new file mode 100755 index 0000000..d67a142 --- /dev/null +++ b/sources/official/saga-registers/clxdatx.htm @@ -0,0 +1,32 @@ + + +
+ +CLXDAT + + This register contains detailed Sprite collision detection + + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 15 | HIT15 | Sprite to SpriteF | + | 14 | HIT14 | Sprite to SpriteE | + | 13 | HIT13 | Sprite to SpriteD | + | 12 | HIT12 | Sprite to SpriteC | + | 11 | HIT11 | Sprite to SpriteB | + | 10 | HIT10 | Sprite to SpriteA | + | 09 | HIT9 | Sprite to Sprite9 | + | 08 | HIT8 | Sprite to Sprite8 | + | 07 | HIT7 | Sprite to Sprite7 | + | 06 | HIT6 | Sprite to Sprite6 | + | 05 | HIT5 | Sprite to Sprite5 | + | 04 | HIT4 | Sprite to Sprite4 | + | 03 | HIT3 | Sprite to Sprite3 | + | 02 | HIT2 | Sprite to Sprite2 | + | 01 | HIT1 | Sprite to Sprite1 | + | 00 | HIT0 | Sprite to Sprite0 | + +-------+----------+-------------------------------------------+ ++ + diff --git a/sources/official/saga-registers/colorx.htm b/sources/official/saga-registers/colorx.htm new file mode 100755 index 0000000..82155e5 --- /dev/null +++ b/sources/official/saga-registers/colorx.htm @@ -0,0 +1,28 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +COLORxx 180 W D Color table xx + + There are 32 of these registers (xx=00-31) and they + are sometimes collectively called the "color + palette." They contain 12-bit codes representing + red, green, and blue colors for RGB systems. + One of these registers at a time is selected + (by the BPLxDAT serialized video code) + for presentation at the RGB video output pins. + The table below shows the color register bit usage. + + BIT# 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00 + ----------- ----------- ----------- ----------- + RGB X X X X R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 + + B=blue, G=green, R=red, + ++ + diff --git a/sources/official/saga-registers/cop1lch.htm b/sources/official/saga-registers/cop1lch.htm new file mode 100755 index 0000000..32cd463 --- /dev/null +++ b/sources/official/saga-registers/cop1lch.htm @@ -0,0 +1,22 @@ + + +
+ Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +COP1LCH 080 W A( E ) Copper first location register + (high 3 bits, high 5 bits if ECS) +COP1LCL 082 W A Copper first location register + (low 15 bits) +COP2LCH 084 W A( E ) Copper second location register + (high 3 bits, high 5 bits if ECS) +COP2LCL 086 W A Copper second location register + (low 15 bits) + + These registers contain the jump addresses + described above. + ++ + diff --git a/sources/official/saga-registers/cop2lch.htm b/sources/official/saga-registers/cop2lch.htm new file mode 100755 index 0000000..8476265 --- /dev/null +++ b/sources/official/saga-registers/cop2lch.htm @@ -0,0 +1,24 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +COP1LCH 080 W A( E ) Copper first location register + (high 3 bits, high 5 bits if ECS) +COP1LCL 082 W A Copper first location register + (low 15 bits) +COP2LCH 084 W A( E ) Copper second location register + (high 3 bits, high 5 bits if ECS) +COP2LCL 086 W A Copper second location register + (low 15 bits) + + These registers contain the jump addresses + described above. + + ++ + diff --git a/sources/official/saga-registers/copcon.htm b/sources/official/saga-registers/copcon.htm new file mode 100755 index 0000000..86b9a17 --- /dev/null +++ b/sources/official/saga-registers/copcon.htm @@ -0,0 +1,22 @@ + + +
+ Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +COPCON 02E W A( E ) Copper control register + + This is a 1-bit register that when set true, allows + the Copper to access the blitter hardware. This + bit is cleared by power-on reset, so that the Copper + cannot access the blitter hardware. See Appendix C + for ECS operation. + + BIT# NAME FUNCTION + ---- ------- ------------------ + 01 CDANG Copper danger mode. Allows Copper + access to blitter if true. ++ + diff --git a/sources/official/saga-registers/copins.htm b/sources/official/saga-registers/copins.htm new file mode 100755 index 0000000..49bcba4 --- /dev/null +++ b/sources/official/saga-registers/copins.htm @@ -0,0 +1,100 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +COPINS 08C W A Copper instruction fetch identify + + This is a dummy address that is generated by the + Copper whenever it is loading instructions into + its own instruction register. This actually occurs + every Copper cycle except for the second (IR2) + cycle of the MOVE instruction. The three types + of instructions are shown below. + + MOVE Move immediate to destination. + WAIT Wait until beam counter is equal to, or + greater than. (keeps Copper off of bus + until beam position has been reached). + SKIP Skip if beam counter is equal to or greater + than (skips following MOVE instruction unless + beam position has been reached). + + MOVE WAIT UNTIL SKIP IF + -------- ----------- ------------ + BIT# IR1 IR2 IR1 IR2 IR1 IR2 + ---- ---- ---- ---- ---- ---- ---- + 15 X RD15 VP7 BFD * VP7 BFD * + 14 X RD14 VP6 VE6 VP6 VE6 + 13 X RD13 VP5 VE5 VP5 VE5 + 12 X RD12 VP4 VE4 VP4 VE4 + 11 X RD11 VP3 VE3 VP3 VE3 + 10 X RD10 VP2 VE2 VP2 VE2 + 09 X RD09 VP1 VE1 VP1 VE1 + 08 DA8 RD08 VP0 VE0 VP0 VE0 + 07 DA7 RD07 HP8 HE8 HP8 HE8 + 06 DA6 RD06 HP7 HE7 HP7 HE7 + 05 DA5 RD05 HP6 HE6 HP6 HE6 + 04 DA4 RD04 HP5 HE5 HP5 HE5 + 03 DA3 RD03 HP4 HE4 HP4 HE4 + 02 DA2 RD02 HP3 HE3 HP3 HE3 + 01 DA1 RD01 HP2 HE2 HP2 HE2 + 00 0 RD00 1 0 1 1 + + IR1=First instruction register + IR2=Second instruction register + DA =Destination address for MOVE instruction. Fetched + during IR1 time, used during IR2 time on RGA bus. + RD =RAM data moved by MOVE instruction at IR2 time + directly from RAM to the address given by the + DA field. + VP =Vertical beam position comparison bit. + HP =Horizontal beam position comparison bit. + VE =Enable comparison (mask bit). + HE =Enable comparison (mask bit). + + * NOTE BFD=Blitter finished disable. When this bit + is true, the Blitter Finished flag will + have no effect on the Copper. When this + bit is zero, the Blitter Finished flag + must be true (in addition to the rest of + the bit comparisons) before the Copper + can exit from its wait state or skip + over an instruction. Note that the V7 + comparison cannot be masked. + + The Copper is basically a two-cycle machine that + requests the bus only during odd memory cycles + (4 memory cycles per instruction). This prevents + collisions with display, audio, disk, refresh, and + sprites, all of which use only even cycles. It + therefore needs (and has) priority over only the + blitter and microprocessor. + + There are only three types of instructions: + MOVE immediate, WAIT until, and SKIP if. All + instructions (except for WAIT) require two bus + cycles (and two instruction words). Since only + the odd bus cycles are requested, four memory + cycle times are required per instruction + (memory cycles are 280 ns.) + + There are two indirect jump registers, COP1LC and + COP2LC . These are 18-bit pointer registers whose + contents are used to modify the program counter for + initialization or jumps. They are transferred to + the program counter whenever strobe addresses + COPJMP1 or COPJMP2 are written. In addition, + COP1LC is automatically used at the beginning of + each vertical blank time. + + It is important that one of the jump registers be + initialized and its jump strobe address hit after + power-up but before Copper DMA is initialized. + This insures a determined startup address and state. ++ + \ No newline at end of file diff --git a/sources/official/saga-registers/copjmp.htm b/sources/official/saga-registers/copjmp.htm new file mode 100755 index 0000000..3fae975 --- /dev/null +++ b/sources/official/saga-registers/copjmp.htm @@ -0,0 +1,21 @@ + + +
+ Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +COPJMP1 088 S A Copper restart at first location +COPJMP2 08A S A Copper restart at second location + + These addresses are strobe addresses. When written + to, they cause the Copper to jump indirect using + the address contained in the first or second + location registers described below. The Copper + itself can write to these addresses, causing its + own jump indirect. ++ + + + diff --git a/sources/official/saga-registers/ddfstrt.htm b/sources/official/saga-registers/ddfstrt.htm new file mode 100755 index 0000000..707c22a --- /dev/null +++ b/sources/official/saga-registers/ddfstrt.htm @@ -0,0 +1,48 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +DDFSTOP 094 W A Display data fetch stop (horiz. position) +DDFSTRT 092 W A Display data fetch start (horiz. position) + + These registers control the horizontal timing of the + beginning and end of the bitplane DMA display data + fetch. The vertical bitplane DMA timing is identical + to the display windows described above. + The bitplane modulos are dependent on the bitplane + horizontal size and on this data-fetch window size. + + Register bit assignment + ------------------------- + BIT# 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00 + ----------------------------------------------- + USE X X X X X X X X H8 H7 H6 H5 H4 H3 X X + + (Always set X bits to 0 to maintain upward compatibility) + + The tables below show the start and stop timing for + different register contents. + + DDFSTRT (left edge of display data fetch) + ---------------------------------------- + PURPOSE H8,H7,H6,H5,H4 + ----------------- -------------- + Extra wide (max) * 0 0 1 0 1 + Wide 0 0 1 1 0 + Normal 0 0 1 1 1 + Narrow 0 1 0 0 0 + + DDFSTOP (right edge of display data fetch) + ------------------------------------------ + PURPOSE H8,H7,H6,H5,H4 + ------------------ -------------- + Narrow 1 1 0 0 1 + Normal 1 1 0 1 0 + Wide (max) 1 1 0 1 1 ++ + diff --git a/sources/official/saga-registers/deniseid.htm b/sources/official/saga-registers/deniseid.htm new file mode 100755 index 0000000..2c3f3fc --- /dev/null +++ b/sources/official/saga-registers/deniseid.htm @@ -0,0 +1,14 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +DENISEID 07C R D( E ) Chip revision level for Denise + (video out chip) + ++ + diff --git a/sources/official/saga-registers/diwhigh.htm b/sources/official/saga-registers/diwhigh.htm new file mode 100755 index 0000000..9a3a39d --- /dev/null +++ b/sources/official/saga-registers/diwhigh.htm @@ -0,0 +1,36 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +DIWHIGH 1E4 W A,D( E ) Display window - upper bits for + start, stop + +DIWSTOP 090 W A Display window stop (lower right + vertical-horizontal position) +DIWSTRT 08E W A Display window start (upper left + vertical-horizontal position) + + These registers control display window size and position + by locating the upper left and lower right corners. + + BIT# 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00 + ----------------------------------------------- + USE V7 V6 V5 V4 V3 V2 V1 V0 H7 H6 H5 H4 H3 H2 H1 H0 + + DIWSTRT is vertically restricted to the upper 2/3 + of the display (V8=0) and horizontally restricted to + the left 3/4 of the display (H8=0). + + DIWSTOP is vertically restricted to the lower 1/2 + of the display (V8=/=V7) and horizontally restricted + to the right 1/4 of the display (H8=1). + + + ++ + diff --git a/sources/official/saga-registers/diwstrt.htm b/sources/official/saga-registers/diwstrt.htm new file mode 100755 index 0000000..5a7cfbe --- /dev/null +++ b/sources/official/saga-registers/diwstrt.htm @@ -0,0 +1,34 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +DIWHIGH 1E4 W A,D( E ) Display window - upper bits for + start, stop + +DIWSTOP 090 W A Display window stop (lower right + vertical-horizontal position) +DIWSTRT 08E W A Display window start (upper left + vertical-horizontal position) + + These registers control display window size and position + by locating the upper left and lower right corners. + + BIT# 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00 + ----------------------------------------------- + USE V7 V6 V5 V4 V3 V2 V1 V0 H7 H6 H5 H4 H3 H2 H1 H0 + + DIWSTRT is vertically restricted to the upper 2/3 + of the display (V8=0) and horizontally restricted to + the left 3/4 of the display (H8=0). + + DIWSTOP is vertically restricted to the lower 1/2 + of the display (V8=/=V7) and horizontally restricted + to the right 1/4 of the display (H8=1). + ++ + diff --git a/sources/official/saga-registers/dmacon2.htm b/sources/official/saga-registers/dmacon2.htm new file mode 100755 index 0000000..72daf32 --- /dev/null +++ b/sources/official/saga-registers/dmacon2.htm @@ -0,0 +1,32 @@ + + +
+ +DMACON2 + + DMA Channel control 2 - For Audio channels and Ethernet + + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 15 | | SET/CLR | + | 14 | | | + | 13 | ETH | Ethernet | + | 12 | | | + | 11 | AUD15 | Audio channel 15 | + | 10 | AUD14 | Audio channel 14 | + | 09 | AUD13 | Audio channel 13 | + | 08 | AUD12 | Audio channel 12 | + | 07 | AUD11 | Audio channel 11 | + | 06 | AUD10 | Audio channel 10 | + | 05 | AUD9 | Audio channel 9 | + | 04 | AUD8 | Audio channel 8 | + | 03 | AUD7 | Audio channel 7 | + | 02 | AUD6 | Audio channel 6 | + | 01 | AUD5 | Audio channel 5 | + | 00 | AUD4 | Audio channel 4 | + +-------+----------+-------------------------------------------+ ++ + diff --git a/sources/official/saga-registers/dmaconr.htm b/sources/official/saga-registers/dmaconr.htm new file mode 100755 index 0000000..68fff4c --- /dev/null +++ b/sources/official/saga-registers/dmaconr.htm @@ -0,0 +1,45 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +DMACON 096 W A D P DMA control write (clear or set) +DMACONR 002 R A P DMA control (and blitter status) read + + This register controls all of the DMA channels and + contains blitter DMA status bits. + + BIT# FUNCTION DESCRIPTION + ---- --------- ----------------------------------- + 15 SET/CLR Set/clear control bit. Determines + if bits written with a 1 get set or + cleared. Bits written with a zero + are unchanged. + 14 BBUSY Blitter busy status bit (read only) + 13 BZERO Blitter logic zero status bit + (read only). + 12 X + 11 X + 10 BLTPRI Blitter DMA priority + (over CPU micro) (also called + "blitter nasty") (disables /BLS + pin, preventing micro from + stealing any bus cycles while + blitter DMA is running). + 09 DMAEN Enable all DMA below + 08 BPLEN Bitplane DMA enable + 07 COPEN Copper DMA enable + 06 BLTEN Blitter DMA enable + 05 SPREN Sprite DMA enable + 04 DSKEN Disk DMA enable + 03 AUD3EN Audio channel 3 DMA enable + 02 AUD2EN Audio channel 2 DMA enable + 01 AUD1EN Audio channel 1 DMA enable + 00 AUD0EN Audio channel 0 DMA enable + ++ + diff --git a/sources/official/saga-registers/dskbytr.htm b/sources/official/saga-registers/dskbytr.htm new file mode 100755 index 0000000..b6e3578 --- /dev/null +++ b/sources/official/saga-registers/dskbytr.htm @@ -0,0 +1,30 @@ + + +
+ + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +DSKBYTR 01A R P Disk data byte and status read + + This register is the disk-microprocessor data + buffer. Data from the disk (in read mode) is + loaded into this register one byte at a time, and + bit 15 (DSKBYT) is set true. + + BIT# + ---- --------- -------------------------------- + 15 DSKBYT Disk byte ready (reset on read) + 14 DMAON Mirror of bit 15 (DMAEN) in DSKLEN , + ANDed with Bit09 (DMAEN) in DMACON + 13 DISKWRITE Mirror of bit 14 (WRITE) in DSKLEN + 12 WORDEQUAL This bit true only while the + DSKSYNC register equals the data + from disk. + 11-08 X Not used + 07-00 DATA Disk byte data ++ + \ No newline at end of file diff --git a/sources/official/saga-registers/dskdatr.htm b/sources/official/saga-registers/dskdatr.htm new file mode 100755 index 0000000..b42e96c --- /dev/null +++ b/sources/official/saga-registers/dskdatr.htm @@ -0,0 +1,24 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +DSKDAT 026 W P Disk DMA data write +DSKDATR 008 ER P Disk DMA data read (early read dummy + address) + + This register is the disk DMA data buffer. It + contains two bytes of data that are either sent + (written) to or received (read) from the disk. + The write mode is enabled by bit 14 of the LENGTH + register. The DMA controller automatically + transfers data to or from this register and RAM, + and when the DMA data is finished (length=0) it + causes a disk block interrupt. See interrupts below. + ++ + diff --git a/sources/official/saga-registers/dsklen.htm b/sources/official/saga-registers/dsklen.htm new file mode 100755 index 0000000..b740dbc --- /dev/null +++ b/sources/official/saga-registers/dsklen.htm @@ -0,0 +1,24 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +DSKLEN 024 W P Disk length + + This register contains the length (number of words) + of disk DMA data. It also contains two control + bits, a DMA enable bit, and a DMA direction + (read/write) bit. + + BIT# FUNCTION DESCRIPTION + ---- ----------- -------------------------------- + 15 DMAEN Disk DMA enable + 14 WRITE Disk write (RAM to disk) if 1 + 13-0 LENGTH Length (# of words) of DMA data. ++ + + diff --git a/sources/official/saga-registers/dskpth.htm b/sources/official/saga-registers/dskpth.htm new file mode 100755 index 0000000..7e2ea37 --- /dev/null +++ b/sources/official/saga-registers/dskpth.htm @@ -0,0 +1,18 @@ + + +
+ Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +DSKPTH 020 W A( E ) Disk pointer (high 3 bits, + high 5 bits if ECS) +DSKPTL 022 W A Disk pointer (low 15 bits) + + This pair of registers contains the 18-bit + address of disk DMA data. These address registers + must be initialized by the processor or Copper + before disk DMA is enabled. ++ + diff --git a/sources/official/saga-registers/dsksync.htm b/sources/official/saga-registers/dsksync.htm new file mode 100755 index 0000000..81ea9a8 --- /dev/null +++ b/sources/official/saga-registers/dsksync.htm @@ -0,0 +1,15 @@ + + +
+ Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +DSKSYNC 07E W P Disk sync register + + holds the match code for disk read synchronization. + See ADKCON bit 10. + ++ + diff --git a/sources/official/saga-registers/fmode.htm b/sources/official/saga-registers/fmode.htm new file mode 100755 index 0000000..5bcb6b1 --- /dev/null +++ b/sources/official/saga-registers/fmode.htm @@ -0,0 +1,27 @@ + + +
+ +FMODE + + This register controls the fetch mechanism for different + types of Chip RAM accesses: + + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 15 | SSCAN2 | Global enable for sprite scan-doubling. | + | 14 | BSCAN2 | Enables the use of 2nd P/F modulus on an | + | | | alternate line basis to support bitplane | + | | | scan-doubling. | + | 13-05 | Unused | | + | 04 | SAGA | Enable SAGA New features | + | 03 | SPAGEM | Sprite page mode (double CAS) | + | 02 | SPR32 | Sprite 32 bit wide mode | + | 01 | BPAGEM | Bitplane Page Mode (double CAS) | + | 00 | BLP32 | Bitplane 32 bit wide mode | + +-------+----------+-------------------------------------------+ ++ + diff --git a/sources/official/saga-registers/gfxmode.htm b/sources/official/saga-registers/gfxmode.htm new file mode 100755 index 0000000..f4272a0 --- /dev/null +++ b/sources/official/saga-registers/gfxmode.htm @@ -0,0 +1,54 @@ + + +
+ +GFXMODE + 16bit register selecting the screen size and the pixelformat for the Chunky plane. + + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-----------------------------------------+ + | 15.08 | Resolution | $00 | + | | $01 = 320x200 60Hz 28Mhz x2 x2 | + | | $02 = 320x240 60Hz 28Mhz x2 x2 | + | | $03 = 320x256 60Hz 28Mhz x2 x2 | + | | $04 = 640x400 60Hz 28Mhz | + | | $05 = 640x480 60Hz 28MHz | + | | $06 = 640x512 50Hz 28MHz | + | | $07 = 960x540 60Hz 42Mhz | + | | $08 = 480x270 60Hz 42Mhz x2 x2 | + | | $09 = 304x224 60Hz 28Mhz x2 x2 | + | | $0A = 1280x720 50Hz 85Mhz | + | | $0B = 640x360 50Hz 85Mhz x2 x2 | + | | $0C = 800x600 60Hz 42MHz | + | | $0D = 1024x768 60Hz 85MHz | + | | $0E = 720x576 50Hz 28Mhz | + | | $0F = 848x480 60Hz 42MHz | + | | $10 = 640x200 60Hz 28Mhz | + | | $11 = 1920x1080 24Hz 85Mhz | + | | $12 = 1280x1024 50Hz 85Mhz | + | | $13 = 1280x800 60Hz 84Mhz | + | | $14 = 1440x900 50Hz 85Mhz | + | | $15 = 720x405 50Hz 28Mhz | + +-------+----------+-----------------------------------------+ + | 07.00 | Pixelformat | $00 | + | | $01 = 8bit CHUNKY (indexed) | + | | $02 = 16bit R5G6B5 | + | | $03 = 15bit 1R5G5B5 | + | | $04 = 24bit R8G8B8 | + | | $05 = 32bit A8R8G8B8 | + | | $06 = YUV888 | + | | $0E = YUV444 | + | | $07 = | + | | $08 = PLANAR 1BIT ATARI | + | | $09 = PLANAR 2BIT ATARI | + | | $0A = PLANAR 4BIT ATARI | + | | $0B = PLANAR 8BIT ATARI | + +-------+----------+-----------------------------------------+ + + ++ + + diff --git a/sources/official/saga-registers/hbstrt.htm b/sources/official/saga-registers/hbstrt.htm new file mode 100755 index 0000000..167deda --- /dev/null +++ b/sources/official/saga-registers/hbstrt.htm @@ -0,0 +1,21 @@ + + +
+ + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +HBSTOP 1C6 W A( E ) Horizontal line position for HBLANK stop +HBSTRT 1C4 W A( E ) Horizontal line position for HBLANK start +HCENTER 1E2 W A( E ) Horizontal position for Vsync on interlace +HSSTOP 1C2 W A( E ) Horizontal line position for HSYNC stop +HSSTRT 1DE W A( E ) Horizontal sync start (VARHSY) +HTOTAL 1C0 W A( E ) Highest number count, horiz. line + (VARBEAMEN=1) + + ++ + diff --git a/sources/official/saga-registers/hcenter.htm b/sources/official/saga-registers/hcenter.htm new file mode 100755 index 0000000..64fc0cc --- /dev/null +++ b/sources/official/saga-registers/hcenter.htm @@ -0,0 +1,23 @@ + + +
+ + + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +HBSTOP 1C6 W A( E ) Horizontal line position for HBLANK stop +HBSTRT 1C4 W A( E ) Horizontal line position for HBLANK start +HCENTER 1E2 W A( E ) Horizontal position for Vsync on interlace +HSSTOP 1C2 W A( E ) Horizontal line position for HSYNC stop +HSSTRT 1DE W A( E ) Horizontal sync start (VARHSY) +HTOTAL 1C0 W A( E ) Highest number count, horiz. line + (VARBEAMEN=1) + + + ++ + diff --git a/sources/official/saga-registers/hsstop.htm b/sources/official/saga-registers/hsstop.htm new file mode 100755 index 0000000..167deda --- /dev/null +++ b/sources/official/saga-registers/hsstop.htm @@ -0,0 +1,21 @@ + + +
+ + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +HBSTOP 1C6 W A( E ) Horizontal line position for HBLANK stop +HBSTRT 1C4 W A( E ) Horizontal line position for HBLANK start +HCENTER 1E2 W A( E ) Horizontal position for Vsync on interlace +HSSTOP 1C2 W A( E ) Horizontal line position for HSYNC stop +HSSTRT 1DE W A( E ) Horizontal sync start (VARHSY) +HTOTAL 1C0 W A( E ) Highest number count, horiz. line + (VARBEAMEN=1) + + ++ + diff --git a/sources/official/saga-registers/hsstrt.htm b/sources/official/saga-registers/hsstrt.htm new file mode 100755 index 0000000..ca4aa3f --- /dev/null +++ b/sources/official/saga-registers/hsstrt.htm @@ -0,0 +1,19 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +HBSTOP 1C6 W A( E ) Horizontal line position for HBLANK stop +HBSTRT 1C4 W A( E ) Horizontal line position for HBLANK start +HCENTER 1E2 W A( E ) Horizontal position for Vsync on interlace +HSSTOP 1C2 W A( E ) Horizontal line position for HSYNC stop +HSSTRT 1DE W A( E ) Horizontal sync start (VARHSY) +HTOTAL 1C0 W A( E ) Highest number count, horiz. line + (VARBEAMEN=1) + ++ + diff --git a/sources/official/saga-registers/htotal.htm b/sources/official/saga-registers/htotal.htm new file mode 100755 index 0000000..8e67ff7 --- /dev/null +++ b/sources/official/saga-registers/htotal.htm @@ -0,0 +1,20 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +HBSTOP 1C6 W A( E ) Horizontal line position for HBLANK stop +HBSTRT 1C4 W A( E ) Horizontal line position for HBLANK start +HCENTER 1E2 W A( E ) Horizontal position for Vsync on interlace +HSSTOP 1C2 W A( E ) Horizontal line position for HSYNC stop +HSSTRT 1DE W A( E ) Horizontal sync start (VARHSY) +HTOTAL 1C0 W A( E ) Highest number count, horiz. line + (VARBEAMEN=1) + + ++ + \ No newline at end of file diff --git a/sources/official/saga-registers/index.htm b/sources/official/saga-registers/index.htm new file mode 100755 index 0000000..48ebcdf --- /dev/null +++ b/sources/official/saga-registers/index.htm @@ -0,0 +1,3386 @@ + + +
| Address | +Name | +Access | +OCS | ECS | AGA | SAGA | +Description | +
|---|---|---|---|---|---|---|---|
| DFF000 | +BLTDDAT | +ER | +* | * | * | * | +Blitter dest. early read (dummy address) | +
| DFF002 | +DMACONR | +R | +* | * | * | * | +Dma control (and blitter status) read | +
| DFF004 | +VPOSR | +R | +* | * | * | * | +Read vertical most sig. bits (and frame flop) | +
| DFF006 | +VHPOSR | +R | +* | * | * | * | +Read vert and horiz position of beam | +
| DFF008 | +DSKDATR | +ER | +* | * | * | * | +Disk data early read (dummy address) | +
| DFF00A | +JOY0DAT | +R | +* | * | * | * | +Joystick-mouse 0 data (vert, horiz) | +
| DFF00C | +JOY1DAT | +R | +* | * | * | * | +Joystick-mouse 1 data (vert, horiz) | +
| DFF00E | +CLXDAT | +R | +* | * | * | * | +Collision data reg. (read and clear) | +
| DFF010 | +ADKCONR | +R | +* | * | * | * | +Audio,disk control register read | +
| DFF012 | +POT0DAT | +R | +* | * | * | * | +Pot counter data left pair (vert, horiz) | +
| DFF014 | +POT1DAT | +R | +* | * | * | * | +Pot counter data right pair (vert, horiz) | +
| DFF016 | +POTINP | +R | +* | * | * | * | +Pot pin data read | +
| DFF018 | +SERDATR | +R | +* | * | * | * | +Serial port data and status read | +
| DFF01A | +DSKBYTR | +R | +* | * | * | * | +Disk data byte and status read | +
| DFF01C | +INTENAR | +R | +* | * | * | * | +Interrupt enable bits read | +
| DFF01E | +INTREQR | +R | +* | * | * | * | +Interrupt request bits read | +
| DFF020 | +DSKPTH | +W | +* | * | * | * | +Disk pointer (high 5 bits, was 3 bits) | +
| DFF022 | +DSKPTL | +W | +* | * | * | * | +Disk pointer (low 15 bits) | +
| DFF024 | +DSKLEN | +W | +* | +* | * | * | +Disk length | +
| DFF026 | +DSKDAT | +W | +* | * | * | * | +Disk DMA data write | +
| DFF028 | +REFPTR | +W | +* | * | * | * | +Refresh pointer | +
| DFF02A | +VPOSW | +W | +* | * | * | * | +Write vert most sig. bits (and frame flop) | +
| DFF02C | +VHPOSW | +W | +* | * | * | * | +Write vert and horiz pos of beam | +
| DFF02E | +COPCON | +W | +* | * | * | * | +Coprocessor control | +
| DFF030 | +SERDAT | +W | +* | * | * | * | +Serial port data and stop bits write | +
| DFF032 | +SERPER | +W | +* | * | * | * | +Serial port period and control | +
| DFF034 | +POTGO | +W | +* | * | * | * | +Pot count start,pot pin drive enable data | +
| DFF036 | +JOYTEST | +W | +* | * | * | * | +Write to all 4 joystick-mouse counters at once | +
| DFF038 | +STREQU | +S | +* | * | * | * | +Strobe for horiz sync with VB and EQU | +
| DFF03A | +STRVBL | +S | +* | * | * | * | +Strobe for horiz sync with VB (vert blank) | +
| DFF03C | +STRHOR | +S | +* | * | * | * | +Strobe for horiz sync | +
| DFF03E | +STRLONG | +S | +* | * | * | * | +Strobe for identification of long horiz line | +
| DFF040 | +BLTCON0 | +W | +* | * | * | * | +Blitter control register 0 | +
| DFF042 | +BLTCON1 | +W | +* | * | * | * | +Blitter control register 1 | +
| DFF044 | +BLTAFWM | +W | +* | * | * | * | +Blitter first word mask for source A | +
| DFF046 | +BLTALWM | +W | +* | * | * | * | +Blitter last word mask for source A | +
| DFF048 | +BLTCPTH | +W | +* | * | * | * | +Blitter pointer to source C (high 5 bits, was 3 bits) | +
| DFF04A | +BLTCPTL | +W | +* | * | * | * | +Blitter pointer to source C (low 15 bits) | +
| DFF04C | +BLTBPTH | +W | +* | * | * | * | +Blitter pointer to source B (high 5 bits, was 3 bits) | +
| DFF04E | +BLTBPTL | +W | +* | * | * | * | +Blitter pointer to source B (low 15 bits) | +
| DFF050 | +BLTAPTH | +W | +* | * | * | * | +Blitter pointer to source A (high 5 bits, was 3 bits) | +
| DFF052 | +BLTAPTL | +W | +* | * | * | * | +Blitter pointer to source A (low 15 bits) | +
| DFF054 | +BLTDPTH | +W | +* | * | * | * | +Blitter pointer to dest D (high 5 bits, was 3 bits) | +
| DFF056 | +BLTDPTL | +W | +* | * | * | * | +Blitter pointer to dest D (low 15 bits) | +
| DFF058 | +BLTSIZE | +W | +* | * | * | * | +Blitter start and size (win/width,height) | +
| DFF05A | +BLTCON0L | +W | +* | * | * | +Blitter control 0, lower 8 bits (minterms) | +|
| DFF05C | +BLTSIZV | +W | +* | * | * | +Blitter V size (for 15 bit vertical size) | +|
| DFF05E | +BLTSIZH | +W | +* | * | * | +Blitter H size and start (for 11 bit H size) | +|
| DFF060 | +BLTCMOD | +W | +* | * | * | * | +Blitter modulo for source C | +
| DFF062 | +BLTBMOD | +W | +* | * | * | * | +Blitter modulo for source B | +
| DFF064 | +BLTAMOD | +W | +* | * | * | * | +Blitter modulo for source A | +
| DFF066 | +BLTDMOD | +W | +* | * | * | * | +Blitter modulo for dest D | +
| DFF070 | +BLTCDAT | +W | +* | * | * | * | +Blitter source C data register | +
| DFF072 | +BLTBDAT | +W | +* | * | * | * | +Blitter source B data register | +
| DFF074 | +BLTADAT | +W | +* | * | * | * | +Blitter source A data register | +
| DFF078 | +SPRHDAT | +W | +* | * | * | +Ext. logic UHRES sprite pointer and data identifier | +|
| DFF07A | +BPLHDAT | +W | +* | * | * | +Ext. logic UHRES bit plane identifier | +|
| DFF07C | +DENISEID | +R | +* | * | * | +Chip revision level for Denise/Lisa (video out chip) | +|
| DFF07E | +DSKSYNC | +W | +* | * | * | * | +Disk sync pattern reg for disk read | +
| DFF080 | +COP1LCH | +W | +* | * | * | * | +Coprocessor 1st location (high 5 bits,was 3 bits) | +
| DFF082 | +COP1LCL | +W | +* | * | * | * | +Coprocessor 1st location (low 15 bits) | +
| DFF084 | +COP2LCH | +W | +* | * | * | * | +Coprocessor 2nd location(high 5 bits,was 3 bits) | +
| DFF086 | +COP2LCL | +W | +* | * | * | * | +Coprocessor 2nd location (low 15 bits) | +
| DFF088 | +COPJMP1 | +S | +* | * | * | * | +Coprocessor restart at 1st location | +
| DFF08A | +COPJMP2 | +S | +* | * | * | * | +Coprocessor restart at 2nd location | +
| DFF08C | +COPINS | +S | +* | * | * | * | +Coprocessor inst fetch identify | +
| DFF08E | +DIWSTRT | +W | +* | * | * | * | +Display window start (upper left vert,horiz pos) | +
| DFF090 | +DIWSTOP | +W | +* | * | * | * | +Display window stop (lower right vert,horiz pos) | +
| DFF092 | +DDFSTRT | +W | +* | * | * | * | +Display bit plane data fetch start,horiz pos | +
| DFF094 | +DDFSTOP | +W | +* | * | * | * | +Display bit plane data fetch stop,horiz pos | +
| DFF096 | +DMACON | +W | +* | * | * | * | +DMA control write (clear or set) | +
| DFF098 | +CLXCON | +W | +* | * | * | * | +Collision control | +
| DFF09A | +INTENA | +W | +* | * | * | * | +Interrupt enable bits (clear or set bits) | +
| DFF09C | +INTREQ | +W | +* | * | * | * | +Interrupt request bits (clear or set bits) | +
| DFF09E | +ADKCON | +W | +* | * | * | * | +Audio,disk,UART control | +
| DFF0A0 | +AUD0LCH | +W | +* | * | * | * | +Audio channel 0 location (high 5 bits was 3 bits) | +
| DFF0A2 | +AUD0LCL | +W | +* | * | * | * | +Audio channel 0 location (low 15 bits) | +
| DFF0A4 | +AUD0LEN | +W | +* | * | * | * | +Audio channel 0 length | +
| DFF0A6 | +AUD0PER | +W | +* | * | * | * | +Audio channel 0 period | +
| DFF0A8 | +AUD0VOL | +W | +* | * | * | * | +Audio channel 0 volume | +
| DFF0AA | +AUD0DAT | +W | +* | * | * | * | +Audio channel 0 data | +
| DFF0B0 | +AUD1LCH | +W | +* | * | * | * | +Audio channel 1 location (high 5 bits was 3 bits) | +
| DFF0B2 | +AUD1LCL | +W | +* | * | * | * | +Audio channel 1 location (low 15 bits) | +
| DFF0B4 | +AUD1LEN | +W | +* | * | * | * | +Audio channel 1 length | +
| DFF0B6 | +AUD1PER | +W | +* | * | * | * | +Audio channel 1 period | +
| DFF0B8 | +AUD1VOL | +W | +* | * | * | * | +Audio channel 1 volume | +
| DFF0BA | +AUD1DAT | +W | +* | * | * | * | +Audio channel 1 data | +
| DFF0C0 | +AUD2LCH | +W | +* | * | * | * | +Audio channel 2 location (high 5 bits was 3 bits) | +
| DFF0C2 | +AUD2LCL | +W | +* | * | * | * | +Audio channel 2 location (low 15 bits) | +
| DFF0C4 | +AUD2LEN | +W | +* | * | * | * | +Audio channel 2 length | +
| DFF0C6 | +AUD2PER | +W | +* | * | * | * | +Audio channel 2 period | +
| DFF0C8 | +AUD2VOL | +W | +* | * | * | * | +Audio channel 2 volume | +
| DFF0CA | +AUD2DAT | +W | +* | * | * | * | +Audio channel 2 data | +
| DFF0D0 | +AUD3LCH | +W | +* | * | * | * | +Audio channel 3 location (high 5 bits was 3 bits) | +
| DFF0D2 | +AUD3LCL | +W | +* | * | * | * | +Audio channel 3 location (low 15 bits) | +
| DFF0D4 | +AUD3LEN | +W | +* | * | * | * | +Audio channel 3 length | +
| DFF0D6 | +AUD3PER | +W | +* | * | * | * | +Audio channel 3 period | +
| DFF0D8 | +AUD3VOL | +W | +* | * | * | * | +Audio channel 3 volume | +
| DFF0DA | +AUD3DAT | +W | +* | * | * | * | +Audio channel 3 data | +
| DFF0E0 | +BPL1PTH | +W | +* | * | * | * | +Bitplane pointer 1 (high 5 bits was 3 bits) | +
| DFF0E2 | +BPL1PTL | +W | +* | * | * | * | +Bitplane pointer 1 (low 15 bits) | +
| DFF0E4 | +BPL2PTH | +W | +* | * | * | * | +Bitplane pointer 2 (high 5 bits was 3 bits) | +
| DFF0E6 | +BPL2PTL | +W | +* | * | * | * | +Bitplane pointer 2 (low 15 bits) | +
| DFF0E8 | +BPL3PTH | +W | +* | * | * | * | +Bitplane pointer 3 (high 5 bits was 3 bits) | +
| DFF0EA | +BPL3PTL | +W | +* | * | * | * | +Bitplane pointer 3 (low 15 bits) | +
| DFF0EC | +BPL4PTH | +W | +* | * | * | * | +Bitplane pointer 4 (high 5 bits was 3 bits) | +
| DFF0EE | +BPL4PTL | +W | +* | * | * | * | +Bitplane pointer 4 (low 15 bits) | +
| DFF0F0 | +BPL5PTH | +W | +* | * | * | * | +Bitplane pointer 5 (high 5 bits was 3 bits) | +
| DFF0F2 | +BPL5PTL | +W | +* | * | * | * | +Bitplane pointer 5 (low 15 bits) | +
| DFF0F4 | +BPL6PTH | +W | +* | * | * | * | +Bitplane pointer 6 (high 5 bits was 3 bits) | +
| DFF0F6 | +BPL6PTL | +W | +* | * | * | * | +Bitplane pointer 6 (low 15 bits) | +
| DFF0F8 | +BPL7PTH | +W | +* | * | +Bitplane pointer 7 (high 5 bits was 3 bits) | +||
| DFF0FA | +BPL7PTL | +W | +* | * | +Bitplane pointer 7 (low 15 bits) | +||
| DFF0FC | +BPL8PTH | +W | +* | * | +Bitplane pointer 8 (high 5 bits was 3 bits) | +||
| DFF0FE | +BPL8PTL | +W | +* | * | +Bitplane pointer 8 (low 15 bits) | +||
| DFF100 | +BPLCON0 | +W | +* | * | * | * | +Bitplane control (miscellaneous control bits) | +
| DFF102 | +BPLCON1 | +W | +* | * | * | * | +Bitplane control (scroll value) | +
| DFF104 | +BPLCON2 | +W | +* | * | * | * | +Bitplane control (video priority control) | +
| DFF106 | +BPLCON3 | +W | +* | * | * | * | +Bitplane control (enhanced features) | +
| DFF108 | +BPL1MOD | +W | +* | * | * | * | +Bitplane modulo (odd planes) | +
| DFF10A | +BPL2MOD | +W | +* | * | * | * | +Bitplane modulo (even planes) | +
| DFF10C | +BPLCON4 | +W | +* | * | +Bitplane control (bitplane and sprite-masks) | +||
| DFF10E | +CLXCON2 | +W | +* | * | +Extended collision control | +||
| DFF110 | +BPL1DAT | +W | +* | * | * | * | +Bitplane 1 data (parallel to serial convert) | +
| DFF112 | +BPL2DAT | +W | +* | * | * | * | +Bitplane 2 data (parallel to serial convert) | +
| DFF114 | +BPL3DAT | +W | +* | * | * | * | +Bitplane 3 data (parallel to serial convert) | +
| DFF116 | +BPL4DAT | +W | +* | * | * | * | +Bitplane 4 data (parallel to serial convert) | +
| DFF118 | +BPL5DAT | +W | +* | * | * | * | +Bitplane 5 data (parallel to serial convert) | +
| DFF11A | +BPL6DAT | +W | +* | * | * | * | +Bitplane 6 data (parallel to serial convert) | +
| DFF11C | +BPL7DAT | +W | +* | * | +Bitplane 7 data (parallel to serial convert) | +||
| DFF11E | +BPL8DAT | +W | +* | * | +Bitplane 8 data (parallel to serial convert) | +||
| DFF120 | +SPR0PTH | +W | +* | * | * | * | +Sprite 0 pointer (high 5 bits was 3 bits) | +
| DFF122 | +SPR0PTL | +W | +* | * | * | * | +Sprite 0 pointer (low 15 bits) | +
| DFF124 | +SPR1PTH | +W | +* | * | * | * | +Sprite 1 pointer (high 5 bits was 3 bits) | +
| DFF126 | +SPR1PTL | +W | +* | * | * | * | +Sprite 1 pointer (low 15 bits) | +
| DFF128 | +SPR2PTH | +W | +* | * | * | * | +Sprite 2 pointer (high 5 bits was 3 bits) | +
| DFF12A | +SPR2PTL | +W | +* | * | * | * | +Sprite 2 pointer (low 15 bits) | +
| DFF12C | +SPR3PTH | +W | +* | * | * | * | +Sprite 3 pointer (high 5 bits was 3 bits) | +
| DFF12E | +SPR3PTL | +W | +* | * | * | * | +Sprite 3 pointer (low 15 bits) | +
| DFF130 | +SPR4PTH | +W | +* | * | * | * | +Sprite 4 pointer (high 5 bits was 3 bits) | +
| DFF132 | +SPR4PTL | +W | +* | * | * | * | +Sprite 4 pointer (low 15 bits) | +
| DFF134 | +SPR5PTH | +W | +* | * | * | * | +Sprite 5 pointer (high 5 bits was 3 bits) | +
| DFF136 | +SPR5PTL | +W | +* | * | * | * | +Sprite 5 pointer (low 15 bits) | +
| DFF138 | +SPR6PTH | +W | +* | * | * | * | +Sprite 6 pointer (high 5 bits was 3 bits) | +
| DFF13A | +SPR6PTL | +W | +* | * | * | * | +Sprite 6 pointer (low 15 bits) | +
| DFF13C | +SPR7PTH | +W | +* | * | * | * | +Sprite 7 pointer (high 5 bits was 3 bits) | +
| DFF13E | +SPR7PTL | +W | +* | * | * | * | +Sprite 7 pointer (low 15 bits) | +
| DFF140 | +SPR0POS | +W | +* | * | * | * | +Sprite 0 vert,horiz start pos data | +
| DFF142 | +SPR0CTL | +W | +* | * | * | * | +Sprite 0 position and control data | +
| DFF144 | +SPR0DATA | +W | +* | * | * | * | +Sprite 0 image data register A | +
| DFF146 | +SPR0DATB | +W | +* | * | * | * | +Sprite 0 image data register B | +
| DFF148 | +SPR1POS | +W | +* | * | * | * | +Sprite 1 vert,horiz start pos data | +
| DFF14A | +SPR1CTL | +W | +* | * | * | * | +Sprite 1 position and control data | +
| DFF14C | +SPR1DATA | +W | +* | * | * | * | +Sprite 1 image data register A | +
| DFF14E | +SPR1DATB | +W | +* | * | * | * | +Sprite 1 image data register B | +
| DFF150 | +SPR2POS | +W | +* | * | * | * | +Sprite 2 vert,horiz start pos data | +
| DFF152 | +SPR2CTL | +W | +* | * | * | * | +Sprite 2 position and control data | +
| DFF154 | +SPR2DATA | +W | +* | * | * | * | +Sprite 2 image data register A | +
| DFF156 | +SPR2DATB | +W | +* | * | * | * | +Sprite 2 image data register B | +
| DFF158 | +SPR3POS | +W | +* | * | * | * | +Sprite 3 vert,horiz start pos data | +
| DFF15A | +SPR3CTL | +W | +* | * | * | * | +Sprite 3 position and control data | +
| DFF15C | +SPR3DATA | +W | +* | * | * | * | +Sprite 3 image data register A | +
| DFF15E | +SPR3DATB | +W | +* | * | * | * | +Sprite 3 image data register B | +
| DFF160 | +SPR4POS | +W | +* | * | * | * | +Sprite 4 vert,horiz start pos data | +
| DFF162 | +SPR4CTL | +W | +* | * | * | * | +Sprite 4 position and control data | +
| DFF164 | +SPR4DATA | +W | +* | * | * | * | +Sprite 4 image data register A | +
| DFF166 | +SPR4DATB | +W | +* | * | * | * | +Sprite 4 image data register B | +
| DFF168 | +SPR5POS | +W | +* | * | * | * | +Sprite 5 vert,horiz start pos data | +
| DFF16A | +SPR5CTL | +W | +* | * | * | * | +Sprite 5 position and control data | +
| DFF16C | +SPR5DATA | +W | +* | * | * | * | +Sprite 5 image data register A | +
| DFF16E | +SPR5DATB | +W | +* | * | * | * | +Sprite 5 image data register B | +
| DFF170 | +SPR6POS | +W | +* | * | * | * | +Sprite 6 vert,horiz start pos data | +
| DFF172 | +SPR6CTL | +W | +* | * | * | * | +Sprite 6 position and control data | +
| DFF174 | +SPR6DATA | +W | +* | * | * | * | +Sprite 6 image data register A | +
| DFF176 | +SPR6DATB | +W | +* | * | * | * | +Sprite 6 image data register B | +
| DFF178 | +SPR7POS | +W | +* | * | * | * | +Sprite 7 vert,horiz start pos data | +
| DFF17A | +SPR7CTL | +W | +* | * | * | * | +Sprite 7 position and control data | +
| DFF17C | +SPR7DATA | +W | +* | * | * | * | +Sprite 7 image data register A | +
| DFF17E | +SPR7DATB | +W | +* | * | * | * | +Sprite 7 image data register B | +
| DFF180 | +COLOR00 | +W | +* | * | * | * | +Color table 0 | +
| DFF182 | +COLOR01 | +W | +* | * | * | * | +Color table 1 | +
| DFF184 | +COLOR02 | +W | +* | * | * | * | +Color table 2 | +
| DFF186 | +COLOR03 | +W | +* | * | * | * | +Color table 3 | +
| DFF188 | +COLOR04 | +W | +* | * | * | * | +Color table 4 | +
| DFF18A | +COLOR05 | +W | +* | * | * | * | +Color table 5 | +
| DFF18C | +COLOR06 | +W | +* | * | * | * | +Color table 6 | +
| DFF18E | +COLOR07 | +W | +* | * | * | * | +Color table 7 | +
| DFF190 | +COLOR08 | +W | +* | * | * | * | +Color table 8 | +
| DFF192 | +COLOR09 | +W | +* | * | * | * | +Color table 9 | +
| DFF194 | +COLOR10 | +W | +* | * | * | * | +Color table 10 | +
| DFF196 | +COLOR11 | +W | +* | * | * | * | +Color table 11 | +
| DFF198 | +COLOR12 | +W | +* | * | * | * | +Color table 12 | +
| DFF19A | +COLOR13 | +W | +* | * | * | * | +Color table 13 | +
| DFF19C | +COLOR14 | +W | +* | * | * | * | +Color table 14 | +
| DFF19E | +COLOR15 | +W | +* | * | * | * | +Color table 15 | +
| DFF1A0 | +COLOR16 | +W | +* | * | * | * | +Color table 16 | +
| DFF1A2 | +COLOR17 | +W | +* | * | * | * | +Color table 17 | +
| DFF1A4 | +COLOR18 | +W | +* | * | * | * | +Color table 18 | +
| DFF1A6 | +COLOR19 | +W | +* | * | * | * | +Color table 19 | +
| DFF1A8 | +COLOR20 | +W | +* | * | * | * | +Color table 20 | +
| DFF1AA | +COLOR21 | +W | +* | * | * | * | +Color table 21 | +
| DFF1AC | +COLOR22 | +W | +* | * | * | * | +Color table 22 | +
| DFF1AE | +COLOR23 | +W | +* | * | * | * | +Color table 23 | +
| DFF1B0 | +COLOR24 | +W | +* | * | * | * | +Color table 24 | +
| DFF1B2 | +COLOR25 | +W | +* | * | * | * | +Color table 25 | +
| DFF1B4 | +COLOR26 | +W | +* | * | * | * | +Color table 26 | +
| DFF1B6 | +COLOR27 | +W | +* | * | * | * | +Color table 27 | +
| DFF1B8 | +COLOR28 | +W | +* | * | * | * | +Color table 28 | +
| DFF1BA | +COLOR29 | +W | +* | * | * | * | +Color table 29 | +
| DFF1BC | +COLOR30 | +W | +* | * | * | * | +Color table 30 | +
| DFF1BE | +COLOR31 | +W | +* | * | * | * | +Color table 31 | +
| DFF1C0 | +HTOTAL | +W | +* | * | * | +Highest number count, horiz line (VARBEAMEN=1) | +|
| DFF1C2 | +HSSTOP | +W | +* | * | * | +Horizontal line position for HSYNC stop | +|
| DFF1C4 | +HBSTRT | +W | +* | * | * | +Horizontal line position for HBLANK start | +|
| DFF1C6 | +HBSTOP | +W | +* | * | * | +Horizontal line position for HBLANK stop | +|
| DFF1C8 | +VTOTAL | +W | +* | * | * | +Highest numbered vertical line (VARBEAMEN=1) | +|
| DFF1CA | +VSSTOP | +W | +* | * | * | +Vertical line position for VSYNC stop | +|
| DFF1CC | +VBSTRT | +W | +* | * | * | +Vertical line for VBLANK start | +|
| DFF1CE | +VBSTOP | +W | +* | * | * | +Vertical line for VBLANK stop | +|
| DFF1D0 | +SPRHSTRT | +W | +* | * | * | +CHUNKY SPRITE X Pos | +|
| DFF1D2 | +SPRHSTOP | +W | +* | * | * | +CHUNKY SPRITE Y POS | +|
| DFF1D4 | +BPLHSTRT | +W | +* | * | * | +UHRES bit plane vertical start | +|
| DFF1D6 | +BPLHSTOP | +W | +* | * | * | +UHRES bit plane vertical stop | +|
| DFF1D8 | +HHPOSW | +W | +* | * | * | +DUAL mode hires H beam counter write | +|
| DFF1DA | +HHPOSR | +R | +* | * | * | +DUAL mode hires H beam counter read | +|
| DFF1DC | +BEAMCON0 | +W | +* | * | * | * | +Beam counter control register (SHRES,UHRES,PAL) | +
| DFF1DE | +HSSTRT | +W | +* | * | * | +Horizontal sync start (VARHSY) | +|
| DFF1E0 | +VSSTRT | +W | +* | * | * | +Vertical sync start (VARVSY) | +|
| DFF1E2 | +HCENTER | +W | +* | * | * | +Horizontal position for Vsync on interlace | +|
| DFF1E4 | +DIWHIGH | +W | +* | * | * | +Display window - upper bits for start/stop | +|
| DFF1E6 | +BPLHMOD | +W | +* | +Chunky plane modulo | +|||
| DFF1E8 | +SPRHPTH | +W | +* | * | * | +UHRES sprite pointer (high 5 bits) | +|
| DFF1EA | +SPRHPTL | +W | +* | * | * | +UHRES sprite pointer (low 15 bits) | +|
| DFF1EC | +BPLHPTH | +W | +* | +Chunky plane pointer (hi 15 bits) | +|||
| DFF1EE | +BPLHPTL | +W | +* | +Chunky plane pointer (lo 15 bits) | +|||
| DFF1F4 | +GFXMODE | +W | +* | +Set Resolution and Pixformat | +|||
| DFF1FC | +FMODE | +W | +* | * | +Fetch mode register | +||
| Address | +Name | +Access | +OCS | ECS | AGA | SAGA | +Description | +
| DFF202 | +DMACON2 Read | +R | +* | ++ | |||
| DFF20A | +JOY0DAT | +R | +* | * | * | * | +Vanilla DB9 Joystick-mouse 0 data (vert, horiz) | +
| DFF20C | +JOY1DAT | +R | +* | * | * | * | +Vaniall DB9 Joystick-mouse 1 data (vert, horiz) | +
| DFF212 | +Mouse Wheel | +R | +* | +Mouse Wheel read register | +|||
| DFF21c | +INTENA2 Read | +R | +* | ++ | |||
| DFF21E | +INTREQ2 Read | +R | +* | ++ | |||
| DFF220 | +joy0buttons | +R | +* | +16bit USB Joy Buttons (0)=active | +|||
| DFF222 | +joy1buttons | +R | +* | +16bit USB Joy Buttons (0)=active | +|||
| DFF224 | +joy2buttons | +R | +* | +16bit USB Joy Buttons (0)=active | +|||
| DFF226 | +joy3buttons | +R | +* | +16bit USB Joy Buttons (0)=active | +|||
| DFF230 | +clxdat0 | +R | +* | +Sprite0 Detailed Collision | +|||
| DFF232 | +clxdat1 | +R | +* | +Sprite1 Detailed Collision | +|||
| DFF234 | +clxdat2 | +R | +* | +Sprite2 Detailed Collision | +|||
| DFF236 | +clxdat3 | +R | +* | +Sprite3 Detailed Collision | +|||
| DFF238 | +clxdat4 | +R | +* | +Sprite4 Detailed Collision | +|||
| DFF23A | +clxdat5 | +R | +* | +Sprite5 Detailed Collision | +|||
| DFF23C | +clxdat6 | +R | +* | +Sprite6 Detailed Collision | +|||
| DFF23E | +clxdat7 | +R | +* | +Sprite7 Detailed Collision | +|||
| DFF250 | +TEXTPT | +W | +* | +3D 32bit texture source | +|||
| DFF254 | +TEXDPT | +W | +* | +3D 32bit Destination Screen Addr | +|||
| DFF258 | +TEXZPT | +W | +* | +3D ZBuffer Addr | +|||
| DFF25E | +TEXSTRT | +W | +* | +3D 16bit LEN and START +Bit15=0 = Start new job +Bit15=1 = Continue previous job +Bit10..0 = length in pixel + |
+|||
| DFF260 | +TEXMIP | +W | +* | +3D 16bit MIP texture size bit(3..0) ($A=1024/9=512/8=256/7=128/6=64/5=32)
+ Bit4='1' = AutoMipMapMode with Bit3-0 define max mip |
+|||
| DFF262 | +TEXMODE | +W | +* | +3D 16bit MODE
+ (Bit0=use Bilienar) +(Bit1=use Zbuffer) +(Bit2=select 16bit output) +(Bit3=inhibit Zbuffer write) +(Bit4=select 24bit output) +(Bit5=quadratic-mode) +(Bit7-6= BLENDMode "00" =COPY) +(Bit7-6= BLENDMode "01" =ADD) +(Bit7-6= BLENDMode "10" =MUL) + |
+|||
| DFF266 | +TEXDMOD | +W | +* | +3D 16bit signed Destination Step | +|||
| DFF268 | +TEXddUUuuuu | +W | +* | +3D 24bit ddUUuuuu (quadratic) | +|||
| DFF26C | +TEXddVVvvvv | +W | +* | +3D 24bit ddVVvvvv (quadratic) | +|||
| DFF270 | +TEXUUuuuu | +W | +* | +3D 24bit UUuuuu | +|||
| DFF274 | +TEXVVvvvv | +W | +* | +3D 24bit VVvvvv | +|||
| DFF278 | +TEXdUUuuuu | +W | +* | +3D 24bit dUUuuuu | +|||
| DFF27C | +TEXdVVvvvv | +W | +* | +3D 24bit dVVvvvv | +|||
| DFF280 | +TEXLight | +W | +* | +3D 16bit Light Ll | +|||
| DFF282 | +TEXdLight | +W | +* | +3D 16bit Light dLl | +|||
| DFF284 | +TEXLightcolor | +W | +* | +3D 32bit Light color | +|||
| DFF288 | +TEXZZzz | +W | +* | +3D 32bit ZZZZzzzz | +|||
| DFF28C | +TEXdZZzz | +W | +* | +3D 32bit Delta ZZZZzzzz | +|||
| DFF296 | +DMACON2 | +W | +* | +DMACON2 | +|||
| DFF29A | +INTENA2 | +W | +* | +INTENA2 | +|||
| DFF29C | +INTREQ2 | +W | +* | +INTREQ2 | +|||
| DFF380 | +PlanarCOLH | +W | +* | +32bit Planar COLOR Port register | +|||
| DFF382 | +PlanarCOLL | +W | +* | +256 Color Register, Format [ID,RR,GG,BB] | +|||
| DFF384 | +SpriteCOLH | +W | +* | +32bit Sprite COLOR Port register | +|||
| DFF386 | +SpriteCOLL | +W | +* | +256 Color Register, Format [ID,RR,GG,BB] | +|||
| DFF388 | +ChunkyCOLH | +W | +* | +32bit Chunky COLOR Port register | +|||
| DFF38A | +ChunkyCOLL | +W | +* | +256 Color Register, Format [ID,RR,GG,BB] | +|||
| DFF38C | +PIPCOLH | +W | +* | +32bit PIP COLOR Port register | +|||
| DFF38E | +PIPCOLL | +W | +* | +256 Color Register, Format [ID,RR,GG,BB] | +|||
| DFF390/92 | +SCREENMODE ADJUST | +W | +* | +Adjust Y/X for Screenmodes | +|||
| DFF3A2 | +Sprite Col1 | +W | +* | +Word register RGB (11..0) | +|||
| DFF3A4 | +Sprite Col2 | +W | +* | +Word register RGB (11..0) | +|||
| DFF3A6 | +Sprite Col3 | +W | +* | +Word register RGB (11..0) | +|||
| DFF3D0 | +PipXStrt | +W | +* | +X start | +|||
| DFF3D2 | +PipYStrt | +W | +* | +Y start | +|||
| DFF3D4 | +PipXStop | +W | +* | +X stop | +|||
| DFF3D6 | +PipYStop | +W | +* | +Y stop | +|||
| DFF3D8 | +PipPtr | +W | +* | +32 bit Ptr | +|||
| DFF3DC | +PipFormat | +W | +* | +Colorformat (8bit/16bit/15bit/YUV) | +|||
| DFF3DE | +PipModulo | +W | +* | +Modulo | +|||
| DFF3E0 | +PipColorKey | +W | +* | +ColorKey 1000,RRRR,GGGG,BBBB | +|||
| DFF3E2 | +PipDMARowLen | +W | +* | +PipDMARowLen | +|||
| DFF3EA | +CORE REVISION | +R | +* | +Reserved | +|||
| DFF3EC | +SAGA CONTROL REG | +R | +* | +Reserved | +|||
| DFF3EE | +SCREEN SHIFT | +R | +* | +Reserved | +|||
| DFF3F0 | +CHIP ID | +R | +* | ++ | |||
| DFF3F2 | +CHIP ID | +R | +* | ++ | |||
| DFF3F4 | +CHIP ID | +R | +* | ++ | |||
| DFF3F6 | +CHIP ID | +R | +* | ++ | |||
| DFF3F8 | +SPI WRITE | +R | +* | +Reserved | +|||
| DFF3FA | +SPI read | +R | +* | +Reserved | +|||
| DFF3FC | +VAMPIRE VERSION | +R | +* | +8bit Card Version / 8bit clock multiplier | +|||
| Address | +Name | +Access | +OCS | ECS | AGA | SAGA | +Description | +
| DFF400 | +AUD0L | +W | +* | +Audio channel 0 location (32bit PTR) | +|||
| DFF402 | +AUD0L | +W | +* | ++ | |||
| DFF404 | +AUD0LEN | +W | +* | +Audio channel 0 length (32bit) | +|||
| DFF406 | +AUD0LEN | +W | +* | ++ | |||
| DFF408 | +AUD0VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF40A | +AUD0CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF40C | +AUD0PER | +W | +* | +16bit PERIOD | +|||
| DFF410 | +AUD1L | +W | +* | +Audio channel 1 location (32bit PTR) | +|||
| DFF412 | +AUD1L | +W | +* | ++ | |||
| DFF414 | +AUD1LEN | +W | +* | +Audio channel 1 length (32bit) | +|||
| DFF416 | +AUD1LEN | +W | +* | ++ | |||
| DFF418 | +AUD1VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF41A | +AUD1CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF41C | +AUD1PER | +W | +* | +16bit PERIOD | +|||
| DFF420 | +AUD2L | +W | +* | +Audio channel 2 location (32bit PTR) | +|||
| DFF422 | +AUD2L | +W | +* | ++ | |||
| DFF424 | +AUD2LEN | +W | +* | +Audio channel 2 length (32bit) | +|||
| DFF426 | +AUD2LEN | +W | +* | ++ | |||
| DFF428 | +AUD2VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF42A | +AUD2CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF42C | +AUD2PER | +W | +* | +16bit PERIOD | +|||
| DFF430 | +AUD3L | +W | +* | +Audio channel 1 location (32bit PTR) | +|||
| DFF432 | +AUD3L | +W | +* | ++ | |||
| DFF434 | +AUD3LEN | +W | +* | +Audio channel 3 length (32bit) | +|||
| DFF436 | +AUD3LEN | +W | +* | ++ | |||
| DFF438 | +AUD3VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF43A | +AUD3CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF43C | +AUD3PER | +W | +* | +16bit PERIOD | +|||
| DFF440 | +AUD4L | +W | +* | +Audio channel 4 location (32bit PTR) | +|||
| DFF442 | +AUD4L | +W | +* | ++ | |||
| DFF444 | +AUD4LEN | +W | +* | +Audio channel 4 length (32bit) | +|||
| DFF446 | +AUD4LEN | +W | +* | ++ | |||
| DFF448 | +AUD4VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF44A | +AUD4CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF44C | +AUD4PER | +W | +* | +16bit PERIOD | +|||
| DFF450 | +AUD5L | +W | +* | +Audio channel 5 location (32bit PTR) | +|||
| DFF452 | +AUD5L | +W | +* | ++ | |||
| DFF454 | +AUD5LEN | +W | +* | +Audio channel 5 length (32bit) | +|||
| DFF456 | +AUD5LEN | +W | +* | ++ | |||
| DFF458 | +AUD5VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF45A | +AUD5CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF45C | +AUD5PER | +W | +* | +16bit PERIOD | +|||
| DFF460 | +AUD6L | +W | +* | +Audio channel 6 location (32bit PTR) | +|||
| DFF462 | +AUD6L | +W | +* | ++ | |||
| DFF464 | +AUD6LEN | +W | +* | +Audio channel 6 length (32bit) | +|||
| DFF466 | +AUD6LEN | +W | +* | ++ | |||
| DFF468 | +AUD6VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF46A | +AUD6CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF46C | +AUD6PER | +W | +* | +16bit PERIOD | +|||
| DFF470 | +AUD7L | +W | +* | +Audio channel 7 location (32bit PTR) | +|||
| DFF472 | +AUD7L | +W | +* | ++ | |||
| DFF474 | +AUD7LEN | +W | +* | +Audio channel 7 length (32bit) | +|||
| DFF476 | +AUD7LEN | +W | +* | ++ | |||
| DFF478 | +AUD7VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF47A | +AUD7CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF47C | +AUD7PER | +W | +* | +16bit PERIOD | +|||
| DFF480 | +AUD8L | +W | +* | +Audio channel 8 location (32bit PTR) | +|||
| DFF482 | +AUD8L | +W | +* | ++ | |||
| DFF484 | +AUD8LEN | +W | +* | +Audio channel 8 length (32bit) | +|||
| DFF486 | +AUD8LEN | +W | +* | ++ | |||
| DFF488 | +AUD8VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF48A | +AUD8CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF48C | +AUD8PER | +W | +* | +16bit PERIOD | +|||
| DFF490 | +AUD9L | +W | +* | +Audio channel 9 location (32bit PTR) | +|||
| DFF492 | +AUD9L | +W | +* | ++ | |||
| DFF494 | +AUD9LEN | +W | +* | +Audio channel 9 length (32bit) | +|||
| DFF496 | +AUD9LEN | +W | +* | ++ | |||
| DFF498 | +AUD9VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF49A | +AUD9CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF49C | +AUD9PER | +W | +* | +16bit PERIOD | +|||
| DFFAA0 | +AUD10L | +W | +* | +Audio channel 10 location (32bit PTR) | +|||
| DFF4A2 | +AUD10L | +W | +* | ++ | |||
| DFF4A4 | +AUD10LEN | +W | +* | +Audio channel 10 length (32bit) | +|||
| DFF4A6 | +AUD10LEN | +W | +* | ++ | |||
| DFF4A8 | +AUD10VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF4AA | +AUD10CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF4AC | +AUD10PER | +W | +* | +16bit PERIOD | +|||
| DFF4B0 | +AUD11L | +W | +* | +Audio channel 11 location (32bit PTR) | +|||
| DFF4B2 | +AUD11L | +W | +* | ++ | |||
| DFF4B4 | +AUD11LEN | +W | +* | +Audio channel 11 length (32bit) | +|||
| DFF4B6 | +AUD11LEN | +W | +* | ++ | |||
| DFF4B8 | +AUD11VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF4BA | +AUD11CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF4BC | +AUD11PER | +W | +* | +16bit PERIOD | +|||
| DFF4C0 | +AUD12L | +W | +* | +Audio channel 12 location (32bit PTR) | +|||
| DFF4C2 | +AUD12L | +W | +* | ++ | |||
| DFF4C4 | +AUD12LEN | +W | +* | +Audio channel 12 length (32bit) | +|||
| DFF4C6 | +AUD12LEN | +W | +* | ++ | |||
| DFF4C8 | +AUD12VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF4CA | +AUD12CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF4C4C | +AUD12PER | +W | +* | +16bit PERIOD | +|||
| DFF4D0 | +AUD13L | +W | +* | +Audio channel 13 location (32bit PTR) | +|||
| DFF4D2 | +AUD13L | +W | +* | ++ | |||
| DFF4D4 | +AUD13LEN | +W | +* | +Audio channel 13 length (32bit) | +|||
| DFF4D6 | +AUD13LEN | +W | +* | ++ | |||
| DFF4D8 | +AUD13VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF4DA | +AUD13CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF4DC | +AUD13PER | +W | +* | +16bit PERIOD | +|||
| DFF4E0 | +AUD14L | +W | +* | +Audio channel 14 location (32bit PTR) | +|||
| DFF4E2 | +AUD14L | +W | +* | ++ | |||
| DFF4E4 | +AUD14LEN | +W | +* | +Audio channel 14 length (32bit) | +|||
| DFF4E6 | +AUD14LEN | +W | +* | ++ | |||
| DFF4E8 | +AUD14VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF4EA | +AUD14CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF4EC | +AUD14PER | +W | +* | +16bit PERIOD | +|||
| DFF4F0 | +AUD15L | +W | +* | +Audio channel 15 location (32bit PTR) | +|||
| DFF4F2 | +AUD15L | +W | +* | ++ | |||
| DFF4F4 | +AUD15LEN | +W | +* | +Audio channel 15 length (32bit) | +|||
| DFF4F6 | +AUD15LEN | +W | +* | ++ | |||
| DFF4F8 | +AUD15VOL | +W | +* | +2x8bit VOL (LEFT/RIGHT) | +|||
| DFF4FA | +AUD15CTRL | +W | +* | +16 Control bits +2= Stereo +1= Oneshot +0= (8bit/16bit) | +|||
| DFF4FC | +AUD15PER | +W | +* | +16bit PERIOD | +|||
| ATARI CHIPSET | +|||||||
| DF8200 | SHIFTER COLORS | +R/W | * | SHIFTER COLORS | +|||
| DF8800 | YAMAHA_R | +R/W | * | YAMAHA AUDIO | +|||
| DF8802 | YAMAHA_W | +R/W | * | YAMAHA AUDIO | +|||
| DFFA07 | MFP_IERA | +R/W | * | MFP Timer | +|||
| DFFA09 | +MFP_IERB | +R/W | +* | +MFP Timer | +|||
| DFFA0B | +MFP_IPRA | +R/W | +* | +MFP Timer | +|||
| DFFA0D | +MFP_IPRB | +R/W | +* | +MFP Timer | +|||
| DFFA0F | +MFP_ISRA | +R/W | +* | +MFP Timer | +|||
| DFFA11 | +MFP_ISRB | +R/W | +* | +MFP Timer | +|||
| DFFA13 | +MFP_IMRA | +R/W | +* | +MFP Timer | +|||
| DFFA15 | +MFP_IMRB | +R/W | +* | +MFP Timer | +|||
| DFFA17 | +MFP_VEC | +R/W | +* | +MFP Timer | +|||
| DFFA19 | +MFP_TACR | +R/W | +* | +MFP Timer | +|||
| DFFA1B | +MFP_TBCR | +R/W | +* | +MFP Timer | +|||
| DFFA1D | +MFP_TCDCR | +R/W | +* | +MFP Timer | +|||
| DFFA1F | MFP_TADR | +R/W | * | MFP Timer | + +|||
| DFFA21 | MFP_TBDR | +R/W | * | MFP Timer | + + +|||
| DFFA23 | MFP_TCDR | +R/W | * | MFP Timer | + +|||
| DFFA25 | MFP_TDDR | +R/W | * | MFP Timer | + + +|||
+ +INTENA2 + +This register contains interrupt enable bits. The bit assignment for +both the request, and enable registers is given below + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 15 | | SET/CLR | + | 14 | | | + | 13 | ETH | Ethernet | + | 12 | | | + | 11 | AUD15 | Audio channel 15 block finished | + | 10 | AUD14 | Audio channel 14 block finished | + | 09 | AUD13 | Audio channel 13 block finished | + | 08 | AUD12 | Audio channel 12 block finished | + | 07 | AUD11 | Audio channel 11 block finished | + | 06 | AUD10 | Audio channel 10 block finished | + | 05 | AUD9 | Audio channel 9 block finished | + | 04 | AUD8 | Audio channel 8 block finished | + | 03 | AUD7 | Audio channel 7 block finished | + | 02 | AUD6 | Audio channel 6 block finished | + | 01 | AUD5 | Audio channel 5 block finished | + | 00 | AUD4 | Audio channel 4 block finished | + +-------+----------+-------------------------------------------+ + + +Ethernet will throw IRQ $48 +The new Audio channels will throw IRQ $50 + + + ++ + diff --git a/sources/official/saga-registers/intenar.htm b/sources/official/saga-registers/intenar.htm new file mode 100755 index 0000000..57c3023 --- /dev/null +++ b/sources/official/saga-registers/intenar.htm @@ -0,0 +1,41 @@ + + +
+ Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +INTENA 09A W P Interrupt enable bits (clear or set bits) +INTENAR 01C R P Interrupt enable bits (read) + + This register contains interrupt enable bits. The bit + assignment for both the request and enable registers + is given below. + + BIT# FUNCT LEVEL DESCRIPTION + ---- ------ ----- ---------------------------------- + 15 SET/CLR Set/clear control bit. Determines if + bits written with a 1 get set or + cleared. Bits written with a zero + are always unchanged. + 14 INTEN Master interrupt (enable only, + no request) + 13 EXTER 6 External interrupt + 12 DSKSYN 5 Disk sync register ( DSKSYNC ) + matches disk data + 11 RBF 5 Serial port receive buffer full + 10 AUD3 4 Audio channel 3 block finished + 09 AUD2 4 Audio channel 2 block finished + 08 AUD1 4 Audio channel 1 block finished + 07 AUD0 4 Audio channel 0 block finished + 06 BLIT 3 Blitter finished + 05 VERTB 3 Start of vertical blank + 04 COPER 3 Copper + 03 PORTS 2 I/O ports and timers + 02 SOFT 1 Reserved for software-initiated + interrupt + 01 DSKBLK 1 Disk block finished + 00 TBE 1 Serial port transmit buffer empty ++ + diff --git a/sources/official/saga-registers/intreq2.htm b/sources/official/saga-registers/intreq2.htm new file mode 100755 index 0000000..125621e --- /dev/null +++ b/sources/official/saga-registers/intreq2.htm @@ -0,0 +1,41 @@ + + +
+ +INTREQ2 + +This register contains interrupt request bits (or flags). These bits +may be polled by the processor, and if enabled by the bits listed in +the next register, they may cause processor interrupts. Both a set +and clear operation are required to load arbitrary data into this register. + + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 15 | | SET/CLR | + | 14 | | | + | 13 | ETH | Ethernet | + | 12 | | | + | 11 | AUD15 | Audio channel 15 block finished | + | 10 | AUD14 | Audio channel 14 block finished | + | 09 | AUD13 | Audio channel 13 block finished | + | 08 | AUD12 | Audio channel 12 block finished | + | 07 | AUD11 | Audio channel 11 block finished | + | 06 | AUD10 | Audio channel 10 block finished | + | 05 | AUD9 | Audio channel 9 block finished | + | 04 | AUD8 | Audio channel 8 block finished | + | 03 | AUD7 | Audio channel 7 block finished | + | 02 | AUD6 | Audio channel 6 block finished | + | 01 | AUD5 | Audio channel 5 block finished | + | 00 | AUD4 | Audio channel 4 block finished | + +-------+----------+-------------------------------------------+ + + +Ethernet will throw IRQ $48 +The new Audio channels will throw IRQ $50 + + ++ + diff --git a/sources/official/saga-registers/intreqr.htm b/sources/official/saga-registers/intreqr.htm new file mode 100755 index 0000000..9543534 --- /dev/null +++ b/sources/official/saga-registers/intreqr.htm @@ -0,0 +1,24 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +INTREQ 09C W P Interrupt request bits (clear or set) +INTREQR 01E R P Interrupt request bits (read) + + This register contains interrupt request bits (or + flags). These bits may be polled by the processor; + if enabled by the bits listed in the above register, + they may cause processor interrupts. Both a set and + clear operation are required to load arbitrary data + into this register. These status bits are not + automatically reset when the interrupt is serviced, + and must be reset when desired by writing to this + address. The bit assignments are identical to the + enable register . ++ + diff --git a/sources/official/saga-registers/joy0dat.htm b/sources/official/saga-registers/joy0dat.htm new file mode 100755 index 0000000..bfbe6b1 --- /dev/null +++ b/sources/official/saga-registers/joy0dat.htm @@ -0,0 +1,68 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +JOY0DAT 00A R D Joystick-mouse 0 data (left vertical, + horizontal) +JOY1DAT 00C R D Joystick-mouse 1 data (right vertical, + horizontal) + + These addresses each read a pair of 8-bit mouse + counters. 0=left controller pair, 1=right + controller pair (four counters total). The bit + usage for both left and right addresses is shown + below. Each counter is clocked by signals from + two controller pins. Bits 1 and 0 of each counter + may be read to determine the state of these two + clock pins. This allows these pins to double as + joystick switch inputs. + + Mouse counter usage: + (pins 1,3=Yclock, pins 2,4=Xclock) + + BIT# 15,14,13,12,11,10,09,08 07,06,05,04,03,02,01,00 + ----------------------- ----------------------- + 0DAT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0 + 1DAT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0 + + The following table shows the mouse/joystick + connector pin usage. The pins (and their functions) + are sampled (multiplexed) into the DENISE chip + during the clock times shown in the table. + This table is for reference only and should + not be needed by the programmer. (Note that the + joystick functions are all "active low" at the + connector pins.) + + Sampled by DENISE + Conn Joystick Mouse ----------------- + Pin Function Function Pin Name Clock + ---- -------- -------- --- ---- ----- + L1 FORW* Y 38 M0V at CCK + L3 LEFT* YQ 38 M0V at CCK* + L2 BACK* X 9 M0H at CCK + L4 RIGH* XQ 9 M0H at CCK* + R1 FORW* Y 39 M1V at CCK + R3 LEFT* YQ 39 M1V at CCK* + R2 BACK* X 8 M1H at CCK + R4 RIGH* XQ 8 M1H at CCK* + + After being sampled, these connector pin signals + are used in quadrature to clock the mouse counters. + The LEFT and RIGHT joystick functions (active high) + are directly available on the Y1 and X1 bits of + each counter. In order to recreate the FORWARD + and BACK joystick functions, however, it is + necessary to logically combine (exclusive OR) + the lower two bits of each counter. + This is illustrated in the following table. + + To detect Read these counter bits + -------- ---------------- ++ + \ No newline at end of file diff --git a/sources/official/saga-registers/joybuttons.htm b/sources/official/saga-registers/joybuttons.htm new file mode 100755 index 0000000..1aca107 --- /dev/null +++ b/sources/official/saga-registers/joybuttons.htm @@ -0,0 +1,32 @@ + + +
+ +JOYBUTTONS + + This register contains extra fire buttons (USB joyspads) + + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 15 | Right | Move RIGHT | + | 14 | Left | Move Left | + | 13 | Down | Move Down | + | 12 | Up | Move Up | + | 11 | Reserved| | + | 10 | Start | Start | + | 09 | Back | Back | + | 08 | FIRE8 | Firebutton 8 | + | 07 | FIRE7 | Firebutton 7 | + | 06 | FIRE6 | Firebutton 6 | + | 05 | FIRE5 | Firebutton 5 | + | 04 | FIRE4 | Firebutton 4 | + | 03 | FIRE3 | Firebutton 3 | + | 02 | FIRE2 | Firebutton 2 | + | 01 | FIRE1 | Firebutton 1 | + | 00 | PLUG | Joypad connected | + +-------+----------+-------------------------------------------+ ++ + diff --git a/sources/official/saga-registers/joytest.htm b/sources/official/saga-registers/joytest.htm new file mode 100755 index 0000000..4b7e4d7 --- /dev/null +++ b/sources/official/saga-registers/joytest.htm @@ -0,0 +1,20 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +JOYTEST 036 W D Write to all four joystick-mouse counters + at once. + + Mouse counter write test data: + + BIT# 15,14,13,12,11,10,09,08 07,06,05,04,03,02,01,00 + ----------------------- ----------------------- + 0DAT Y7 Y6 Y5 Y4 Y3 Y2 xx xx X7 X6 X5 X4 X3 X2 xx xx + 1DAT Y7 Y6 Y5 Y4 Y3 Y2 xx xx X7 X6 X5 X4 X3 X2 xx xx ++ + diff --git a/sources/official/saga-registers/mousewheel.htm b/sources/official/saga-registers/mousewheel.htm new file mode 100755 index 0000000..6052875 --- /dev/null +++ b/sources/official/saga-registers/mousewheel.htm @@ -0,0 +1,25 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +Wheel 212 R P( E ) Wheel events + + BIT 15-10 unused + BIT 9 Mouse Button 5 + BIT 8 Mouse Button 4 + + + signed 8 bit counter counts USB mouse Wheel events + + BIT# 07,06,05,04,03,02,01,00 + ----- ------------------------ ----------------------- + X7 X6 X5 X4 X3 X2 X1 X0 + + ++ + diff --git a/sources/official/saga-registers/pipcol.htm b/sources/official/saga-registers/pipcol.htm new file mode 100755 index 0000000..7d567ec --- /dev/null +++ b/sources/official/saga-registers/pipcol.htm @@ -0,0 +1,28 @@ + + +
+ +PIP COLOR PORT + + This register allows direct setting of 256 PIP colors registers + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 31-24 | index | 8bit Colornumber | + | 23-16 | RED | 8bit Red | + | 15-08 | GREEN | 8bit Green | + | 07-00 | BLUE | 8bit Blue | + +-------+----------+-------------------------------------------+ + +Example: + + move.l #$00FF0000,$DFF38C -- set color0 = RED + move.l #$01FFFF00,$DFF38C -- set color1 = YELLOW + +Copper: + dc.w $838C,$00FF,$0000 -- set color0 = RED + ++ + diff --git a/sources/official/saga-registers/planarcol.htm b/sources/official/saga-registers/planarcol.htm new file mode 100755 index 0000000..a05b84c --- /dev/null +++ b/sources/official/saga-registers/planarcol.htm @@ -0,0 +1,29 @@ + + +
+ +PLANAR COLOR PORT + + This register allows direct setting of 256 Planar colors registers + + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 31-24 | Number | 8bit Colornumber | + | 23-16 | RED | 8bit Red | + | 15-08 | GREEN | 8bit Green | + | 07-00 | BLUE | 8bit Blue | + +-------+----------+-------------------------------------------+ + +Example: + + move.l #$00FF0000,$DFF380 -- set color0 = RED + move.l #$01FFFF00,$DFF380 -- set color1 = YELLOW + +Copper: + dc.w $8380,$00FF,$0000 -- set color0 = RED + ++ + diff --git a/sources/official/saga-registers/pot0dat.htm b/sources/official/saga-registers/pot0dat.htm new file mode 100755 index 0000000..881dffa --- /dev/null +++ b/sources/official/saga-registers/pot0dat.htm @@ -0,0 +1,34 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +POT0DAT 012 R P( E ) Pot counter data left pair (vert,horiz.) +POT1DAT 014 R P( E ) Pot counter data right pair (vert,horiz.) + + These addresses each read a pair of 8-bit pot counters. + (Four counters total.) The bit assignment for both + addresses is shown below. The counters are stopped by + signals from two controller connectors (left-right) + with two pins each. + + BIT# 15,14,13,12,11,10,09,08 07,06,05,04,03,02,01,00 + ----- ------------------------ ----------------------- + RIGHT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0 + LEFT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0 + + CONNECTORS PAULA + -------------------- ---------------- + Loc. Dir. Sym Pin Pin# Pin Name + ---- --- ---- ---- ---- -------- + RIGHT Y RY 9 36 (POT1Y) + RIGHT X RX 5 35 (POT1X) + LEFT Y LY 9 33 (POT0Y) + LEFT X LX 5 32 (POT0X) + ++ + \ No newline at end of file diff --git a/sources/official/saga-registers/potgo.htm b/sources/official/saga-registers/potgo.htm new file mode 100755 index 0000000..3b08e84 --- /dev/null +++ b/sources/official/saga-registers/potgo.htm @@ -0,0 +1,38 @@ + + +
+ Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +POTGO 034 W P Pot port data write and start. + +POTGOR 016 R P Pot port data read + (formerly called POTINP). + + This register controls a 4-bit bi-directional I/O port + that shares the same four pins as the four pot counters + above. + + BIT# FUNCT DESCRIPTION + ---- --------------------------------------- + 15 OUTRY Output enable for Paula pin 36 + 14 DATRY I/O data Paula pin 36 + 13 OUTRX Output enable for Paula pin 35 + 12 DATRX I/O data Paula pin 35 + 11 OUTLY Output enable for Paula pin 33 + 10 DATLY I/O data Paula pin 33 + 09 OUTLX Output enable for Paula pin 32 + 08 DATLX I/O data Paula pin 32 + 07-01 0 Reserved for chip ID code (presently 0) + 00 START Start pots (dump capacitors, start + counters) + +Bit 14 = Firebutton 2 Joy2 +Bit 12 = Firebutton 3 Joy2 +Bit 10 = Firebutton 2 +Bit 8 = Firebutton 3 + ++ + diff --git a/sources/official/saga-registers/potinp.htm b/sources/official/saga-registers/potinp.htm new file mode 100755 index 0000000..3aa3167 --- /dev/null +++ b/sources/official/saga-registers/potinp.htm @@ -0,0 +1,33 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +POTGO 034 W P Pot port data write and start. + +POTGOR 016 R P Pot port data read + (formerly called POTINP). + + This register controls a 4-bit bi-directional I/O port + that shares the same four pins as the four pot counters + above. + + BIT# FUNCT DESCRIPTION + ---- --------------------------------------- + 15 OUTRY Output enable for Paula pin 36 + 14 DATRY I/O data Paula pin 36 + 13 OUTRX Output enable for Paula pin 35 + 12 DATRX I/O data Paula pin 35 + 11 OUTLY Output enable for Paula pin 33 + 10 DATLY I/O data Paula pin 33 + 09 OUTLX Output enable for Paula pin 32 + 08 DATLX I/O data Paula pin 32 + 07-01 0 Reserved for chip ID code (PAULA=0/ARNE=1) + 00 START Start pots (dump capacitors, start + counters) ++ + diff --git a/sources/official/saga-registers/refptr.htm b/sources/official/saga-registers/refptr.htm new file mode 100755 index 0000000..16c102a --- /dev/null +++ b/sources/official/saga-registers/refptr.htm @@ -0,0 +1,18 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +REFPTR 028 W A Refresh pointer + + This register is used as a dynamic RAM refresh + address generator. It is writeable for test + purposes only, and should never be written by + the microprocessor. ++ + + diff --git a/sources/official/saga-registers/saga.htm b/sources/official/saga-registers/saga.htm new file mode 100755 index 0000000..490993e --- /dev/null +++ b/sources/official/saga-registers/saga.htm @@ -0,0 +1,2139 @@ + + +
| Address | +Name | +Access | +OCS | ECS | AGA | SAGA | +Description | +
|---|---|---|---|---|---|---|---|
| DFF000 | +BLTDDAT | +ER | +* | * | * | * | +Blitter dest. early read (dummy address) | +
| DFF002 | +DMACONR | +R | +* | * | * | * | +Dma control (and blitter status) read | +
| DFF004 | +VPOSR | +R | +* | * | * | * | +Read vertical most sig. bits (and frame flop) | +
| DFF006 | +VHPOSR | +R | +* | * | * | * | +Read vert and horiz position of beam | +
| DFF008 | +DSKDATR | +ER | +* | * | * | * | +Disk data early read (dummy address) | +
| DFF00A | +JOY0DAT | +R | +* | * | * | * | +Joystick-mouse 0 data (vert, horiz) | +
| DFF00C | +JOY1DAT | +R | +* | * | * | * | +Joystick-mouse 1 data (vert, horiz) | +
| DFF00E | +CLXDAT | +R | +* | * | * | * | +Collision data reg. (read and clear) | +
| DFF010 | +ADKCONR | +R | +* | * | * | * | +Audio,disk control register read | +
| DFF012 | +POT0DAT | +R | +* | * | * | * | +Pot counter data left pair (vert, horiz) | +
| DFF014 | +POT1DAT | +R | +* | * | * | * | +Pot counter data right pair (vert, horiz) | +
| DFF016 | +POTINP | +R | +* | * | * | * | +Pot pin data read | +
| DFF018 | +SERDATR | +R | +* | * | * | * | +Serial port data and status read | +
| DFF01A | +DSKBYTR | +R | +* | * | * | * | +Disk data byte and status read | +
| DFF01C | +INTENAR | +R | +* | * | * | * | +Interrupt enable bits read | +
| DFF01E | +INTREQR | +R | +* | * | * | * | +Interrupt request bits read | +
| DFF020 | +DSKPTH | +W | +* | * | * | * | +Disk pointer (high 5 bits, was 3 bits) | +
| DFF022 | +DSKPTL | +W | +* | * | * | * | +Disk pointer (low 15 bits) | +
| DFF024 | +DSKLEN | +W | +* | +* | * | * | +Disk length | +
| DFF026 | +DSKDAT | +W | +* | * | * | * | +Disk DMA data write | +
| DFF028 | +REFPTR | +W | +* | * | * | * | +Refresh pointer | +
| DFF02A | +VPOSW | +W | +* | * | * | * | +Write vert most sig. bits (and frame flop) | +
| DFF02C | +VHPOSW | +W | +* | * | * | * | +Write vert and horiz pos of beam | +
| DFF02E | +COPCON | +W | +* | * | * | * | +Coprocessor control | +
| DFF030 | +SERDAT | +W | +* | * | * | * | +Serial port data and stop bits write | +
| DFF032 | +SERPER | +W | +* | * | * | * | +Serial port period and control | +
| DFF034 | +POTGO | +W | +* | * | * | * | +Pot count start,pot pin drive enable data | +
| DFF036 | +JOYTEST | +W | +* | * | * | * | +Write to all 4 joystick-mouse counters at once | +
| DFF038 | +STREQU | +S | +* | * | * | * | +Strobe for horiz sync with VB and EQU | +
| DFF03A | +STRVBL | +S | +* | * | * | * | +Strobe for horiz sync with VB (vert blank) | +
| DFF03C | +STRHOR | +S | +* | * | * | * | +Strobe for horiz sync | +
| DFF03E | +STRLONG | +S | +* | * | * | * | +Strobe for identification of long horiz line | +
| DFF040 | +BLTCON0 | +W | +* | * | * | * | +Blitter control register 0 | +
| DFF042 | +BLTCON1 | +W | +* | * | * | * | +Blitter control register 1 | +
| DFF044 | +BLTAFWM | +W | +* | * | * | * | +Blitter first word mask for source A | +
| DFF046 | +BLTALWM | +W | +* | * | * | * | +Blitter last word mask for source A | +
| DFF048 | +BLTCPTH | +W | +* | * | * | * | +Blitter pointer to source C (high 5 bits, was 3 bits) | +
| DFF04A | +BLTCPTL | +W | +* | * | * | * | +Blitter pointer to source C (low 15 bits) | +
| DFF04C | +BLTBPTH | +W | +* | * | * | * | +Blitter pointer to source B (high 5 bits, was 3 bits) | +
| DFF04E | +BLTBPTL | +W | +* | * | * | * | +Blitter pointer to source B (low 15 bits) | +
| DFF050 | +BLTAPTH | +W | +* | * | * | * | +Blitter pointer to source A (high 5 bits, was 3 bits) | +
| DFF052 | +BLTAPTL | +W | +* | * | * | * | +Blitter pointer to source A (low 15 bits) | +
| DFF054 | +BLTDPTH | +W | +* | * | * | * | +Blitter pointer to dest D (high 5 bits, was 3 bits) | +
| DFF056 | +BLTDPTL | +W | +* | * | * | * | +Blitter pointer to dest D (low 15 bits) | +
| DFF058 | +BLTSIZE | +W | +* | * | * | * | +Blitter start and size (win/width,height) | +
| DFF05A | +BLTCON0L | +W | +* | * | * | +Blitter control 0, lower 8 bits (minterms) | +|
| DFF05C | +BLTSIZV | +W | +* | * | * | +Blitter V size (for 15 bit vertical size) | +|
| DFF05E | +BLTSIZH | +W | +* | * | * | +Blitter H size and start (for 11 bit H size) | +|
| DFF060 | +BLTCMOD | +W | +* | * | * | * | +Blitter modulo for source C | +
| DFF062 | +BLTBMOD | +W | +* | * | * | * | +Blitter modulo for source B | +
| DFF064 | +BLTAMOD | +W | +* | * | * | * | +Blitter modulo for source A | +
| DFF066 | +BLTDMOD | +W | +* | * | * | * | +Blitter modulo for dest D | +
| DFF070 | +BLTCDAT | +W | +* | * | * | * | +Blitter source C data register | +
| DFF072 | +BLTBDAT | +W | +* | * | * | * | +Blitter source B data register | +
| DFF074 | +BLTADAT | +W | +* | * | * | * | +Blitter source A data register | +
| DFF078 | +SPRHDAT | +W | +* | * | * | +Ext. logic UHRES sprite pointer and data identifier | +|
| DFF07A | +BPLHDAT | +W | +* | * | * | +Ext. logic UHRES bit plane identifier | +|
| DFF07C | +DENISEID | +R | +* | * | * | +Chip revision level for Denise/Lisa (video out chip) | +|
| DFF07E | +DSKSYNC | +W | +* | * | * | * | +Disk sync pattern reg for disk read | +
| DFF080 | +COP1LCH | +W | +* | * | * | * | +Coprocessor 1st location (high 5 bits,was 3 bits) | +
| DFF082 | +COP1LCL | +W | +* | * | * | * | +Coprocessor 1st location (low 15 bits) | +
| DFF084 | +COP2LCH | +W | +* | * | * | * | +Coprocessor 2nd location(high 5 bits,was 3 bits) | +
| DFF086 | +COP2LCL | +W | +* | * | * | * | +Coprocessor 2nd location (low 15 bits) | +
| DFF088 | +COPJMP1 | +S | +* | * | * | * | +Coprocessor restart at 1st location | +
| DFF08A | +COPJMP2 | +S | +* | * | * | * | +Coprocessor restart at 2nd location | +
| DFF08C | +COPINS | +S | +* | * | * | * | +Coprocessor inst fetch identify | +
| DFF08E | +DIWSTRT | +W | +* | * | * | * | +Display window start (upper left vert,horiz pos) | +
| DFF090 | +DIWSTOP | +W | +* | * | * | * | +Display window stop (lower right vert,horiz pos) | +
| DFF092 | +DDFSTRT | +W | +* | * | * | * | +Display bit plane data fetch start,horiz pos | +
| DFF094 | +DDFSTOP | +W | +* | * | * | * | +Display bit plane data fetch stop,horiz pos | +
| DFF096 | +DMACON | +W | +* | * | * | * | +DMA control write (clear or set) | +
| DFF098 | +CLXCON | +W | +* | * | * | * | +Collision control | +
| DFF09A | +INTENA | +W | +* | * | * | * | +Interrupt enable bits (clear or set bits) | +
| DFF09C | +INTREQ | +W | +* | * | * | * | +Interrupt request bits (clear or set bits) | +
| DFF09E | +ADKCON | +W | +* | * | * | * | +Audio,disk,UART control | +
| DFF0A0 | +AUD0LCH | +W | +* | * | * | * | +Audio channel 0 location (high 5 bits was 3 bits) | +
| DFF0A2 | +AUD0LCL | +W | +* | * | * | * | +Audio channel 0 location (low 15 bits) | +
| DFF0A4 | +AUD0LEN | +W | +* | * | * | * | +Audio channel 0 length | +
| DFF0A6 | +AUD0PER | +W | +* | * | * | * | +Audio channel 0 period | +
| DFF0A8 | +AUD0VOL | +W | +* | * | * | * | +Audio channel 0 volume | +
| DFF0AA | +AUD0DAT | +W | +* | * | * | * | +Audio channel 0 data | +
| DFF0AC | +AUD0VOL2 | +W | +* | +Audio channel 0 volume far side | +|||
| DFF0AE | +AUD0LENHI | +W | +* | +Audio channel 0 length high bits | +|||
| DFF0B0 | +AUD1LCH | +W | +* | * | * | * | +Audio channel 1 location (high 5 bits was 3 bits) | +
| DFF0B2 | +AUD1LCL | +W | +* | * | * | * | +Audio channel 1 location (low 15 bits) | +
| DFF0B4 | +AUD1LEN | +W | +* | * | * | * | +Audio channel 1 length | +
| DFF0B6 | +AUD1PER | +W | +* | * | * | * | +Audio channel 1 period | +
| DFF0B8 | +AUD1VOL | +W | +* | * | * | * | +Audio channel 1 volume | +
| DFF0BA | +AUD1DAT | +W | +* | * | * | * | +Audio channel 1 data | +
| DFF0BC | +AUD1VOL2 | +W | +* | +Audio channel 1 volume far side | +|||
| DFF0BE | +AUD1LENHI | +W | +* | +Audio channel 1 length high bits | +|||
| DFF0C0 | +AUD2LCH | +W | +* | * | * | * | +Audio channel 2 location (high 5 bits was 3 bits) | +
| DFF0C2 | +AUD2LCL | +W | +* | * | * | * | +Audio channel 2 location (low 15 bits) | +
| DFF0C4 | +AUD2LEN | +W | +* | * | * | * | +Audio channel 2 length | +
| DFF0C6 | +AUD2PER | +W | +* | * | * | * | +Audio channel 2 period | +
| DFF0C8 | +AUD2VOL | +W | +* | * | * | * | +Audio channel 2 volume | +
| DFF0CA | +AUD2DAT | +W | +* | * | * | * | +Audio channel 2 data | +
| DFF0CC | +AUD2VOL2 | +W | +* | +Audio channel 2 volume far side | +|||
| DFF0CE | +AUD2LENHI | +W | +* | +Audio channel 2 length high bits | +|||
| DFF0D0 | +AUD3LCH | +W | +* | * | * | * | +Audio channel 3 location (high 5 bits was 3 bits) | +
| DFF0D2 | +AUD3LCL | +W | +* | * | * | * | +Audio channel 3 location (low 15 bits) | +
| DFF0D4 | +AUD3LEN | +W | +* | * | * | * | +Audio channel 3 length | +
| DFF0D6 | +AUD3PER | +W | +* | * | * | * | +Audio channel 3 period | +
| DFF0D8 | +AUD3VOL | +W | +* | * | * | * | +Audio channel 3 volume | +
| DFF0DA | +AUD3DAT | +W | +* | * | * | * | +Audio channel 3 data | +
| DFF0DC | +AUD3VOL2 | +W | +* | +Audio channel 3 volume far side | +|||
| DFF0DE | +AUD3LENHI | +W | +* | +Audio channel 3 length high bits | +|||
| DFF0E0 | +BPL1PTH | +W | +* | * | * | * | +Bitplane pointer 1 (high 5 bits was 3 bits) | +
| DFF0E2 | +BPL1PTL | +W | +* | * | * | * | +Bitplane pointer 1 (low 15 bits) | +
| DFF0E4 | +BPL2PTH | +W | +* | * | * | * | +Bitplane pointer 2 (high 5 bits was 3 bits) | +
| DFF0E6 | +BPL2PTL | +W | +* | * | * | * | +Bitplane pointer 2 (low 15 bits) | +
| DFF0E8 | +BPL3PTH | +W | +* | * | * | * | +Bitplane pointer 3 (high 5 bits was 3 bits) | +
| DFF0EA | +BPL3PTL | +W | +* | * | * | * | +Bitplane pointer 3 (low 15 bits) | +
| DFF0EC | +BPL4PTH | +W | +* | * | * | * | +Bitplane pointer 4 (high 5 bits was 3 bits) | +
| DFF0EE | +BPL4PTL | +W | +* | * | * | * | +Bitplane pointer 4 (low 15 bits) | +
| DFF0F0 | +BPL5PTH | +W | +* | * | * | * | +Bitplane pointer 5 (high 5 bits was 3 bits) | +
| DFF0F2 | +BPL5PTL | +W | +* | * | * | * | +Bitplane pointer 5 (low 15 bits) | +
| DFF0F4 | +BPL6PTH | +W | +* | * | * | * | +Bitplane pointer 6 (high 5 bits was 3 bits) | +
| DFF0F6 | +BPL6PTL | +W | +* | * | * | * | +Bitplane pointer 6 (low 15 bits) | +
| DFF0F8 | +BPL7PTH | +W | +* | * | +Bitplane pointer 7 (high 5 bits was 3 bits) | +||
| DFF0FA | +BPL7PTL | +W | +* | * | +Bitplane pointer 7 (low 15 bits) | +||
| DFF0FC | +BPL8PTH | +W | +* | * | +Bitplane pointer 8 (high 5 bits was 3 bits) | +||
| DFF0FE | +BPL8PTL | +W | +* | * | +Bitplane pointer 8 (low 15 bits) | +||
| DFF100 | +BPLCON0 | +W | +* | * | * | * | +Bitplane control (miscellaneous control bits) | +
| DFF102 | +BPLCON1 | +W | +* | * | * | * | +Bitplane control (scroll value) | +
| DFF104 | +BPLCON2 | +W | +* | * | * | * | +Bitplane control (video priority control) | +
| DFF106 | +BPLCON3 | +W | +* | * | * | * | +Bitplane control (enhanced features) | +
| DFF108 | +BPL1MOD | +W | +* | * | * | * | +Bitplane modulo (odd planes) | +
| DFF10A | +BPL2MOD | +W | +* | * | * | * | +Bitplane modulo (even planes) | +
| DFF10C | +BPLCON4 | +W | +* | * | +Bitplane control (bitplane and sprite-masks) | +||
| DFF10E | +CLXCON2 | +W | +* | * | +Extended collision control | +||
| DFF110 | +BPL1DAT | +W | +* | * | * | * | +Bitplane 1 data (parallel to serial convert) | +
| DFF112 | +BPL2DAT | +W | +* | * | * | * | +Bitplane 2 data (parallel to serial convert) | +
| DFF114 | +BPL3DAT | +W | +* | * | * | * | +Bitplane 3 data (parallel to serial convert) | +
| DFF116 | +BPL4DAT | +W | +* | * | * | * | +Bitplane 4 data (parallel to serial convert) | +
| DFF118 | +BPL5DAT | +W | +* | * | * | * | +Bitplane 5 data (parallel to serial convert) | +
| DFF11A | +BPL6DAT | +W | +* | * | * | * | +Bitplane 6 data (parallel to serial convert) | +
| DFF11C | +BPL7DAT | +W | +* | * | +Bitplane 7 data (parallel to serial convert) | +||
| DFF11E | +BPL8DAT | +W | +* | * | +Bitplane 8 data (parallel to serial convert) | +||
| DFF120 | +SPR0PTH | +W | +* | * | * | * | +Sprite 0 pointer (high 5 bits was 3 bits) | +
| DFF122 | +SPR0PTL | +W | +* | * | * | * | +Sprite 0 pointer (low 15 bits) | +
| DFF124 | +SPR1PTH | +W | +* | * | * | * | +Sprite 1 pointer (high 5 bits was 3 bits) | +
| DFF126 | +SPR1PTL | +W | +* | * | * | * | +Sprite 1 pointer (low 15 bits) | +
| DFF128 | +SPR2PTH | +W | +* | * | * | * | +Sprite 2 pointer (high 5 bits was 3 bits) | +
| DFF12A | +SPR2PTL | +W | +* | * | * | * | +Sprite 2 pointer (low 15 bits) | +
| DFF12C | +SPR3PTH | +W | +* | * | * | * | +Sprite 3 pointer (high 5 bits was 3 bits) | +
| DFF12E | +SPR3PTL | +W | +* | * | * | * | +Sprite 3 pointer (low 15 bits) | +
| DFF130 | +SPR4PTH | +W | +* | * | * | * | +Sprite 4 pointer (high 5 bits was 3 bits) | +
| DFF132 | +SPR4PTL | +W | +* | * | * | * | +Sprite 4 pointer (low 15 bits) | +
| DFF134 | +SPR5PTH | +W | +* | * | * | * | +Sprite 5 pointer (high 5 bits was 3 bits) | +
| DFF136 | +SPR5PTL | +W | +* | * | * | * | +Sprite 5 pointer (low 15 bits) | +
| DFF138 | +SPR6PTH | +W | +* | * | * | * | +Sprite 6 pointer (high 5 bits was 3 bits) | +
| DFF13A | +SPR6PTL | +W | +* | * | * | * | +Sprite 6 pointer (low 15 bits) | +
| DFF13C | +SPR7PTH | +W | +* | * | * | * | +Sprite 7 pointer (high 5 bits was 3 bits) | +
| DFF13E | +SPR7PTL | +W | +* | * | * | * | +Sprite 7 pointer (low 15 bits) | +
| DFF140 | +SPR0POS | +W | +* | * | * | * | +Sprite 0 vert,horiz start pos data | +
| DFF142 | +SPR0CTL | +W | +* | * | * | * | +Sprite 0 position and control data | +
| DFF144 | +SPR0DATA | +W | +* | * | * | * | +Sprite 0 image data register A | +
| DFF146 | +SPR0DATB | +W | +* | * | * | * | +Sprite 0 image data register B | +
| DFF148 | +SPR1POS | +W | +* | * | * | * | +Sprite 1 vert,horiz start pos data | +
| DFF14A | +SPR1CTL | +W | +* | * | * | * | +Sprite 1 position and control data | +
| DFF14C | +SPR1DATA | +W | +* | * | * | * | +Sprite 1 image data register A | +
| DFF14E | +SPR1DATB | +W | +* | * | * | * | +Sprite 1 image data register B | +
| DFF150 | +SPR2POS | +W | +* | * | * | * | +Sprite 2 vert,horiz start pos data | +
| DFF152 | +SPR2CTL | +W | +* | * | * | * | +Sprite 2 position and control data | +
| DFF154 | +SPR2DATA | +W | +* | * | * | * | +Sprite 2 image data register A | +
| DFF156 | +SPR2DATB | +W | +* | * | * | * | +Sprite 2 image data register B | +
| DFF158 | +SPR3POS | +W | +* | * | * | * | +Sprite 3 vert,horiz start pos data | +
| DFF15A | +SPR3CTL | +W | +* | * | * | * | +Sprite 3 position and control data | +
| DFF15C | +SPR3DATA | +W | +* | * | * | * | +Sprite 3 image data register A | +
| DFF15E | +SPR3DATB | +W | +* | * | * | * | +Sprite 3 image data register B | +
| DFF160 | +SPR4POS | +W | +* | * | * | * | +Sprite 4 vert,horiz start pos data | +
| DFF162 | +SPR4CTL | +W | +* | * | * | * | +Sprite 4 position and control data | +
| DFF164 | +SPR4DATA | +W | +* | * | * | * | +Sprite 4 image data register A | +
| DFF166 | +SPR4DATB | +W | +* | * | * | * | +Sprite 4 image data register B | +
| DFF168 | +SPR5POS | +W | +* | * | * | * | +Sprite 5 vert,horiz start pos data | +
| DFF16A | +SPR5CTL | +W | +* | * | * | * | +Sprite 5 position and control data | +
| DFF16C | +SPR5DATA | +W | +* | * | * | * | +Sprite 5 image data register A | +
| DFF16E | +SPR5DATB | +W | +* | * | * | * | +Sprite 5 image data register B | +
| DFF170 | +SPR6POS | +W | +* | * | * | * | +Sprite 6 vert,horiz start pos data | +
| DFF172 | +SPR6CTL | +W | +* | * | * | * | +Sprite 6 position and control data | +
| DFF174 | +SPR6DATA | +W | +* | * | * | * | +Sprite 6 image data register A | +
| DFF176 | +SPR6DATB | +W | +* | * | * | * | +Sprite 6 image data register B | +
| DFF178 | +SPR7POS | +W | +* | * | * | * | +Sprite 7 vert,horiz start pos data | +
| DFF17A | +SPR7CTL | +W | +* | * | * | * | +Sprite 7 position and control data | +
| DFF17C | +SPR7DATA | +W | +* | * | * | * | +Sprite 7 image data register A | +
| DFF17E | +SPR7DATB | +W | +* | * | * | * | +Sprite 7 image data register B | +
| DFF180 | +COLOR00 | +W | +* | * | * | * | +Color table 0 | +
| DFF182 | +COLOR01 | +W | +* | * | * | * | +Color table 1 | +
| DFF184 | +COLOR02 | +W | +* | * | * | * | +Color table 2 | +
| DFF186 | +COLOR03 | +W | +* | * | * | * | +Color table 3 | +
| DFF188 | +COLOR04 | +W | +* | * | * | * | +Color table 4 | +
| DFF18A | +COLOR05 | +W | +* | * | * | * | +Color table 5 | +
| DFF18C | +COLOR06 | +W | +* | * | * | * | +Color table 6 | +
| DFF18E | +COLOR07 | +W | +* | * | * | * | +Color table 7 | +
| DFF190 | +COLOR08 | +W | +* | * | * | * | +Color table 8 | +
| DFF192 | +COLOR09 | +W | +* | * | * | * | +Color table 9 | +
| DFF194 | +COLOR10 | +W | +* | * | * | * | +Color table 10 | +
| DFF196 | +COLOR11 | +W | +* | * | * | * | +Color table 11 | +
| DFF198 | +COLOR12 | +W | +* | * | * | * | +Color table 12 | +
| DFF19A | +COLOR13 | +W | +* | * | * | * | +Color table 13 | +
| DFF19C | +COLOR14 | +W | +* | * | * | * | +Color table 14 | +
| DFF19E | +COLOR15 | +W | +* | * | * | * | +Color table 15 | +
| DFF1A0 | +COLOR16 | +W | +* | * | * | * | +Color table 16 | +
| DFF1A2 | +COLOR17 | +W | +* | * | * | * | +Color table 17 | +
| DFF1A4 | +COLOR18 | +W | +* | * | * | * | +Color table 18 | +
| DFF1A6 | +COLOR19 | +W | +* | * | * | * | +Color table 19 | +
| DFF1A8 | +COLOR20 | +W | +* | * | * | * | +Color table 20 | +
| DFF1AA | +COLOR21 | +W | +* | * | * | * | +Color table 21 | +
| DFF1AC | +COLOR22 | +W | +* | * | * | * | +Color table 22 | +
| DFF1AE | +COLOR23 | +W | +* | * | * | * | +Color table 23 | +
| DFF1B0 | +COLOR24 | +W | +* | * | * | * | +Color table 24 | +
| DFF1B2 | +COLOR25 | +W | +* | * | * | * | +Color table 25 | +
| DFF1B4 | +COLOR26 | +W | +* | * | * | * | +Color table 26 | +
| DFF1B6 | +COLOR27 | +W | +* | * | * | * | +Color table 27 | +
| DFF1B8 | +COLOR28 | +W | +* | * | * | * | +Color table 28 | +
| DFF1BA | +COLOR29 | +W | +* | * | * | * | +Color table 29 | +
| DFF1BC | +COLOR30 | +W | +* | * | * | * | +Color table 30 | +
| DFF1BE | +COLOR31 | +W | +* | * | * | * | +Color table 31 | +
| DFF1C0 | +HTOTAL | +W | +* | * | * | +Highest number count, horiz line (VARBEAMEN=1) | +|
| DFF1C2 | +HSSTOP | +W | +* | * | * | +Horizontal line position for HSYNC stop | +|
| DFF1C4 | +HBSTRT | +W | +* | * | * | +Horizontal line position for HBLANK start | +|
| DFF1C6 | +HBSTOP | +W | +* | * | * | +Horizontal line position for HBLANK stop | +|
| DFF1C8 | +VTOTAL | +W | +* | * | * | +Highest numbered vertical line (VARBEAMEN=1) | +|
| DFF1CA | +VSSTOP | +W | +* | * | * | +Vertical line position for VSYNC stop | +|
| DFF1CC | +VBSTRT | +W | +* | * | * | +Vertical line for VBLANK start | +|
| DFF1CE | +VBSTOP | +W | +* | * | * | +Vertical line for VBLANK stop | +|
| DFF1D0 | +SPRHSTRT | +W | +* | * | * | +UHRES sprite vertical start | +|
| DFF1D2 | +SPRHSTOP | +W | +* | * | * | +UHRES sprite vertical stop | +|
| DFF1D4 | +BPLHSTRT | +W | +* | * | * | +UHRES bit plane vertical start | +|
| DFF1D6 | +BPLHSTOP | +W | +* | * | * | +UHRES bit plane vertical stop | +|
| DFF1D8 | +HHPOSW | +W | +* | * | * | +DUAL mode hires H beam counter write | +|
| DFF1DA | +HHPOSR | +R | +* | * | * | +DUAL mode hires H beam counter read | +|
| DFF1DC | +BEAMCON0 | +W | +* | * | * | * | +Beam counter control register (SHRES,UHRES,PAL) | +
| DFF1DE | +HSSTRT | +W | +* | * | * | +Horizontal sync start (VARHSY) | +|
| DFF1E0 | +VSSTRT | +W | +* | * | * | +Vertical sync start (VARVSY) | +|
| DFF1E2 | +HCENTER | +W | +* | * | * | +Horizontal position for Vsync on interlace | +|
| DFF1E4 | +DIWHIGH | +W | +* | * | * | +Display window - upper bits for start/stop | +|
| DFF1E6 | +BPLHMOD | +W | +* | +Chunky plane modulo | +|||
| DFF1E8 | +SPRHPTH | +W | +* | * | * | +UHRES sprite pointer (high 5 bits) | +|
| DFF1EA | +SPRHPTL | +W | +* | * | * | +UHRES sprite pointer (low 15 bits) | +|
| DFF1EC | +BPLHPTH | +W | +* | +Chunky plane pointer (hi 15 bits) | +|||
| DFF1EE | +BPLHPTL | +W | +* | +Chunky plane pointer (lo 15 bits) | +|||
| DFF1FC | +FMODE | +W | +* | * | +Fetch mode register | +||
| Address | +Name | +Access | +OCS | ECS | AGA | SAGA | +Description | +
| DFF230 | +clxdat0 | +R | +* | +Sprite0 Detailed Collision | +|||
| DFF232 | +clxdat1 | +R | +* | +Sprite1 Detailed Collision | +|||
| DFF234 | +clxdat2 | +R | +* | +Sprite2 Detailed Collision | +|||
| DFF236 | +clxdat3 | +R | +* | +Sprite3 Detailed Collision | +|||
| DFF29E | +ADKCON2 | +W | +* | * | * | * | +Audio,disk,UART control | +
| DFF2A0 | +AUD4LCH | +W | +* | +Audio channel 4 location (high 5 bits was 3 bits) | +|||
| DFF2A2 | +AUD4LCL | +W | +* | +Audio channel 4 location (low 15 bits) | +|||
| DFF2A4 | +AUD4LEN | +W | +* | +Audio channel 4 length | +|||
| DFF2A6 | +AUD4PER | +W | +* | +Audio channel 4 period | +|||
| DFF2A8 | +AUD4VOL | +W | +* | +Audio channel 4 volume | +|||
| DFF2AA | +AUD4DAT | +W | +* | +Audio channel 4 data | +|||
| DFF2AC | +AUD4VOL2 | +W | +* | +Audio channel 4 volume far side | +|||
| DFF2AE | +AUD4LENHI | +W | +* | +Audio channel 4 length high bits | +|||
| DFF2B0 | +AUD5LCH | +W | +* | +Audio channel 5 location (high 5 bits was 3 bits) | +|||
| DFF2B2 | +AUD5LCL | +W | +* | +Audio channel 5 location (low 15 bits) | +|||
| DFF2B4 | +AUD5LEN | +W | +* | +Audio channel 5 length | +|||
| DFF2B6 | +AUD5PER | +W | +* | +Audio channel 5 period | +|||
| DFF2B8 | +AUD5VOL | +W | +* | +Audio channel 5 volume | +|||
| DFF2BA | +AUD5DAT | +W | +* | +Audio channel 5 data | +|||
| DFF2BC | +AUD5VOL2 | +W | +* | +Audio channel 1 volume far side | +|||
| DFF2BE | +AUD5LENHI | +W | +* | +Audio channel 5 length high bits | +|||
| DFF2C0 | +AUD6LCH | +W | +* | +Audio channel 6 location (high 5 bits was 3 bits) | +|||
| DFF2C2 | +AUD6LCL | +W | +* | +Audio channel 6 location (low 15 bits) | +|||
| DFF2C4 | +AUD6LEN | +W | +* | +Audio channel 6 length | +|||
| DFF2C6 | +AUD6PER | +W | +* | +Audio channel 6 period | +|||
| DFF2C8 | +AUD6VOL | +W | +* | +Audio channel 6 volume | +|||
| DFF2CA | +AUD6DAT | +W | +* | +Audio channel 6 data | +|||
| DFF2CC | +AUD6VOL2 | +W | +* | +Audio channel 6 volume far side | +|||
| DFF2CE | +AUD6LENHI | +W | +* | +Audio channel 6 length high bits | +|||
| DFF2D0 | +AUD7LCH | +W | +* | +Audio channel 7 location (high 5 bits was 3 bits) | +|||
| DFF2D2 | +AUD7LCL | +W | +* | +Audio channel 7 location (low 15 bits) | +|||
| DFF2D4 | +AUD7LEN | +W | +* | +Audio channel 7 length | +|||
| DFF2D6 | +AUD7PER | +W | +* | +Audio channel 7 period | +|||
| DFF2D8 | +AUD7VOL | +W | +* | +Audio channel 7 volume | +|||
| DFF2DA | +AUD7DAT | +W | +* | +Audio channel 7 data | +|||
| DFF2DC | +AUD7VOL2 | +W | +* | +Audio channel 7 volume far side | +|||
| DFF2DE | +AUD7LENHI | +W | +* | +Audio channel 7 length high bits | +|||
| DFF320 | +SPR8PTH | +W | +* | +Sprite 8 pointer (high 5 bits was 3 bits) | +|||
| DFF322 | +SPR8PTL | +W | +* | +Sprite 8 pointer (low 15 bits) | +|||
| DFF324 | +SPR9PTH | +W | +* | +Sprite 9 pointer (high 5 bits was 3 bits) | +|||
| DFF326 | +SPR9PTL | +W | +* | +Sprite 9 pointer (low 15 bits) | +|||
| DFF328 | +SPR10PTH | +W | +* | +Sprite 10 pointer (high 5 bits was 3 bits) | +|||
| DFF32A | +SPR10PTL | +W | +* | +Sprite 10 pointer (low 15 bits) | +|||
| DFF32C | +SPR11PTH | +W | +* | +Sprite 11 pointer (high 5 bits was 3 bits) | +|||
| DFF32E | +SPR11PTL | +W | +* | +Sprite 11 pointer (low 15 bits) | +|||
| DFF330 | +SPR12PTH | +W | +* | +Sprite 12 pointer (high 5 bits was 3 bits) | +|||
| DFF332 | +SPR12PTL | +W | +* | +Sprite 12 pointer (low 15 bits) | +|||
| DFF334 | +SPR13PTH | +W | +* | +Sprite 13 pointer (high 5 bits was 3 bits) | +|||
| DFF336 | +SPR13PTL | +W | +* | +Sprite 13 pointer (low 15 bits) | +|||
| DFF338 | +SPR14PTH | +W | +* | +Sprite 14 pointer (high 5 bits was 3 bits) | +|||
| DFF33A | +SPR14PTL | +W | +* | +Sprite 14 pointer (low 15 bits) | +|||
| DFF33C | +SPR15PTH | +W | +* | +Sprite 15 pointer (high 5 bits was 3 bits) | +|||
| DFF33E | +SPR15PTL | +W | +* | +Sprite 15 pointer (low 15 bits) | +|||
+ +SAGA CONTROL Register + + + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 15 | SET/CLR | | + | 6 | FORCE OCS MODE | | + | 5 | Enable PAL ZOOM | | + | 4 | -- | | + | 3 | -- | | + | 2 | Enable Zoom | | + | 1 | Scanline Mode | | + | 0 | Scanlines On/Off | | + +-------+----------+-------------------------------------------+ ++Examples: + +No Zoom = apoke $DFF3EC 2 $0024
+ +SCREEN ADJUST PORT + + This register allows adjusting the SAGA screenmodes + + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 31-24 | Number | 8bit Screenmode-ID | + | 23-16 | -- | 8bit 00 reserved | + | 15-08 | -Y | 8bit 0Y more rows | + | 07-00 | -X | 8bit 0X more widthX | + +-------+----------+-------------------------------------------+ + +Example: + + move.l #$00FF0000,$DFF380 -- set color0 = RED + move.l #$01FFFF00,$DFF380 -- set color1 = YELLOW + +Copper: + dc.w $8380,$00FF,$0000 -- set color0 = RED + ++ + diff --git a/sources/official/saga-registers/serdat.htm b/sources/official/saga-registers/serdat.htm new file mode 100755 index 0000000..f8cba48 --- /dev/null +++ b/sources/official/saga-registers/serdat.htm @@ -0,0 +1,64 @@ + + +
+ Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +SERDAT 030 W P Serial port data and stop bits write + (transmit data buffer) + + This address writes data to a transmit data buffer. + Data from this buffer is moved into a serial shift + register for output transmission whenever it is + empty. This sets the interrupt request TBE + (transmit buffer empty). A stop bit must be + provided as part of the data word. The length of + the data word is set by the position of the stop + bit. + + BIT# 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00 + ----------------------------------------------- + USE 0 0 0 0 0 0 S D8 D7 D6 D5 D4 D3 D2 D1 D0 + + Note: S = stop bit = 1, D = data bits. + +SERDATR 018 R P Serial port data and status read + (receive data buffer) + + This address reads data from a receive data buffer. + Data in this buffer is loaded from a receiving + shift register whenever it is full. Several + interrupt request bits are also read at this + address, along with the data, as shown below. + + BIT# SYM FUNCTION + ---- ---- ----------------------- + 15 OVRUN Serial port receiver overrun. + Reset by resetting bit 11 of + INTREQ . + 14 RBF Serial port receive buffer full + (mirror). + 13 TBE Serial port transmit buffer + empty (mirror). + 12 TSRE Serial port transmit shift + register empty. + Reset by loading into buffer. + 11 RXD RXD pin receives UART serial + data for direct bit test by + the microprocessor. + 10 0 Not used + 09 STP Stop bit + 08 STP-DB8 Stop bit if LONG, data bit if + not. + 07 DB7 Data bit + 06 DB6 Data bit + 05 DB5 Data bit + 04 DB4 Data bit + 03 DB3 Data bit + 02 DB2 Data bit + 01 DB1 Data bit + 00 DB0 Data bit ++ + diff --git a/sources/official/saga-registers/serdatr.htm b/sources/official/saga-registers/serdatr.htm new file mode 100755 index 0000000..94e404e --- /dev/null +++ b/sources/official/saga-registers/serdatr.htm @@ -0,0 +1,66 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +SERDAT 030 W P Serial port data and stop bits write + (transmit data buffer) + + This address writes data to a transmit data buffer. + Data from this buffer is moved into a serial shift + register for output transmission whenever it is + empty. This sets the interrupt request TBE + (transmit buffer empty). A stop bit must be + provided as part of the data word. The length of + the data word is set by the position of the stop + bit. + + BIT# 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00 + ----------------------------------------------- + USE 0 0 0 0 0 0 S D8 D7 D6 D5 D4 D3 D2 D1 D0 + + Note: S = stop bit = 1, D = data bits. + +SERDATR 018 R P Serial port data and status read + (receive data buffer) + + This address reads data from a receive data buffer. + Data in this buffer is loaded from a receiving + shift register whenever it is full. Several + interrupt request bits are also read at this + address, along with the data, as shown below. + + BIT# SYM FUNCTION + ---- ---- ----------------------- + 15 OVRUN Serial port receiver overrun. + Reset by resetting bit 11 of + INTREQ . + 14 RBF Serial port receive buffer full + (mirror). + 13 TBE Serial port transmit buffer + empty (mirror). + 12 TSRE Serial port transmit shift + register empty. + Reset by loading into buffer. + 11 RXD RXD pin receives UART serial + data for direct bit test by + the microprocessor. + 10 0 Not used + 09 STP Stop bit + 08 STP-DB8 Stop bit if LONG, data bit if + not. + 07 DB7 Data bit + 06 DB6 Data bit + 05 DB5 Data bit + 04 DB4 Data bit + 03 DB3 Data bit + 02 DB2 Data bit + 01 DB1 Data bit + 00 DB0 Data bit + ++ + \ No newline at end of file diff --git a/sources/official/saga-registers/serper.htm b/sources/official/saga-registers/serper.htm new file mode 100755 index 0000000..c8bb3e0 --- /dev/null +++ b/sources/official/saga-registers/serper.htm @@ -0,0 +1,22 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +SERPER 032 W P Serial port period and control + + This register contains the control bit LONG referred to + above, and a 15-bit number defining the serial port + baud rate. If this number is N, then the baud rate is + 1 bit every (N+1)*.2794 microseconds. + + BIT# SYM FUNCTION + ----- ---- --------------- + 15 LONG Defines serial receive as 9-bit word. + 14-00 RATE Defines baud rate=1/((N+1)*.2794 microsec.) ++ + diff --git a/sources/official/saga-registers/shiftdown.htm b/sources/official/saga-registers/shiftdown.htm new file mode 100755 index 0000000..66cf1c7 --- /dev/null +++ b/sources/official/saga-registers/shiftdown.htm @@ -0,0 +1,19 @@ + + +
+ +SAGA CONTROL Register + + + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 15 ..8 | Y shift | | + | 7..0 | X shift | | + +-------+----------+-------------------------------------------+ ++ + + + diff --git a/sources/official/saga-registers/spritecol.htm b/sources/official/saga-registers/spritecol.htm new file mode 100755 index 0000000..c978416 --- /dev/null +++ b/sources/official/saga-registers/spritecol.htm @@ -0,0 +1,29 @@ + + +
+ +SPRITE COLOR PORT + + This register allows direct setting of 256 Sprite colors + + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 31-24 | number | 8bit Colornumber | + | 23-16 | RED | 8bit Red | + | 15-08 | GREEN | 8bit Green | + | 07-00 | BLUE | 8bit Blue | + +-------+----------+-------------------------------------------+ + +Example: + + move.l #$00FF0000,$DFF384 -- set color0 = RED + move.l #$01FFFF00,$DFF384 -- set color1 = YELLOW + +Copper: + dc.w $8384,$00FF,$0000 -- set color0 = RED + ++ + diff --git a/sources/official/saga-registers/sprxctl.htm b/sources/official/saga-registers/sprxctl.htm new file mode 100755 index 0000000..85c245c --- /dev/null +++ b/sources/official/saga-registers/sprxctl.htm @@ -0,0 +1,40 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +SPRxCTL 142 W A D( E ) Sprite x vert stop position and + control data +SPRxPOS 140 W A D Sprite x vert-horiz start position data + + These two registers work together as position, size and + feature sprite-control registers. They are usually loaded + by the sprite DMA channel during horizontal blank; + however, they may be loaded by either processor at any + time. SPRxPOS register: + + BIT# SYM FUNCTION + ---- ---- ----------------------------- + 15-08 SV7-SV0 Start vertical value. High bit(SV8) is + in SPRxCTL register below. + 07-00 SH8-SH1 Start horizontal value. Low bit(SH0) is + in SPRxCTL register below. + + SPRxCTL register (writing this address disables sprite + horizontal comparator circuit): + + BIT# SYM FUNCTION + ---- -------- ----------------------------- + 15-08 EV7-EV0 End (stop) vertical value low 8 bits + 07 ATT Sprite attach control bit (odd sprites) + 06-04 X Not used + 02 SV8 Start vertical value high bit + 01 EV8 End (stop) vertical value high bit + 00 SH0 Start horizontal value low bit + ++ + diff --git a/sources/official/saga-registers/sprxdata.htm b/sources/official/saga-registers/sprxdata.htm new file mode 100755 index 0000000..0ea8a10 --- /dev/null +++ b/sources/official/saga-registers/sprxdata.htm @@ -0,0 +1,27 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +SPRxDATA 144 W D Sprite x image data register A +SPRxDATB 146 W D Sprite x image data register B + + These registers buffer the sprite image data. They are + usually loaded by the sprite DMA channel but may be + loaded by either processor at any time. When a + horizontal comparison occurs, the buffers are dumped + into shift registers and serially outputted to the + display, MSB first on the left. + + NOTE: Writing to the A buffer enables (arms) the sprite. + Writing to the SPRxCTL register disables the sprite. + If enabled, data in the A and B buffers will be outputted + whenever the beam counter equals the sprite horizontal + position value in the SPRxPOS register. + ++ + diff --git a/sources/official/saga-registers/sprxpos.htm b/sources/official/saga-registers/sprxpos.htm new file mode 100755 index 0000000..13b8bbb --- /dev/null +++ b/sources/official/saga-registers/sprxpos.htm @@ -0,0 +1,41 @@ + + +
+ + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +SPRxCTL 142 W A D( E ) Sprite x vert stop position and + control data +SPRxPOS 140 W A D Sprite x vert-horiz start position data + + These two registers work together as position, size and + feature sprite-control registers. They are usually loaded + by the sprite DMA channel during horizontal blank; + however, they may be loaded by either processor at any + time. SPRxPOS register: + + BIT# SYM FUNCTION + ---- ---- ----------------------------- + 15-08 SV7-SV0 Start vertical value. High bit(SV8) is + in SPRxCTL register below. + 07-00 SH8-SH1 Start horizontal value. Low bit(SH0) is + in SPRxCTL register below. + + SPRxCTL register (writing this address disables sprite + horizontal comparator circuit): + + BIT# SYM FUNCTION + ---- -------- ----------------------------- + 15-08 EV7-EV0 End (stop) vertical value low 8 bits + 07 ATT Sprite attach control bit (odd sprites) + 06-04 X Not used + 02 SV8 Start vertical value high bit + 01 EV8 End (stop) vertical value high bit + 00 SH0 Start horizontal value low bit + ++ + diff --git a/sources/official/saga-registers/sprxpth.htm b/sources/official/saga-registers/sprxpth.htm new file mode 100755 index 0000000..48df63b --- /dev/null +++ b/sources/official/saga-registers/sprxpth.htm @@ -0,0 +1,24 @@ + + +
+ + + + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +SPRxPTH 120 W A Sprite x pointer (high 3 bits) +SPRxPTL 122 W A Sprite x pointer (low 15 bits) + + This pair of registers contains the 18-bit address + of sprite x (x=0,1,2,3,4,5,6,7) DMA data. These address + registers must be initialized by the processor or Copper + every vertical blank time. + + + ++ + diff --git a/sources/official/saga-registers/strequ.htm b/sources/official/saga-registers/strequ.htm new file mode 100755 index 0000000..b4a5843 --- /dev/null +++ b/sources/official/saga-registers/strequ.htm @@ -0,0 +1,28 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +STREQU 038 S D Strobe for horizontal sync with VB + and EQU +STRHOR 03C S D P Strobe for horizontal sync +STRLONG 03E S D( E ) Strobe for identification of long + horizontal line + + One of the first three strobe addresses above is + placed on the destination address bus during the + first refresh time slot. The fourth strobe shown + above is used during the second refresh time slot of + every other line to identify lines with long counts + (228). There are four refresh time slots, and any + not used for strobes will leave a null (FF) address + on the destination address bus. + +STRVBL 03A S D Strobe for horizontal sync with VB + (vertical blank) ++ + diff --git a/sources/official/saga-registers/vampversion.htm b/sources/official/saga-registers/vampversion.htm new file mode 100755 index 0000000..e76c529 --- /dev/null +++ b/sources/official/saga-registers/vampversion.htm @@ -0,0 +1,19 @@ + + +
+ +VAMP VERSION + + This register card version and CPU Clockrate + + + +-------+----------+-------------------------------------------+ + | BIT# | FUNCTION | DESCRIPTION | + +-------+----------+-------------------------------------------+ + | 15-08 | Card | Card Version | + | | | 1=V600, 2=V500, 3=V4_500(Firebird=500/Salamander=2000/Phoenix=1000), 4=V4_1200(Icedrake), 5=V4SA, 6=V1200, 7=V4_600(Manticore) | + | 07-00 | Clock | Clock multiplier | + +-------+----------+-------------------------------------------+ ++ + diff --git a/sources/official/saga-registers/vbstrt.htm b/sources/official/saga-registers/vbstrt.htm new file mode 100755 index 0000000..8dbbd7e --- /dev/null +++ b/sources/official/saga-registers/vbstrt.htm @@ -0,0 +1,17 @@ + + +
+ + + + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +VBSTOP 1CE W A( E ) Vertical line for VBLANK stop +VBSTRT 1CC W A( E ) Vertical line for VBLANK start + ++ + diff --git a/sources/official/saga-registers/vhposr.htm b/sources/official/saga-registers/vhposr.htm new file mode 100755 index 0000000..637ca16 --- /dev/null +++ b/sources/official/saga-registers/vhposr.htm @@ -0,0 +1,22 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +VHPOSR 006 R A Read vertical and horizontal position of + beam or lightpen +VHPOSW 02C W A Write vertical and horizontal position + of beam or lightpen + + BIT# 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00 + ----------------------------------------------- + USE V7 V6 V5 V4 V3 V2 V1 V0,H8 H7 H6 H5 H4 H3 H2 H1 + + RESOLUTION = 1/160 of screen width (280 ns) + ++ + diff --git a/sources/official/saga-registers/vposr.htm b/sources/official/saga-registers/vposr.htm new file mode 100755 index 0000000..4b5f49a --- /dev/null +++ b/sources/official/saga-registers/vposr.htm @@ -0,0 +1,22 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +VPOSR 004 R A( E ) Read vertical most significant bit + (and frame flop) +VPOSW 02A W A Write vertical most significant bit + (and frame flop) + + BIT# 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00 + ----------------------------------------------- + USE LOF-- -- -- -- -- -- --,-- -- -- -- -- -- -- V8 + + LOF=Long frame (auto toggle control bit in BPLCON0 ) + ++ + \ No newline at end of file diff --git a/sources/official/saga-registers/vsstrt.htm b/sources/official/saga-registers/vsstrt.htm new file mode 100755 index 0000000..5f82938 --- /dev/null +++ b/sources/official/saga-registers/vsstrt.htm @@ -0,0 +1,16 @@ + + +
+ + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +VSSTOP 1CA W A( E ) Vertical line position for VSYNC stop +VSSTRT 1E0 W A( E ) Vertical sync start (VARVSY) +VTOTAL 1C8 W A( E ) Highest numbered vertical line + (VARBEAMEN=1) + ++ + diff --git a/sources/official/saga-registers/vtotal.htm b/sources/official/saga-registers/vtotal.htm new file mode 100755 index 0000000..167deda --- /dev/null +++ b/sources/official/saga-registers/vtotal.htm @@ -0,0 +1,21 @@ + + +
+ + + Agnus/ + Read/ Denise/ +Register Address Write Paula Function +-------- ------- ----- ------- -------- +HBSTOP 1C6 W A( E ) Horizontal line position for HBLANK stop +HBSTRT 1C4 W A( E ) Horizontal line position for HBLANK start +HCENTER 1E2 W A( E ) Horizontal position for Vsync on interlace +HSSTOP 1C2 W A( E ) Horizontal line position for HSYNC stop +HSSTRT 1DE W A( E ) Horizontal sync start (VARHSY) +HTOTAL 1C0 W A( E ) Highest number count, horiz. line + (VARBEAMEN=1) + + ++ + diff --git a/tools/intake/sagaregs.py b/tools/intake/sagaregs.py new file mode 100644 index 0000000..4c9148a --- /dev/null +++ b/tools/intake/sagaregs.py @@ -0,0 +1,1027 @@ +#!/usr/bin/env python3 +"""Document intake: convert the SAGA register documentation +(sources/official/saga-registers/, HTML) into core/saga-registers/. + + sagaregs.py regenerate core/saga-registers/ + sagaregs.py --check exit 1 if the generated files are out of date + +The HTML is leading (CONTRIBUTING.md section 11). Never edit the generated +files: change the original, or this script, and regenerate. Uses only the +Python standard library. + +The original is a register table (index.htm) with one page per register or +register group. This script takes only the SAGA-specific registers (the rows +where OCS, ECS and AGA are empty, plus the SAGA addresses listed in +EXTRA_ROWS), skips the Atari section, and applies the corrections in +CORRECTIONS. Facts that the original lacks come from ADDITIONS, each with +its source tag. Both lists are printed in core/saga-registers/index.md. +""" +import html +import os +import re +import sys + +ROOT = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..")) +SRCDIR = "sources/official/saga-registers" +SOURCE = f"{SRCDIR}/index.htm" +OUTDIR = "core/saga-registers" +OWNER = "WDrijver" +CORE = "Core 12000+" +SOURCE_NAME = "SAGA register documentation, sources/official/saga-registers/ (HTML)" +WD = "WDrijver (maintainer), answers on the SAGA register documentation, 2026-11-04" +WDS = "WDrijver, 2026-11-04" +BIGGUN = "Gunnar (core developer, BigGun), Apollo chat, 2026-11-04 (relayed by WDrijver)" +BGS = "G, 2026-11-04" +APOLLOLIB = ("ApolloLib, github.com/WDrijver/ApolloCrossDev Projects/ApolloLib " + "(ApolloCrossDev_Defines.h, ApolloCrossDev_LibC.c), commit 2dfaa5c (2026-09-02)") +APOLLOLIB_OLD = ("ApolloLib, older copy in ApolloClaude docs/toolchain/_ApolloLib " + "(ApolloCrossDev_Defines.h), 2026-11-04") +EX_PIP = ("Example SAGAPiP.c, github.com/WDrijver/ApolloCrossDev Projects/SAGAPiP, " + "commit 2dfaa5c (2026-09-02)") +EX_POINTER = ("Example ApolloPointer.c, github.com/WDrijver/ApolloCrossDev " + "Projects/ApolloPointer, commit 2dfaa5c (2026-09-02)") +APOLLOOS = ("ApolloOS source, github.com/ApolloTeam-dev/ApolloOS.R10 " + "arch/m68k-amiga/hidd/sagagfx/sagagfx_hw.h, commit ca5ef46 (2025-06-10)") +MAGGIE = "maggie.library samples, see os/libraries/maggie-library.md" + +ACCESS = {"R": "read", "W": "write", "S": "strobe (a write of any value " + "triggers the action)", "ER": "early read", + "R/W": "read and write (used in the original's Atari section, and here " + "for `$DFF3EE`)"} + + +# ------------------------------------------------------------ the original + +def read(name): + with open(os.path.join(ROOT, SRCDIR, name), encoding="latin-1") as f: + return f.read() + + +def index_rows(): + """The rows of index.htm: (address, name, page, access, flags, description). + flags is the set of chipsets marked with '*'. Stops at the Atari section.""" + rows = [] + for part in re.split(r"